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5191 | serge | 1 | /* cr16.h -- Header file for CR16 opcode and register tables. |
6324 | serge | 2 | Copyright (C) 2007-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Contributed by M R Swami Reddy |
4 | |||
5 | This file is part of GAS, GDB and the GNU binutils. |
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6 | |||
7 | GAS, GDB, and GNU binutils is free software; you can redistribute it |
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8 | and/or modify it under the terms of the GNU General Public License as |
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9 | published by the Free Software Foundation; either version 3, or (at your |
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10 | option) any later version. |
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11 | |||
12 | GAS, GDB, and GNU binutils are distributed in the hope that they will be |
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13 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this program; if not, write to the Free Software Foundation, |
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19 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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20 | |||
21 | #ifndef _CR16_H_ |
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22 | #define _CR16_H_ |
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23 | |||
24 | /* CR16 core Registers : |
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25 | The enums are used as indices to CR16 registers table (cr16_regtab). |
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26 | Therefore, order MUST be preserved. */ |
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27 | |||
28 | typedef enum |
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29 | { |
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30 | /* 16-bit general purpose registers. */ |
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31 | r0, r1, r2, r3, |
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32 | r4, r5, r6, r7, |
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33 | r8, r9, r10, r11, |
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34 | r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, |
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35 | |||
36 | /* 32-bit general purpose registers. */ |
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37 | r12 = 12, r13 = 13, r14 = 14, r15 = 15, |
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38 | era = 14, sp = 15, RA, |
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39 | |||
40 | /* Not a register. */ |
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41 | nullregister, |
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42 | MAX_REG |
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43 | } |
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44 | reg; |
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45 | |||
46 | /* CR16 processor registers and special registers : |
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47 | The enums are used as indices to CR16 processor registers table |
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48 | (cr16_pregtab). Therefore, order MUST be preserved. */ |
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49 | |||
50 | typedef enum |
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51 | { |
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52 | /* processor registers. */ |
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53 | dbs = MAX_REG, |
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54 | dsr, dcrl, dcrh, |
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55 | car0l, car0h, car1l, car1h, |
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56 | cfg, psr, intbasel, intbaseh, |
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57 | ispl, isph, uspl, usph, |
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58 | dcr = dcrl, |
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59 | car0 = car0l, |
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60 | car1 = car1l, |
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61 | intbase = intbasel, |
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62 | isp = ispl, |
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63 | usp = uspl, |
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64 | /* Not a processor register. */ |
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65 | nullpregister = usph + 1, |
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66 | MAX_PREG |
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67 | } |
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68 | preg; |
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69 | |||
70 | /* CR16 Register types. */ |
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71 | |||
72 | typedef enum |
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73 | { |
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74 | CR16_R_REGTYPE, /* r |
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75 | CR16_RP_REGTYPE, /* reg pair */ |
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76 | CR16_P_REGTYPE /* Processor register */ |
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77 | } |
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78 | reg_type; |
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79 | |||
80 | /* CR16 argument types : |
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81 | The argument types correspond to instructions operands |
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82 | |||
83 | Argument types : |
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84 | r - register |
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85 | rp - register pair |
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86 | c - constant |
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87 | i - immediate |
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88 | idxr - index with register |
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89 | idxrp - index with register pair |
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90 | rbase - register base |
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91 | rpbase - register pair base |
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92 | pr - processor register. */ |
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93 | |||
94 | typedef enum |
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95 | { |
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96 | arg_r, |
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97 | arg_c, |
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98 | arg_cr, |
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99 | arg_crp, |
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100 | arg_ic, |
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101 | arg_icr, |
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102 | arg_idxr, |
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103 | arg_idxrp, |
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104 | arg_rbase, |
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105 | arg_rpbase, |
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106 | arg_rp, |
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107 | arg_pr, |
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108 | arg_prp, |
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109 | arg_cc, |
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110 | arg_ra, |
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111 | /* Not an argument. */ |
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112 | nullargs |
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113 | } |
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114 | argtype; |
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115 | |||
116 | /* CR16 operand types:The operand types correspond to instructions operands. */ |
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117 | |||
118 | typedef enum |
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119 | { |
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120 | dummy, |
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121 | /* N-bit signed immediate. */ |
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122 | imm3, imm4, imm5, imm6, imm16, imm20, imm32, |
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123 | /* N-bit unsigned immediate. */ |
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124 | uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, |
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125 | /* N-bit signed displacement. */ |
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126 | disps5, disps17, disps25, |
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127 | /* N-bit unsigned displacement. */ |
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128 | dispe9, |
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129 | /* N-bit absolute address. */ |
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130 | abs20, abs24, |
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131 | /* Register relative. */ |
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132 | rra, rbase, rbase_disps20, rbase_dispe20, |
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133 | /* Register pair relative. */ |
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134 | rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, |
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135 | rpbase_disps20, rpbase_dispe20, |
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136 | /* Register index. */ |
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137 | rindex7_abs20, rindex8_abs20, |
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138 | /* Register pair index. */ |
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139 | rpindex_disps0, rpindex_disps14, rpindex_disps20, |
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140 | /* register. */ |
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141 | regr, |
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142 | /* register pair. */ |
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143 | regp, |
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144 | /* processor register. */ |
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145 | pregr, |
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146 | /* processor register 32 bit. */ |
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147 | pregrp, |
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148 | /* condition code - 4 bit. */ |
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149 | cc, |
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150 | /* Not an operand. */ |
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151 | nulloperand, |
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152 | /* Maximum supported operand. */ |
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153 | MAX_OPRD |
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154 | } |
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155 | operand_type; |
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156 | |||
157 | /* CR16 instruction types. */ |
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158 | |||
159 | #define NO_TYPE_INS 0 |
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160 | #define ARITH_INS 1 |
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161 | #define LD_STOR_INS 2 |
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162 | #define BRANCH_INS 3 |
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163 | #define ARITH_BYTE_INS 4 |
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164 | #define SHIFT_INS 5 |
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165 | #define BRANCH_NEQ_INS 6 |
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166 | #define LD_STOR_INS_INC 7 |
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167 | #define STOR_IMM_INS 8 |
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168 | #define CSTBIT_INS 9 |
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169 | |||
170 | /* Maximum value supported for instruction types. */ |
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171 | #define CR16_INS_MAX (1 << 4) |
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172 | /* Mask to record an instruction type. */ |
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173 | #define CR16_INS_MASK (CR16_INS_MAX - 1) |
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174 | /* Return instruction type, given instruction's attributes. */ |
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175 | #define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) |
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176 | |||
177 | /* Indicates whether this instruction has a register list as parameter. */ |
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178 | #define REG_LIST CR16_INS_MAX |
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179 | |||
180 | /* The operands in binary and assembly are placed in reverse order. |
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181 | load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ |
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182 | #define REVERSE_MATCH (1 << 5) |
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183 | |||
184 | /* Printing formats, where the instruction prefix isn't consecutive. */ |
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185 | #define FMT_1 (1 << 9) /* 0xF0F00000 */ |
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186 | #define FMT_2 (1 << 10) /* 0xFFF0FF00 */ |
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187 | #define FMT_3 (1 << 11) /* 0xFFF00F00 */ |
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188 | #define FMT_4 (1 << 12) /* 0xFFF0F000 */ |
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189 | #define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ |
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190 | #define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) |
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191 | |||
192 | /* Indicates whether this instruction can be relaxed. */ |
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193 | #define RELAXABLE (1 << 14) |
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194 | |||
195 | /* Indicates that instruction uses user registers (and not |
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196 | general-purpose registers) as operands. */ |
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197 | #define USER_REG (1 << 15) |
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198 | |||
199 | |||
200 | /* Instruction shouldn't allow 'sp' usage. */ |
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201 | #define NO_SP (1 << 17) |
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202 | |||
203 | /* Instruction shouldn't allow to push a register which is used as a rptr. */ |
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204 | #define NO_RPTR (1 << 18) |
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205 | |||
206 | /* Maximum operands per instruction. */ |
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207 | #define MAX_OPERANDS 5 |
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208 | /* Maximum register name length. */ |
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209 | #define MAX_REGNAME_LEN 10 |
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210 | /* Maximum instruction length. */ |
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211 | #define MAX_INST_LEN 256 |
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212 | |||
213 | |||
214 | /* Values defined for the flags field of a struct operand_entry. */ |
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215 | |||
216 | /* Operand must be an unsigned number. */ |
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217 | #define OP_UNSIGNED (1 << 0) |
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218 | /* Operand must be a signed number. */ |
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219 | #define OP_SIGNED (1 << 1) |
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220 | /* Operand must be a negative number. */ |
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221 | #define OP_NEG (1 << 2) |
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222 | /* A special load/stor 4-bit unsigned displacement operand. */ |
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223 | #define OP_DEC (1 << 3) |
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224 | /* Operand must be an even number. */ |
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225 | #define OP_EVEN (1 << 4) |
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226 | /* Operand is shifted right. */ |
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227 | #define OP_SHIFT (1 << 5) |
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228 | /* Operand is shifted right and decremented. */ |
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229 | #define OP_SHIFT_DEC (1 << 6) |
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230 | /* Operand has reserved escape sequences. */ |
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231 | #define OP_ESC (1 << 7) |
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232 | /* Operand must be a ABS20 number. */ |
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233 | #define OP_ABS20 (1 << 8) |
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234 | /* Operand must be a ABS24 number. */ |
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235 | #define OP_ABS24 (1 << 9) |
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236 | /* Operand has reserved escape sequences type 1. */ |
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237 | #define OP_ESC1 (1 << 10) |
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238 | |||
239 | /* Single operand description. */ |
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240 | |||
241 | typedef struct |
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242 | { |
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243 | /* Operand type. */ |
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244 | operand_type op_type; |
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245 | /* Operand location within the opcode. */ |
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246 | unsigned int shift; |
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247 | } |
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248 | operand_desc; |
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249 | |||
250 | /* Instruction data structure used in instruction table. */ |
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251 | |||
252 | typedef struct |
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253 | { |
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254 | /* Name. */ |
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255 | const char *mnemonic; |
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256 | /* Size (in words). */ |
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257 | unsigned int size; |
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258 | /* Constant prefix (matched by the disassembler). */ |
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259 | unsigned long match; /* ie opcode */ |
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260 | /* Match size (in bits). */ |
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261 | /* MASK: if( (i & match_bits) == match ) then match */ |
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262 | int match_bits; |
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263 | /* Attributes. */ |
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264 | unsigned int flags; |
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265 | /* Operands (always last, so unreferenced operands are initialized). */ |
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266 | operand_desc operands[MAX_OPERANDS]; |
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267 | } |
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268 | inst; |
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269 | |||
270 | /* Data structure for a single instruction's arguments (Operands). */ |
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271 | |||
272 | typedef struct |
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273 | { |
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274 | /* Register or base register. */ |
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275 | reg r; |
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276 | /* Register pair register. */ |
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277 | reg rp; |
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278 | /* Index register. */ |
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279 | reg i_r; |
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280 | /* Processor register. */ |
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281 | preg pr; |
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282 | /* Processor register. 32 bit */ |
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283 | preg prp; |
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284 | /* Constant/immediate/absolute value. */ |
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285 | long constant; |
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286 | /* CC code. */ |
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287 | unsigned int cc; |
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288 | /* Scaled index mode. */ |
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289 | unsigned int scale; |
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290 | /* Argument type. */ |
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291 | argtype type; |
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292 | /* Size of the argument (in bits) required to represent. */ |
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293 | int size; |
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294 | /* The type of the expression. */ |
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295 | unsigned char X_op; |
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296 | } |
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297 | argument; |
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298 | |||
299 | /* Internal structure to hold the various entities |
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300 | corresponding to the current assembling instruction. */ |
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301 | |||
302 | typedef struct |
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303 | { |
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304 | /* Number of arguments. */ |
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305 | int nargs; |
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306 | /* The argument data structure for storing args (operands). */ |
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307 | argument arg[MAX_OPERANDS]; |
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308 | /* The following fields are required only by CR16-assembler. */ |
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309 | #ifdef TC_CR16 |
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310 | /* Expression used for setting the fixups (if any). */ |
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311 | expressionS exp; |
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312 | bfd_reloc_code_real_type rtype; |
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313 | #endif /* TC_CR16 */ |
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314 | /* Instruction size (in bytes). */ |
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315 | int size; |
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316 | } |
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317 | ins; |
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318 | |||
319 | /* Structure to hold information about predefined operands. */ |
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320 | |||
321 | typedef struct |
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322 | { |
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323 | /* Size (in bits). */ |
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324 | unsigned int bit_size; |
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325 | /* Argument type. */ |
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326 | argtype arg_type; |
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327 | /* One bit syntax flags. */ |
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328 | int flags; |
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329 | } |
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330 | operand_entry; |
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331 | |||
332 | /* Structure to hold trap handler information. */ |
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333 | |||
334 | typedef struct |
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335 | { |
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336 | /* Trap name. */ |
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337 | char *name; |
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338 | /* Index in dispatch table. */ |
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339 | unsigned int entry; |
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340 | } |
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341 | trap_entry; |
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342 | |||
343 | /* Structure to hold information about predefined registers. */ |
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344 | |||
345 | typedef struct |
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346 | { |
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347 | /* Name (string representation). */ |
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348 | char *name; |
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349 | /* Value (enum representation). */ |
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350 | union |
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351 | { |
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352 | /* Register. */ |
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353 | reg reg_val; |
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354 | /* processor register. */ |
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355 | preg preg_val; |
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356 | } value; |
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357 | /* Register image. */ |
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358 | int image; |
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359 | /* Register type. */ |
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360 | reg_type type; |
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361 | } |
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362 | reg_entry; |
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363 | |||
364 | /* CR16 opcode table. */ |
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365 | extern const inst cr16_instruction[]; |
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366 | extern const unsigned int cr16_num_opcodes; |
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367 | #define NUMOPCODES cr16_num_opcodes |
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368 | |||
369 | /* CR16 operands table. */ |
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370 | extern const operand_entry cr16_optab[]; |
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371 | extern const unsigned int cr16_num_optab; |
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372 | |||
373 | /* CR16 registers table. */ |
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374 | extern const reg_entry cr16_regtab[]; |
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375 | extern const unsigned int cr16_num_regs; |
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376 | #define NUMREGS cr16_num_regs |
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377 | |||
378 | /* CR16 register pair table. */ |
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379 | extern const reg_entry cr16_regptab[]; |
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380 | extern const unsigned int cr16_num_regps; |
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381 | #define NUMREGPS cr16_num_regps |
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382 | |||
383 | /* CR16 processor registers table. */ |
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384 | extern const reg_entry cr16_pregtab[]; |
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385 | extern const unsigned int cr16_num_pregs; |
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386 | #define NUMPREGS cr16_num_pregs |
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387 | |||
388 | /* CR16 processor registers - 32 bit table. */ |
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389 | extern const reg_entry cr16_pregptab[]; |
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390 | extern const unsigned int cr16_num_pregps; |
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391 | #define NUMPREGPS cr16_num_pregps |
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392 | |||
393 | /* CR16 trap/interrupt table. */ |
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394 | extern const trap_entry cr16_traps[]; |
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395 | extern const unsigned int cr16_num_traps; |
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396 | #define NUMTRAPS cr16_num_traps |
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397 | |||
398 | /* CR16 CC - codes bit table. */ |
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399 | extern const char * cr16_b_cond_tab[]; |
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400 | extern const unsigned int cr16_num_cc; |
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401 | #define NUMCC cr16_num_cc; |
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402 | |||
403 | |||
404 | /* Table of instructions with no operands. */ |
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405 | extern const char * cr16_no_op_insn[]; |
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406 | |||
407 | /* Current instruction we're assembling. */ |
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408 | extern const inst *instruction; |
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409 | |||
410 | /* A macro for representing the instruction "constant" opcode, that is, |
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411 | the FIXED part of the instruction. The "constant" opcode is represented |
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412 | as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) |
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413 | over that range. */ |
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414 | #define BIN(OPC,SHIFT) (OPC << SHIFT) |
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415 | |||
416 | /* Is the current instruction type is TYPE ? */ |
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417 | #define IS_INSN_TYPE(TYPE) \ |
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418 | (CR16_INS_TYPE (instruction->flags) == TYPE) |
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419 | |||
420 | /* Is the current instruction mnemonic is MNEMONIC ? */ |
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421 | #define IS_INSN_MNEMONIC(MNEMONIC) \ |
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422 | (strcmp (instruction->mnemonic, MNEMONIC) == 0) |
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423 | |||
424 | /* Does the current instruction has register list ? */ |
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425 | #define INST_HAS_REG_LIST \ |
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426 | (instruction->flags & REG_LIST) |
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427 | |||
428 | |||
429 | /* Utility macros for string comparison. */ |
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430 | #define streq(a, b) (strcmp (a, b) == 0) |
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431 | #define strneq(a, b, c) (strncmp (a, b, c) == 0) |
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432 | |||
433 | /* Long long type handling. */ |
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434 | /* Replace all appearances of 'long long int' with LONGLONG. */ |
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435 | typedef long long int LONGLONG; |
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436 | typedef unsigned long long ULONGLONG; |
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437 | |||
438 | /* Data types for opcode handling. */ |
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439 | typedef unsigned long dwordU; |
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440 | typedef unsigned short wordU; |
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441 | |||
442 | /* Globals to store opcode data and build the instruction. */ |
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443 | extern wordU cr16_words[3]; |
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444 | extern ULONGLONG cr16_allWords; |
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445 | extern ins cr16_currInsn; |
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446 | |||
447 | /* Prototypes for function in cr16-dis.c. */ |
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448 | extern void cr16_make_instruction (void); |
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449 | extern int cr16_match_opcode (void); |
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450 | |||
451 | #endif /* _CR16_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |