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Rev | Author | Line No. | Line |
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5191 | serge | 1 | /* Header file for targets using CGEN: Cpu tools GENerator. |
2 | |||
6324 | serge | 3 | Copyright (C) 1996-2015 Free Software Foundation, Inc. |
5191 | serge | 4 | |
5 | This file is part of GDB, the GNU debugger, and the GNU Binutils. |
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6 | |||
7 | This program is free software; you can redistribute it and/or modify |
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8 | it under the terms of the GNU General Public License as published by |
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9 | the Free Software Foundation; either version 3 of the License, or |
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10 | (at your option) any later version. |
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11 | |||
12 | This program is distributed in the hope that it will be useful, |
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13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License along |
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18 | with this program; if not, write to the Free Software Foundation, Inc., |
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19 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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20 | |||
21 | #ifndef OPCODE_CGEN_H |
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22 | #define OPCODE_CGEN_H |
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23 | |||
24 | #include "symcat.h" |
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25 | #include "cgen/bitset.h" |
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26 | |||
27 | /* ??? IWBN to replace bfd in the name. */ |
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28 | #include "bfd_stdint.h" |
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29 | |||
6324 | serge | 30 | #ifdef __cplusplus |
31 | extern "C" { |
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32 | #endif |
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33 | |||
5191 | serge | 34 | /* ??? This file requires bfd.h but only to get bfd_vma. |
35 | Seems like an awful lot to require just to get such a fundamental type. |
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36 | Perhaps the definition of bfd_vma can be moved outside of bfd.h. |
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37 | Or perhaps one could duplicate its definition in another file. |
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38 | Until such time, this file conditionally compiles definitions that require |
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39 | bfd_vma using __BFD_H_SEEN__. */ |
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40 | |||
41 | /* Enums must be defined before they can be used. |
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42 | Allow them to be used in struct definitions, even though the enum must |
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43 | be defined elsewhere. |
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44 | If CGEN_ARCH isn't defined, this file is being included by something other |
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45 | than |
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46 | |||
47 | /* Prepend the arch name, defined in |
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48 | The lack of spaces in the arg list is important for non-stdc systems. |
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49 | This file is included by |
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50 | It can be included independently of |
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51 | dependent portions will be declared as "unknown_cgen_foo". */ |
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52 | |||
53 | #ifndef CGEN_SYM |
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54 | #define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) |
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55 | #endif |
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56 | |||
57 | /* This file contains the static (unchanging) pieces and as much other stuff |
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58 | as we can reasonably put here. It's generally cleaner to put stuff here |
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59 | rather than having it machine generated if possible. */ |
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60 | |||
61 | /* The assembler syntax is made up of expressions (duh...). |
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62 | At the lowest level the values are mnemonics, register names, numbers, etc. |
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63 | Above that are subexpressions, if any (an example might be the |
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64 | "effective address" in m68k cpus). Subexpressions are wip. |
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65 | At the second highest level are the insns themselves. Above that are |
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66 | pseudo-insns, synthetic insns, and macros, if any. */ |
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67 | |||
68 | /* Lots of cpu's have a fixed insn size, or one which rarely changes, |
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69 | and it's generally easier to handle these by treating the insn as an |
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70 | integer type, rather than an array of characters. So we allow targets |
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71 | to control this. When an integer type the value is in host byte order, |
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72 | when an array of characters the value is in target byte order. */ |
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73 | |||
74 | typedef unsigned int CGEN_INSN_INT; |
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75 | typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */ |
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76 | typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */ |
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77 | |||
78 | #if CGEN_INT_INSN_P |
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79 | typedef CGEN_INSN_INT CGEN_INSN_BYTES; |
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80 | typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; |
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81 | #else |
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82 | typedef unsigned char *CGEN_INSN_BYTES; |
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83 | typedef unsigned char *CGEN_INSN_BYTES_PTR; |
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84 | #endif |
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85 | |||
86 | #ifdef __GNUC__ |
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87 | #define CGEN_INLINE __inline__ |
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88 | #else |
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89 | #define CGEN_INLINE |
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90 | #endif |
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91 | |||
92 | enum cgen_endian |
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93 | { |
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94 | CGEN_ENDIAN_UNKNOWN, |
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95 | CGEN_ENDIAN_LITTLE, |
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96 | CGEN_ENDIAN_BIG |
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97 | }; |
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98 | |||
99 | /* Forward decl. */ |
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100 | |||
101 | typedef struct cgen_insn CGEN_INSN; |
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102 | |||
103 | /* Opaque pointer version for use by external world. */ |
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104 | |||
105 | typedef struct cgen_cpu_desc *CGEN_CPU_DESC; |
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106 | |||
107 | /* Attributes. |
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108 | Attributes are used to describe various random things associated with |
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109 | an object (ifield, hardware, operand, insn, whatever) and are specified |
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110 | as name/value pairs. |
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111 | Integer attributes computed at compile time are currently all that's |
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112 | supported, though adding string attributes and run-time computation is |
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113 | straightforward. Integer attribute values are always host int's |
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114 | (signed or unsigned). For portability, this means 32 bits. |
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115 | Integer attributes are further categorized as boolean, bitset, integer, |
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116 | and enum types. Boolean attributes appear frequently enough that they're |
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117 | recorded in one host int. This limits the maximum number of boolean |
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118 | attributes to 32, though that's a *lot* of attributes. */ |
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119 | |||
120 | /* Type of attribute values. */ |
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121 | |||
122 | typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; |
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123 | typedef int CGEN_ATTR_VALUE_ENUM_TYPE; |
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124 | typedef union |
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125 | { |
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126 | CGEN_ATTR_VALUE_BITSET_TYPE bitset; |
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127 | CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; |
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128 | } CGEN_ATTR_VALUE_TYPE; |
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129 | |||
130 | /* Struct to record attribute information. */ |
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131 | |||
132 | typedef struct |
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133 | { |
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134 | /* Boolean attributes. */ |
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135 | unsigned int bool_; |
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136 | /* Non-boolean integer attributes. */ |
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137 | CGEN_ATTR_VALUE_TYPE nonbool[1]; |
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138 | } CGEN_ATTR; |
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139 | |||
140 | /* Define a structure member for attributes with N non-boolean entries. |
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141 | There is no maximum number of non-boolean attributes. |
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142 | There is a maximum of 32 boolean attributes (since they are all recorded |
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143 | in one host int). */ |
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144 | |||
145 | #define CGEN_ATTR_TYPE(n) \ |
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146 | struct { unsigned int bool_; \ |
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147 | CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } |
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148 | |||
149 | /* Return the boolean attributes. */ |
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150 | |||
151 | #define CGEN_ATTR_BOOLS(a) ((a)->bool_) |
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152 | |||
153 | /* Non-boolean attribute numbers are offset by this much. */ |
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154 | |||
155 | #define CGEN_ATTR_NBOOL_OFFSET 32 |
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156 | |||
157 | /* Given a boolean attribute number, return its mask. */ |
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158 | |||
159 | #define CGEN_ATTR_MASK(attr) (1 << (attr)) |
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160 | |||
161 | /* Return the value of boolean attribute ATTR in ATTRS. */ |
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162 | |||
163 | #define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) |
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164 | |||
165 | /* Return value of attribute ATTR in ATTR_TABLE for OBJ. |
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166 | OBJ is a pointer to the entity that has the attributes |
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167 | (??? not used at present but is reserved for future purposes - eventually |
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168 | the goal is to allow recording attributes in source form and computing |
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169 | them lazily at runtime, not sure of the details yet). */ |
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170 | |||
171 | #define CGEN_ATTR_VALUE(obj, attr_table, attr) \ |
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172 | ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ |
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173 | ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ |
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174 | : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) |
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175 | #define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ |
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176 | ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) |
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177 | |||
178 | /* Attribute name/value tables. |
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179 | These are used to assist parsing of descriptions at run-time. */ |
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180 | |||
181 | typedef struct |
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182 | { |
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183 | const char * name; |
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184 | unsigned value; |
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185 | } CGEN_ATTR_ENTRY; |
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186 | |||
187 | /* For each domain (ifld,hw,operand,insn), list of attributes. */ |
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188 | |||
189 | typedef struct |
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190 | { |
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191 | const char * name; |
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192 | const CGEN_ATTR_ENTRY * dfault; |
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193 | const CGEN_ATTR_ENTRY * vals; |
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194 | } CGEN_ATTR_TABLE; |
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195 | |||
196 | /* Instruction set variants. */ |
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197 | |||
198 | typedef struct { |
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199 | const char *name; |
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200 | |||
201 | /* Default instruction size (in bits). |
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202 | This is used by the assembler when it encounters an unknown insn. */ |
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203 | unsigned int default_insn_bitsize; |
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204 | |||
205 | /* Base instruction size (in bits). |
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206 | For non-LIW cpus this is generally the length of the smallest insn. |
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207 | For LIW cpus its wip (work-in-progress). For the m32r its 32. */ |
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208 | unsigned int base_insn_bitsize; |
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209 | |||
210 | /* Minimum/maximum instruction size (in bits). */ |
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211 | unsigned int min_insn_bitsize; |
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212 | unsigned int max_insn_bitsize; |
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213 | } CGEN_ISA; |
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214 | |||
215 | /* Machine variants. */ |
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216 | |||
217 | typedef struct { |
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218 | const char *name; |
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219 | /* The argument to bfd_arch_info->scan. */ |
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220 | const char *bfd_name; |
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221 | /* one of enum mach_attr */ |
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222 | int num; |
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223 | /* parameter from mach->cpu */ |
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224 | unsigned int insn_chunk_bitsize; |
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225 | } CGEN_MACH; |
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226 | |||
227 | /* Parse result (also extraction result). |
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228 | |||
229 | The result of parsing an insn is stored here. |
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230 | To generate the actual insn, this is passed to the insert handler. |
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231 | When printing an insn, the result of extraction is stored here. |
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232 | To print the insn, this is passed to the print handler. |
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233 | |||
234 | It is machine generated so we don't define it here, |
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235 | but we do need a forward decl for the handler fns. |
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236 | |||
237 | There is one member for each possible field in the insn. |
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238 | The type depends on the field. |
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239 | Also recorded here is the computed length of the insn for architectures |
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240 | where it varies. |
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241 | */ |
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242 | |||
243 | typedef struct cgen_fields CGEN_FIELDS; |
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244 | |||
245 | /* Total length of the insn, as recorded in the `fields' struct. */ |
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246 | /* ??? The field insert handler has lots of opportunities for optimization |
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247 | if it ever gets inlined. On architectures where insns all have the same |
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248 | size, may wish to detect that and make this macro a constant - to allow |
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249 | further optimizations. */ |
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250 | |||
251 | #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) |
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252 | |||
253 | /* Extraction support for variable length insn sets. */ |
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254 | |||
255 | /* When disassembling we don't know the number of bytes to read at the start. |
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256 | So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest |
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257 | are read when needed. This struct controls this. It is basically the |
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258 | disassemble_info stuff, except that we provide a cache for values already |
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259 | read (since bytes can typically be read several times to fetch multiple |
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260 | operands that may be in them), and that extraction of fields is needed |
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261 | in contexts other than disassembly. */ |
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262 | |||
263 | typedef struct { |
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264 | /* A pointer to the disassemble_info struct. |
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265 | We don't require dis-asm.h so we use void * for the type here. |
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266 | If NULL, BYTES is full of valid data (VALID == -1). */ |
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267 | void *dis_info; |
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268 | /* Points to a working buffer of sufficient size. */ |
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269 | unsigned char *insn_bytes; |
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270 | /* Mask of bytes that are valid in INSN_BYTES. */ |
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271 | unsigned int valid; |
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272 | } CGEN_EXTRACT_INFO; |
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273 | |||
274 | /* Associated with each insn or expression is a set of "handlers" for |
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275 | performing operations like parsing, printing, etc. These require a bfd_vma |
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276 | value to be passed around but we don't want all applications to need bfd.h. |
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277 | So this stuff is only provided if bfd.h has been included. */ |
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278 | |||
279 | /* Parse handler. |
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280 | CD is a cpu table descriptor. |
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281 | INSN is a pointer to a struct describing the insn being parsed. |
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282 | STRP is a pointer to a pointer to the text being parsed. |
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283 | FIELDS is a pointer to a cgen_fields struct in which the results are placed. |
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284 | If the expression is successfully parsed, *STRP is updated. |
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285 | If not it is left alone. |
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286 | The result is NULL if success or an error message. */ |
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287 | typedef const char * (cgen_parse_fn) |
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288 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
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289 | const char **strp_, CGEN_FIELDS *fields_); |
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290 | |||
291 | /* Insert handler. |
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292 | CD is a cpu table descriptor. |
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293 | INSN is a pointer to a struct describing the insn being parsed. |
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294 | FIELDS is a pointer to a cgen_fields struct from which the values |
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295 | are fetched. |
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296 | INSNP is a pointer to a buffer in which to place the insn. |
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297 | PC is the pc value of the insn. |
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298 | The result is an error message or NULL if success. */ |
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299 | |||
300 | #ifdef __BFD_H_SEEN__ |
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301 | typedef const char * (cgen_insert_fn) |
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302 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
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303 | CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, |
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304 | bfd_vma pc_); |
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305 | #else |
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306 | typedef const char * (cgen_insert_fn) (); |
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307 | #endif |
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308 | |||
309 | /* Extract handler. |
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310 | CD is a cpu table descriptor. |
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311 | INSN is a pointer to a struct describing the insn being parsed. |
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312 | The second argument is a pointer to a struct controlling extraction |
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313 | (only used for variable length insns). |
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314 | EX_INFO is a pointer to a struct for controlling reading of further |
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315 | bytes for the insn. |
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316 | BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). |
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317 | FIELDS is a pointer to a cgen_fields struct in which the results are placed. |
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318 | PC is the pc value of the insn. |
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319 | The result is the length of the insn in bits or zero if not recognized. */ |
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320 | |||
321 | #ifdef __BFD_H_SEEN__ |
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322 | typedef int (cgen_extract_fn) |
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323 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
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324 | CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, |
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325 | CGEN_FIELDS *fields_, bfd_vma pc_); |
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326 | #else |
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327 | typedef int (cgen_extract_fn) (); |
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328 | #endif |
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329 | |||
330 | /* Print handler. |
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331 | CD is a cpu table descriptor. |
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332 | INFO is a pointer to the disassembly info. |
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333 | Eg: disassemble_info. It's defined as `PTR' so this file can be included |
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334 | without dis-asm.h. |
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335 | INSN is a pointer to a struct describing the insn being printed. |
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336 | FIELDS is a pointer to a cgen_fields struct. |
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337 | PC is the pc value of the insn. |
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338 | LEN is the length of the insn, in bits. */ |
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339 | |||
340 | #ifdef __BFD_H_SEEN__ |
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341 | typedef void (cgen_print_fn) |
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342 | (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, |
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343 | CGEN_FIELDS *fields_, bfd_vma pc_, int len_); |
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344 | #else |
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345 | typedef void (cgen_print_fn) (); |
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346 | #endif |
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347 | |||
348 | /* Parse/insert/extract/print handlers. |
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349 | |||
350 | Indices into the handler tables. |
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351 | We could use pointers here instead, but 90% of them are generally identical |
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352 | and that's a lot of redundant data. Making these unsigned char indices |
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353 | into tables of pointers saves a bit of space. |
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354 | Using indices also keeps assembler code out of the disassembler and |
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355 | vice versa. */ |
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356 | |||
357 | struct cgen_opcode_handler |
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358 | { |
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359 | unsigned char parse, insert, extract, print; |
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360 | }; |
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361 | |||
362 | /* Assembler interface. |
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363 | |||
364 | The interface to the assembler is intended to be clean in the sense that |
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365 | libopcodes.a is a standalone entity and could be used with any assembler. |
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366 | Not that one would necessarily want to do that but rather that it helps |
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367 | keep a clean interface. The interface will obviously be slanted towards |
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368 | GAS, but at least it's a start. |
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369 | ??? Note that one possible user of the assembler besides GAS is GDB. |
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370 | |||
371 | Parsing is controlled by the assembler which calls |
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372 | CGEN_SYM (assemble_insn). If it can parse and build the entire insn |
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373 | it doesn't call back to the assembler. If it needs/wants to call back |
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374 | to the assembler, cgen_parse_operand_fn is called which can either |
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375 | |||
376 | - return a number to be inserted in the insn |
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377 | - return a "register" value to be inserted |
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378 | (the register might not be a register per pe) |
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379 | - queue the argument and return a marker saying the expression has been |
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380 | queued (eg: a fix-up) |
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381 | - return an error message indicating the expression wasn't recognizable |
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382 | |||
383 | The result is an error message or NULL for success. |
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384 | The parsed value is stored in the bfd_vma *. */ |
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385 | |||
386 | /* Values for indicating what the caller wants. */ |
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387 | |||
388 | enum cgen_parse_operand_type |
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389 | { |
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390 | CGEN_PARSE_OPERAND_INIT, |
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391 | CGEN_PARSE_OPERAND_INTEGER, |
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392 | CGEN_PARSE_OPERAND_ADDRESS, |
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393 | CGEN_PARSE_OPERAND_SYMBOLIC |
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394 | }; |
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395 | |||
396 | /* Values for indicating what was parsed. */ |
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397 | |||
398 | enum cgen_parse_operand_result |
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399 | { |
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400 | CGEN_PARSE_OPERAND_RESULT_NUMBER, |
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401 | CGEN_PARSE_OPERAND_RESULT_REGISTER, |
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402 | CGEN_PARSE_OPERAND_RESULT_QUEUED, |
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403 | CGEN_PARSE_OPERAND_RESULT_ERROR |
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404 | }; |
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405 | |||
406 | #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ |
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407 | typedef const char * (cgen_parse_operand_fn) |
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408 | (CGEN_CPU_DESC, |
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409 | enum cgen_parse_operand_type, const char **, int, int, |
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410 | enum cgen_parse_operand_result *, bfd_vma *); |
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411 | #else |
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412 | typedef const char * (cgen_parse_operand_fn) (); |
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413 | #endif |
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414 | |||
415 | /* Set the cgen_parse_operand_fn callback. */ |
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416 | |||
417 | extern void cgen_set_parse_operand_fn |
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418 | (CGEN_CPU_DESC, cgen_parse_operand_fn); |
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419 | |||
420 | /* Called before trying to match a table entry with the insn. */ |
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421 | |||
422 | extern void cgen_init_parse_operand (CGEN_CPU_DESC); |
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423 | |||
424 | /* Operand values (keywords, integers, symbols, etc.) */ |
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425 | |||
426 | /* Types of assembler elements. */ |
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427 | |||
428 | enum cgen_asm_type |
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429 | { |
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430 | CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX |
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431 | }; |
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432 | |||
433 | #ifndef CGEN_ARCH |
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434 | enum cgen_hw_type { CGEN_HW_MAX }; |
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435 | #endif |
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436 | |||
437 | /* List of hardware elements. */ |
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438 | |||
439 | typedef struct |
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440 | { |
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441 | char *name; |
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442 | enum cgen_hw_type type; |
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443 | /* There is currently no example where both index specs and value specs |
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444 | are required, so for now both are clumped under "asm_data". */ |
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445 | enum cgen_asm_type asm_type; |
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446 | void *asm_data; |
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447 | #ifndef CGEN_HW_NBOOL_ATTRS |
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448 | #define CGEN_HW_NBOOL_ATTRS 1 |
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449 | #endif |
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450 | CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; |
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451 | #define CGEN_HW_ATTRS(hw) (&(hw)->attrs) |
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452 | } CGEN_HW_ENTRY; |
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453 | |||
454 | /* Return value of attribute ATTR in HW. */ |
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455 | |||
456 | #define CGEN_HW_ATTR_VALUE(hw, attr) \ |
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457 | CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) |
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458 | |||
459 | /* Table of hardware elements for selected mach, computed at runtime. |
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460 | enum cgen_hw_type is an index into this table (specifically `entries'). */ |
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461 | |||
462 | typedef struct { |
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463 | /* Pointer to null terminated table of all compiled in entries. */ |
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464 | const CGEN_HW_ENTRY *init_entries; |
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465 | unsigned int entry_size; /* since the attribute member is variable sized */ |
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466 | /* Array of all entries, initial and run-time added. */ |
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467 | const CGEN_HW_ENTRY **entries; |
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468 | /* Number of elements in `entries'. */ |
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469 | unsigned int num_entries; |
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470 | /* For now, xrealloc is called each time a new entry is added at runtime. |
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471 | ??? May wish to keep track of some slop to reduce the number of calls to |
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472 | xrealloc, except that there's unlikely to be many and not expected to be |
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473 | in speed critical code. */ |
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474 | } CGEN_HW_TABLE; |
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475 | |||
476 | extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name |
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477 | (CGEN_CPU_DESC, const char *); |
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478 | extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num |
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479 | (CGEN_CPU_DESC, unsigned int); |
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480 | |||
481 | /* This struct is used to describe things like register names, etc. */ |
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482 | |||
483 | typedef struct cgen_keyword_entry |
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484 | { |
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485 | /* Name (as in register name). */ |
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486 | char * name; |
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487 | |||
488 | /* Value (as in register number). |
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489 | The value cannot be -1 as that is used to indicate "not found". |
||
490 | IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ |
||
491 | int value; |
||
492 | |||
493 | /* Attributes. |
||
494 | This should, but technically needn't, appear last. It is a variable sized |
||
495 | array in that one architecture may have 1 nonbool attribute and another |
||
496 | may have more. Having this last means the non-architecture specific code |
||
497 | needn't care. The goal is to eventually record |
||
498 | attributes in their raw form, evaluate them at run-time, and cache the |
||
499 | values, so this worry will go away anyway. */ |
||
500 | /* ??? Moving this last should be done by treating keywords like insn lists |
||
501 | and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ |
||
502 | /* FIXME: Not used yet. */ |
||
503 | #ifndef CGEN_KEYWORD_NBOOL_ATTRS |
||
504 | #define CGEN_KEYWORD_NBOOL_ATTRS 1 |
||
505 | #endif |
||
506 | CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; |
||
507 | |||
508 | /* ??? Putting these here means compiled in entries can't be const. |
||
509 | Not a really big deal, but something to consider. */ |
||
510 | /* Next name hash table entry. */ |
||
511 | struct cgen_keyword_entry *next_name; |
||
512 | /* Next value hash table entry. */ |
||
513 | struct cgen_keyword_entry *next_value; |
||
514 | } CGEN_KEYWORD_ENTRY; |
||
515 | |||
516 | /* Top level struct for describing a set of related keywords |
||
517 | (e.g. register names). |
||
518 | |||
519 | This struct supports run-time entry of new values, and hashed lookups. */ |
||
520 | |||
521 | typedef struct cgen_keyword |
||
522 | { |
||
523 | /* Pointer to initial [compiled in] values. */ |
||
524 | CGEN_KEYWORD_ENTRY *init_entries; |
||
525 | |||
526 | /* Number of entries in `init_entries'. */ |
||
527 | unsigned int num_init_entries; |
||
528 | |||
529 | /* Hash table used for name lookup. */ |
||
530 | CGEN_KEYWORD_ENTRY **name_hash_table; |
||
531 | |||
532 | /* Hash table used for value lookup. */ |
||
533 | CGEN_KEYWORD_ENTRY **value_hash_table; |
||
534 | |||
535 | /* Number of entries in the hash_tables. */ |
||
536 | unsigned int hash_table_size; |
||
537 | |||
538 | /* Pointer to null keyword "" entry if present. */ |
||
539 | const CGEN_KEYWORD_ENTRY *null_entry; |
||
540 | |||
541 | /* String containing non-alphanumeric characters used |
||
542 | in keywords. |
||
543 | At present, the highest number of entries used is 1. */ |
||
544 | char nonalpha_chars[8]; |
||
545 | } CGEN_KEYWORD; |
||
546 | |||
547 | /* Structure used for searching. */ |
||
548 | |||
549 | typedef struct |
||
550 | { |
||
551 | /* Table being searched. */ |
||
552 | const CGEN_KEYWORD *table; |
||
553 | |||
554 | /* Specification of what is being searched for. */ |
||
555 | const char *spec; |
||
556 | |||
557 | /* Current index in hash table. */ |
||
558 | unsigned int current_hash; |
||
559 | |||
560 | /* Current element in current hash chain. */ |
||
561 | CGEN_KEYWORD_ENTRY *current_entry; |
||
562 | } CGEN_KEYWORD_SEARCH; |
||
563 | |||
564 | /* Lookup a keyword from its name. */ |
||
565 | |||
566 | const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name |
||
567 | (CGEN_KEYWORD *, const char *); |
||
568 | |||
569 | /* Lookup a keyword from its value. */ |
||
570 | |||
571 | const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value |
||
572 | (CGEN_KEYWORD *, int); |
||
573 | |||
574 | /* Add a keyword. */ |
||
575 | |||
576 | void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); |
||
577 | |||
578 | /* Keyword searching. |
||
579 | This can be used to retrieve every keyword, or a subset. */ |
||
580 | |||
581 | CGEN_KEYWORD_SEARCH cgen_keyword_search_init |
||
582 | (CGEN_KEYWORD *, const char *); |
||
583 | const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next |
||
584 | (CGEN_KEYWORD_SEARCH *); |
||
585 | |||
586 | /* Operand value support routines. */ |
||
587 | |||
588 | extern const char *cgen_parse_keyword |
||
589 | (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); |
||
590 | #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ |
||
591 | extern const char *cgen_parse_signed_integer |
||
592 | (CGEN_CPU_DESC, const char **, int, long *); |
||
593 | extern const char *cgen_parse_unsigned_integer |
||
594 | (CGEN_CPU_DESC, const char **, int, unsigned long *); |
||
595 | extern const char *cgen_parse_address |
||
596 | (CGEN_CPU_DESC, const char **, int, int, |
||
597 | enum cgen_parse_operand_result *, bfd_vma *); |
||
598 | extern const char *cgen_validate_signed_integer |
||
599 | (long, long, long); |
||
600 | extern const char *cgen_validate_unsigned_integer |
||
601 | (unsigned long, unsigned long, unsigned long); |
||
602 | #endif |
||
603 | |||
604 | /* Operand modes. */ |
||
605 | |||
606 | /* ??? This duplicates the values in arch.h. Revisit. |
||
607 | These however need the CGEN_ prefix [as does everything in this file]. */ |
||
608 | /* ??? Targets may need to add their own modes so we may wish to move this |
||
609 | to |
||
610 | |||
611 | enum cgen_mode { |
||
612 | CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ |
||
613 | CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, |
||
614 | CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, |
||
615 | CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, |
||
616 | CGEN_MODE_TARGET_MAX, |
||
617 | CGEN_MODE_INT, CGEN_MODE_UINT, |
||
618 | CGEN_MODE_MAX |
||
619 | }; |
||
620 | |||
621 | /* FIXME: Until simulator is updated. */ |
||
622 | |||
623 | #define CGEN_MODE_VM CGEN_MODE_VOID |
||
624 | |||
625 | /* Operands. */ |
||
626 | |||
627 | #ifndef CGEN_ARCH |
||
628 | enum cgen_operand_type { CGEN_OPERAND_MAX }; |
||
629 | #endif |
||
630 | |||
631 | /* "nil" indicator for the operand instance table */ |
||
632 | #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX |
||
633 | |||
634 | /* A tree of these structs represents the multi-ifield |
||
635 | structure of an operand's hw-index value, if it exists. */ |
||
636 | |||
637 | struct cgen_ifld; |
||
638 | |||
639 | typedef struct cgen_maybe_multi_ifield |
||
640 | { |
||
641 | int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); |
||
642 | n: indexed by array of more cgen_maybe_multi_ifields. */ |
||
643 | union |
||
644 | { |
||
645 | const void *p; |
||
646 | const struct cgen_maybe_multi_ifield * multi; |
||
647 | const struct cgen_ifld * leaf; |
||
648 | } val; |
||
649 | } |
||
650 | CGEN_MAYBE_MULTI_IFLD; |
||
651 | |||
652 | /* This struct defines each entry in the operand table. */ |
||
653 | |||
654 | typedef struct |
||
655 | { |
||
656 | /* Name as it appears in the syntax string. */ |
||
657 | char *name; |
||
658 | |||
659 | /* Operand type. */ |
||
660 | enum cgen_operand_type type; |
||
661 | |||
662 | /* The hardware element associated with this operand. */ |
||
663 | enum cgen_hw_type hw_type; |
||
664 | |||
665 | /* FIXME: We don't yet record ifield definitions, which we should. |
||
666 | When we do it might make sense to delete start/length (since they will |
||
667 | be duplicated in the ifield's definition) and replace them with a |
||
668 | pointer to the ifield entry. */ |
||
669 | |||
670 | /* Bit position. |
||
671 | This is just a hint, and may be unused in more complex operands. |
||
672 | May be unused for a modifier. */ |
||
673 | unsigned char start; |
||
674 | |||
675 | /* The number of bits in the operand. |
||
676 | This is just a hint, and may be unused in more complex operands. |
||
677 | May be unused for a modifier. */ |
||
678 | unsigned char length; |
||
679 | |||
680 | /* The (possibly-multi) ifield used as an index for this operand, if it |
||
681 | is indexed by a field at all. This substitutes / extends the start and |
||
682 | length fields above, but unsure at this time whether they are used |
||
683 | anywhere. */ |
||
684 | CGEN_MAYBE_MULTI_IFLD index_fields; |
||
685 | #if 0 /* ??? Interesting idea but relocs tend to get too complicated, |
||
686 | and ABI dependent, for simple table lookups to work. */ |
||
687 | /* Ideally this would be the internal (external?) reloc type. */ |
||
688 | int reloc_type; |
||
689 | #endif |
||
690 | |||
691 | /* Attributes. |
||
692 | This should, but technically needn't, appear last. It is a variable sized |
||
693 | array in that one architecture may have 1 nonbool attribute and another |
||
694 | may have more. Having this last means the non-architecture specific code |
||
695 | needn't care, now or tomorrow. The goal is to eventually record |
||
696 | attributes in their raw form, evaluate them at run-time, and cache the |
||
697 | values, so this worry will go away anyway. */ |
||
698 | #ifndef CGEN_OPERAND_NBOOL_ATTRS |
||
699 | #define CGEN_OPERAND_NBOOL_ATTRS 1 |
||
700 | #endif |
||
701 | CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; |
||
702 | #define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) |
||
703 | } CGEN_OPERAND; |
||
704 | |||
705 | /* Return value of attribute ATTR in OPERAND. */ |
||
706 | |||
707 | #define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ |
||
708 | CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) |
||
709 | |||
710 | /* Table of operands for selected mach/isa, computed at runtime. |
||
711 | enum cgen_operand_type is an index into this table (specifically |
||
712 | `entries'). */ |
||
713 | |||
714 | typedef struct { |
||
715 | /* Pointer to null terminated table of all compiled in entries. */ |
||
716 | const CGEN_OPERAND *init_entries; |
||
717 | unsigned int entry_size; /* since the attribute member is variable sized */ |
||
718 | /* Array of all entries, initial and run-time added. */ |
||
719 | const CGEN_OPERAND **entries; |
||
720 | /* Number of elements in `entries'. */ |
||
721 | unsigned int num_entries; |
||
722 | /* For now, xrealloc is called each time a new entry is added at runtime. |
||
723 | ??? May wish to keep track of some slop to reduce the number of calls to |
||
724 | xrealloc, except that there's unlikely to be many and not expected to be |
||
725 | in speed critical code. */ |
||
726 | } CGEN_OPERAND_TABLE; |
||
727 | |||
728 | extern const CGEN_OPERAND * cgen_operand_lookup_by_name |
||
729 | (CGEN_CPU_DESC, const char *); |
||
730 | extern const CGEN_OPERAND * cgen_operand_lookup_by_num |
||
731 | (CGEN_CPU_DESC, int); |
||
732 | |||
733 | /* Instruction operand instances. |
||
734 | |||
735 | For each instruction, a list of the hardware elements that are read and |
||
736 | written are recorded. */ |
||
737 | |||
738 | /* The type of the instance. */ |
||
739 | |||
740 | enum cgen_opinst_type { |
||
741 | /* End of table marker. */ |
||
742 | CGEN_OPINST_END = 0, |
||
743 | CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT |
||
744 | }; |
||
745 | |||
746 | typedef struct |
||
747 | { |
||
748 | /* Input or output indicator. */ |
||
749 | enum cgen_opinst_type type; |
||
750 | |||
751 | /* Name of operand. */ |
||
752 | const char *name; |
||
753 | |||
754 | /* The hardware element referenced. */ |
||
755 | enum cgen_hw_type hw_type; |
||
756 | |||
757 | /* The mode in which the operand is being used. */ |
||
758 | enum cgen_mode mode; |
||
759 | |||
760 | /* The operand table entry CGEN_OPERAND_NIL if there is none |
||
761 | (i.e. an explicit hardware reference). */ |
||
762 | enum cgen_operand_type op_type; |
||
763 | |||
764 | /* If `operand' is "nil", the index (e.g. into array of registers). */ |
||
765 | int index; |
||
766 | |||
767 | /* Attributes. |
||
768 | ??? This perhaps should be a real attribute struct but there's |
||
769 | no current need, so we save a bit of space and just have a set of |
||
770 | flags. The interface is such that this can easily be made attributes |
||
771 | should it prove useful. */ |
||
772 | unsigned int attrs; |
||
773 | #define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) |
||
774 | /* Return value of attribute ATTR in OPINST. */ |
||
775 | #define CGEN_OPINST_ATTR(opinst, attr) \ |
||
776 | ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) |
||
777 | /* Operand is conditionally referenced (read/written). */ |
||
778 | #define CGEN_OPINST_COND_REF 1 |
||
779 | } CGEN_OPINST; |
||
780 | |||
781 | /* Syntax string. |
||
782 | |||
783 | Each insn format and subexpression has one of these. |
||
784 | |||
785 | The syntax "string" consists of characters (n > 0 && n < 128), and operand |
||
786 | values (n >= 128), and is terminated by 0. Operand values are 128 + index |
||
787 | into the operand table. The operand table doesn't exist in C, per se, as |
||
788 | the data is recorded in the parse/insert/extract/print switch statements. */ |
||
789 | |||
790 | /* This should be at least as large as necessary for any target. */ |
||
791 | #define CGEN_MAX_SYNTAX_ELEMENTS 48 |
||
792 | |||
793 | /* A target may know its own precise maximum. Assert that it falls below |
||
794 | the above limit. */ |
||
795 | #ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS |
||
796 | #if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS |
||
797 | #error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" |
||
798 | #endif |
||
799 | #endif |
||
800 | |||
801 | typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; |
||
802 | |||
803 | typedef struct |
||
804 | { |
||
805 | CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; |
||
806 | } CGEN_SYNTAX; |
||
807 | |||
808 | #define CGEN_SYNTAX_STRING(syn) (syn->syntax) |
||
809 | #define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) |
||
810 | #define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) |
||
811 | #define CGEN_SYNTAX_FIELD(c) ((c) - 128) |
||
812 | #define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) |
||
813 | |||
814 | /* ??? I can't currently think of any case where the mnemonic doesn't come |
||
815 | first [and if one ever doesn't building the hash tables will be tricky]. |
||
816 | However, we treat mnemonics as just another operand of the instruction. |
||
817 | A value of 1 means "this is where the mnemonic appears". 1 isn't |
||
818 | special other than it's a non-printable ASCII char. */ |
||
819 | |||
820 | #define CGEN_SYNTAX_MNEMONIC 1 |
||
821 | #define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) |
||
822 | |||
823 | /* Instruction fields. |
||
824 | |||
825 | ??? We currently don't allow adding fields at run-time. |
||
826 | Easy to fix when needed. */ |
||
827 | |||
828 | typedef struct cgen_ifld { |
||
829 | /* Enum of ifield. */ |
||
830 | int num; |
||
831 | #define CGEN_IFLD_NUM(f) ((f)->num) |
||
832 | |||
833 | /* Name of the field, distinguishes it from all other fields. */ |
||
834 | const char *name; |
||
835 | #define CGEN_IFLD_NAME(f) ((f)->name) |
||
836 | |||
837 | /* Default offset, in bits, from the start of the insn to the word |
||
838 | containing the field. */ |
||
839 | int word_offset; |
||
840 | #define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) |
||
841 | |||
842 | /* Default length of the word containing the field. */ |
||
843 | int word_size; |
||
844 | #define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) |
||
845 | |||
846 | /* Default starting bit number. |
||
847 | Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ |
||
848 | int start; |
||
849 | #define CGEN_IFLD_START(f) ((f)->start) |
||
850 | |||
851 | /* Length of the field, in bits. */ |
||
852 | int length; |
||
853 | #define CGEN_IFLD_LENGTH(f) ((f)->length) |
||
854 | |||
855 | #ifndef CGEN_IFLD_NBOOL_ATTRS |
||
856 | #define CGEN_IFLD_NBOOL_ATTRS 1 |
||
857 | #endif |
||
858 | CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; |
||
859 | #define CGEN_IFLD_ATTRS(f) (&(f)->attrs) |
||
860 | } CGEN_IFLD; |
||
861 | |||
862 | /* Return value of attribute ATTR in IFLD. */ |
||
863 | #define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ |
||
864 | CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) |
||
865 | |||
866 | /* Instruction data. */ |
||
867 | |||
868 | /* Instruction formats. |
||
869 | |||
870 | Instructions are grouped by format. Associated with an instruction is its |
||
871 | format. Each insn's opcode table entry contains a format table entry. |
||
872 | ??? There is usually very few formats compared with the number of insns, |
||
873 | so one can reduce the size of the opcode table by recording the format table |
||
874 | as a separate entity. Given that we currently don't, format table entries |
||
875 | are also distinguished by their operands. This increases the size of the |
||
876 | table, but reduces the number of tables. It's all minutiae anyway so it |
||
877 | doesn't really matter [at this point in time]. |
||
878 | |||
879 | ??? Support for variable length ISA's is wip. */ |
||
880 | |||
881 | /* Accompanying each iformat description is a list of its fields. */ |
||
882 | |||
883 | typedef struct { |
||
884 | const CGEN_IFLD *ifld; |
||
885 | #define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) |
||
886 | } CGEN_IFMT_IFLD; |
||
887 | |||
888 | /* This should be at least as large as necessary for any target. */ |
||
889 | #define CGEN_MAX_IFMT_OPERANDS 16 |
||
890 | |||
891 | /* A target may know its own precise maximum. Assert that it falls below |
||
892 | the above limit. */ |
||
893 | #ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS |
||
894 | #if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS |
||
895 | #error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" |
||
896 | #endif |
||
897 | #endif |
||
898 | |||
899 | |||
900 | typedef struct |
||
901 | { |
||
902 | /* Length that MASK and VALUE have been calculated to |
||
903 | [VALUE is recorded elsewhere]. |
||
904 | Normally it is base_insn_bitsize. On [V]LIW architectures where the base |
||
905 | insn size may be larger than the size of an insn, this field is less than |
||
906 | base_insn_bitsize. */ |
||
907 | unsigned char mask_length; |
||
908 | #define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) |
||
909 | |||
910 | /* Total length of instruction, in bits. */ |
||
911 | unsigned char length; |
||
912 | #define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) |
||
913 | |||
914 | /* Mask to apply to the first MASK_LENGTH bits. |
||
915 | Each insn's value is stored with the insn. |
||
916 | The first step in recognizing an insn for disassembly is |
||
917 | (opcode & mask) == value. */ |
||
918 | CGEN_INSN_INT mask; |
||
919 | #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) |
||
920 | |||
921 | /* Instruction fields. |
||
922 | +1 for trailing NULL. */ |
||
923 | CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; |
||
924 | #define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) |
||
925 | } CGEN_IFMT; |
||
926 | |||
927 | /* Instruction values. */ |
||
928 | |||
929 | typedef struct |
||
930 | { |
||
931 | /* The opcode portion of the base insn. */ |
||
932 | CGEN_INSN_INT base_value; |
||
933 | |||
934 | #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS |
||
935 | /* Extra opcode values beyond base_value. */ |
||
936 | unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; |
||
937 | #endif |
||
938 | } CGEN_IVALUE; |
||
939 | |||
940 | /* Instruction opcode table. |
||
941 | This contains the syntax and format data of an instruction. */ |
||
942 | |||
943 | /* ??? Some ports already have an opcode table yet still need to use the rest |
||
944 | of what cgen_insn has. Plus keeping the opcode data with the operand |
||
945 | instance data can create a pretty big file. So we keep them separately. |
||
946 | Not sure this is a good idea in the long run. */ |
||
947 | |||
948 | typedef struct |
||
949 | { |
||
950 | /* Indices into parse/insert/extract/print handler tables. */ |
||
951 | struct cgen_opcode_handler handlers; |
||
952 | #define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) |
||
953 | |||
954 | /* Syntax string. */ |
||
955 | CGEN_SYNTAX syntax; |
||
956 | #define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) |
||
957 | |||
958 | /* Format entry. */ |
||
959 | const CGEN_IFMT *format; |
||
960 | #define CGEN_OPCODE_FORMAT(opc) ((opc)->format) |
||
961 | #define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) |
||
962 | #define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) |
||
963 | #define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) |
||
964 | |||
965 | /* Instruction opcode value. */ |
||
966 | CGEN_IVALUE value; |
||
967 | #define CGEN_OPCODE_VALUE(opc) (& (opc)->value) |
||
968 | #define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) |
||
969 | #define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) |
||
970 | } CGEN_OPCODE; |
||
971 | |||
972 | /* Instruction attributes. |
||
973 | This is made a published type as applications can cache a pointer to |
||
974 | the attributes for speed. */ |
||
975 | |||
976 | #ifndef CGEN_INSN_NBOOL_ATTRS |
||
977 | #define CGEN_INSN_NBOOL_ATTRS 1 |
||
978 | #endif |
||
979 | typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; |
||
980 | |||
981 | /* Enum of architecture independent attributes. */ |
||
982 | |||
983 | #ifndef CGEN_ARCH |
||
984 | /* ??? Numbers here are recorded in two places. */ |
||
985 | typedef enum cgen_insn_attr { |
||
986 | CGEN_INSN_ALIAS = 0 |
||
987 | } CGEN_INSN_ATTR; |
||
988 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) |
||
989 | #endif |
||
990 | |||
991 | /* This struct defines each entry in the instruction table. */ |
||
992 | |||
993 | typedef struct |
||
994 | { |
||
995 | /* Each real instruction is enumerated. */ |
||
996 | /* ??? This may go away in time. */ |
||
997 | int num; |
||
998 | #define CGEN_INSN_NUM(insn) ((insn)->base->num) |
||
999 | |||
1000 | /* Name of entry (that distinguishes it from all other entries). */ |
||
1001 | /* ??? If mnemonics have operands, try to print full mnemonic. */ |
||
1002 | const char *name; |
||
1003 | #define CGEN_INSN_NAME(insn) ((insn)->base->name) |
||
1004 | |||
1005 | /* Mnemonic. This is used when parsing and printing the insn. |
||
1006 | In the case of insns that have operands on the mnemonics, this is |
||
1007 | only the constant part. E.g. for conditional execution of an `add' insn, |
||
1008 | where the full mnemonic is addeq, addne, etc., and the condition is |
||
1009 | treated as an operand, this is only "add". */ |
||
1010 | const char *mnemonic; |
||
1011 | #define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) |
||
1012 | |||
1013 | /* Total length of instruction, in bits. */ |
||
1014 | int bitsize; |
||
1015 | #define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) |
||
1016 | |||
1017 | #if 0 /* ??? Disabled for now as there is a problem with embedded newlines |
||
1018 | and the table is already pretty big. Should perhaps be moved |
||
1019 | to a file of its own. */ |
||
1020 | /* Semantics, as RTL. */ |
||
1021 | /* ??? Plain text or bytecodes? */ |
||
1022 | /* ??? Note that the operand instance table could be computed at run-time |
||
1023 | if we parse this and cache the results. Something to eventually do. */ |
||
1024 | const char *rtx; |
||
1025 | #define CGEN_INSN_RTX(insn) ((insn)->base->rtx) |
||
1026 | #endif |
||
1027 | |||
1028 | /* Attributes. |
||
1029 | This must appear last. It is a variable sized array in that one |
||
1030 | architecture may have 1 nonbool attribute and another may have more. |
||
1031 | Having this last means the non-architecture specific code needn't |
||
1032 | care. The goal is to eventually record attributes in their raw form, |
||
1033 | evaluate them at run-time, and cache the values, so this worry will go |
||
1034 | away anyway. */ |
||
1035 | CGEN_INSN_ATTR_TYPE attrs; |
||
1036 | #define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) |
||
1037 | /* Return value of attribute ATTR in INSN. */ |
||
1038 | #define CGEN_INSN_ATTR_VALUE(insn, attr) \ |
||
1039 | CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) |
||
1040 | #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ |
||
1041 | CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) |
||
1042 | } CGEN_IBASE; |
||
1043 | |||
1044 | /* Return non-zero if INSN is the "invalid" insn marker. */ |
||
1045 | |||
1046 | #define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) |
||
1047 | |||
1048 | /* Main struct contain instruction information. |
||
1049 | BASE is always present, the rest is present only if asked for. */ |
||
1050 | |||
1051 | struct cgen_insn |
||
1052 | { |
||
1053 | /* ??? May be of use to put a type indicator here. |
||
1054 | Then this struct could different info for different classes of insns. */ |
||
1055 | /* ??? A speedup can be had by moving `base' into this struct. |
||
1056 | Maybe later. */ |
||
1057 | const CGEN_IBASE *base; |
||
1058 | const CGEN_OPCODE *opcode; |
||
1059 | const CGEN_OPINST *opinst; |
||
1060 | |||
1061 | /* Regex to disambiguate overloaded opcodes */ |
||
1062 | void *rx; |
||
1063 | #define CGEN_INSN_RX(insn) ((insn)->rx) |
||
1064 | #define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) |
||
1065 | }; |
||
1066 | |||
1067 | /* Instruction lists. |
||
1068 | This is used for adding new entries and for creating the hash lists. */ |
||
1069 | |||
1070 | typedef struct cgen_insn_list |
||
1071 | { |
||
1072 | struct cgen_insn_list *next; |
||
1073 | const CGEN_INSN *insn; |
||
1074 | } CGEN_INSN_LIST; |
||
1075 | |||
1076 | /* Table of instructions. */ |
||
1077 | |||
1078 | typedef struct |
||
1079 | { |
||
1080 | const CGEN_INSN *init_entries; |
||
1081 | unsigned int entry_size; /* since the attribute member is variable sized */ |
||
1082 | unsigned int num_init_entries; |
||
1083 | CGEN_INSN_LIST *new_entries; |
||
1084 | } CGEN_INSN_TABLE; |
||
1085 | |||
1086 | /* Return number of instructions. This includes any added at run-time. */ |
||
1087 | |||
1088 | extern int cgen_insn_count (CGEN_CPU_DESC); |
||
1089 | extern int cgen_macro_insn_count (CGEN_CPU_DESC); |
||
1090 | |||
1091 | /* Macros to access the other insn elements not recorded in CGEN_IBASE. */ |
||
1092 | |||
1093 | /* Fetch INSN's operand instance table. */ |
||
1094 | /* ??? Doesn't handle insns added at runtime. */ |
||
1095 | #define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) |
||
1096 | |||
1097 | /* Return INSN's opcode table entry. */ |
||
1098 | #define CGEN_INSN_OPCODE(insn) ((insn)->opcode) |
||
1099 | |||
1100 | /* Return INSN's handler data. */ |
||
1101 | #define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) |
||
1102 | |||
1103 | /* Return INSN's syntax. */ |
||
1104 | #define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) |
||
1105 | |||
1106 | /* Return size of base mask in bits. */ |
||
1107 | #define CGEN_INSN_MASK_BITSIZE(insn) \ |
||
1108 | CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) |
||
1109 | |||
1110 | /* Return mask of base part of INSN. */ |
||
1111 | #define CGEN_INSN_BASE_MASK(insn) \ |
||
1112 | CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) |
||
1113 | |||
1114 | /* Return value of base part of INSN. */ |
||
1115 | #define CGEN_INSN_BASE_VALUE(insn) \ |
||
1116 | CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) |
||
1117 | |||
1118 | /* Standard way to test whether INSN is supported by MACH. |
||
1119 | MACH is one of enum mach_attr. |
||
1120 | The "|1" is because the base mach is always selected. */ |
||
1121 | #define CGEN_INSN_MACH_HAS_P(insn, mach) \ |
||
1122 | ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) |
||
1123 | |||
1124 | /* Macro instructions. |
||
1125 | Macro insns aren't real insns, they map to one or more real insns. |
||
1126 | E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or |
||
1127 | some such. |
||
1128 | |||
1129 | Macro insns can expand to nothing (e.g. a nop that is optimized away). |
||
1130 | This is useful in multi-insn macros that build a constant in a register. |
||
1131 | Of course this isn't the default behaviour and must be explicitly enabled. |
||
1132 | |||
1133 | Assembly of macro-insns is relatively straightforward. Disassembly isn't. |
||
1134 | However, disassembly of at least some kinds of macro insns is important |
||
1135 | in order that the disassembled code preserve the readability of the original |
||
1136 | insn. What is attempted here is to disassemble all "simple" macro-insns, |
||
1137 | where "simple" is currently defined to mean "expands to one real insn". |
||
1138 | |||
1139 | Simple macro-insns are handled specially. They are emitted as ALIAS's |
||
1140 | of real insns. This simplifies their handling since there's usually more |
||
1141 | of them than any other kind of macro-insn, and proper disassembly of them |
||
1142 | falls out for free. */ |
||
1143 | |||
1144 | /* For each macro-insn there may be multiple expansion possibilities, |
||
1145 | depending on the arguments. This structure is accessed via the `data' |
||
1146 | member of CGEN_INSN. */ |
||
1147 | |||
1148 | typedef struct cgen_minsn_expansion { |
||
1149 | /* Function to do the expansion. |
||
1150 | If the expansion fails (e.g. "no match") NULL is returned. |
||
1151 | Space for the expansion is obtained with malloc. |
||
1152 | It is up to the caller to free it. */ |
||
1153 | const char * (* fn) |
||
1154 | (const struct cgen_minsn_expansion *, |
||
1155 | const char *, const char **, int *, |
||
1156 | CGEN_OPERAND **); |
||
1157 | #define CGEN_MIEXPN_FN(ex) ((ex)->fn) |
||
1158 | |||
1159 | /* Instruction(s) the macro expands to. |
||
1160 | The format of STR is defined by FN. |
||
1161 | It is typically the assembly code of the real insn, but it could also be |
||
1162 | the original Scheme expression or a tokenized form of it (with FN being |
||
1163 | an appropriate interpreter). */ |
||
1164 | const char * str; |
||
1165 | #define CGEN_MIEXPN_STR(ex) ((ex)->str) |
||
1166 | } CGEN_MINSN_EXPANSION; |
||
1167 | |||
1168 | /* Normal expander. |
||
1169 | When supported, this function will convert the input string to another |
||
1170 | string and the parser will be invoked recursively. The output string |
||
1171 | may contain further macro invocations. */ |
||
1172 | |||
1173 | extern const char * cgen_expand_macro_insn |
||
1174 | (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, |
||
1175 | const char *, const char **, int *, CGEN_OPERAND **); |
||
1176 | |||
1177 | /* The assembler insn table is hashed based on some function of the mnemonic |
||
1178 | (the actually hashing done is up to the target, but we provide a few |
||
1179 | examples like the first letter or a function of the entire mnemonic). */ |
||
1180 | |||
1181 | extern CGEN_INSN_LIST * cgen_asm_lookup_insn |
||
1182 | (CGEN_CPU_DESC, const char *); |
||
1183 | #define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) |
||
1184 | #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) |
||
1185 | |||
1186 | /* The disassembler insn table is hashed based on some function of machine |
||
1187 | instruction (the actually hashing done is up to the target). */ |
||
1188 | |||
1189 | extern CGEN_INSN_LIST * cgen_dis_lookup_insn |
||
1190 | (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); |
||
1191 | /* FIXME: delete these two */ |
||
1192 | #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) |
||
1193 | #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) |
||
1194 | |||
1195 | /* The CPU description. |
||
1196 | A copy of this is created when the cpu table is "opened". |
||
1197 | All global state information is recorded here. |
||
1198 | Access macros are provided for "public" members. */ |
||
1199 | |||
1200 | typedef struct cgen_cpu_desc |
||
1201 | { |
||
1202 | /* Bitmap of selected machine(s) (a la BFD machine number). */ |
||
1203 | int machs; |
||
1204 | |||
1205 | /* Bitmap of selected isa(s). */ |
||
1206 | CGEN_BITSET *isas; |
||
1207 | #define CGEN_CPU_ISAS(cd) ((cd)->isas) |
||
1208 | |||
1209 | /* Current endian. */ |
||
1210 | enum cgen_endian endian; |
||
1211 | #define CGEN_CPU_ENDIAN(cd) ((cd)->endian) |
||
1212 | |||
1213 | /* Current insn endian. */ |
||
1214 | enum cgen_endian insn_endian; |
||
1215 | #define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) |
||
1216 | |||
1217 | /* Word size (in bits). */ |
||
1218 | /* ??? Or maybe maximum word size - might we ever need to allow a cpu table |
||
1219 | to be opened for both sparc32/sparc64? |
||
1220 | ??? Another alternative is to create a table of selected machs and |
||
1221 | lazily fetch the data from there. */ |
||
1222 | unsigned int word_bitsize; |
||
1223 | |||
1224 | /* Instruction chunk size (in bits), for purposes of endianness |
||
1225 | conversion. */ |
||
1226 | unsigned int insn_chunk_bitsize; |
||
1227 | |||
1228 | /* Indicator if sizes are unknown. |
||
1229 | This is used by default_insn_bitsize,base_insn_bitsize if there is a |
||
1230 | difference between the selected isa's. */ |
||
1231 | #define CGEN_SIZE_UNKNOWN 65535 |
||
1232 | |||
1233 | /* Default instruction size (in bits). |
||
1234 | This is used by the assembler when it encounters an unknown insn. */ |
||
1235 | unsigned int default_insn_bitsize; |
||
1236 | |||
1237 | /* Base instruction size (in bits). |
||
1238 | For non-LIW cpus this is generally the length of the smallest insn. |
||
1239 | For LIW cpus its wip (work-in-progress). For the m32r its 32. */ |
||
1240 | unsigned int base_insn_bitsize; |
||
1241 | |||
1242 | /* Minimum/maximum instruction size (in bits). */ |
||
1243 | unsigned int min_insn_bitsize; |
||
1244 | unsigned int max_insn_bitsize; |
||
1245 | |||
1246 | /* Instruction set variants. */ |
||
1247 | const CGEN_ISA *isa_table; |
||
1248 | |||
1249 | /* Machine variants. */ |
||
1250 | const CGEN_MACH *mach_table; |
||
1251 | |||
1252 | /* Hardware elements. */ |
||
1253 | CGEN_HW_TABLE hw_table; |
||
1254 | |||
1255 | /* Instruction fields. */ |
||
1256 | const CGEN_IFLD *ifld_table; |
||
1257 | |||
1258 | /* Operands. */ |
||
1259 | CGEN_OPERAND_TABLE operand_table; |
||
1260 | |||
1261 | /* Main instruction table. */ |
||
1262 | CGEN_INSN_TABLE insn_table; |
||
1263 | #define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) |
||
1264 | |||
1265 | /* Macro instructions are defined separately and are combined with real |
||
1266 | insns during hash table computation. */ |
||
1267 | CGEN_INSN_TABLE macro_insn_table; |
||
1268 | |||
1269 | /* Copy of CGEN_INT_INSN_P. */ |
||
1270 | int int_insn_p; |
||
1271 | |||
1272 | /* Called to rebuild the tables after something has changed. */ |
||
1273 | void (*rebuild_tables) (CGEN_CPU_DESC); |
||
1274 | |||
1275 | /* Operand parser callback. */ |
||
1276 | cgen_parse_operand_fn * parse_operand_fn; |
||
1277 | |||
1278 | /* Parse/insert/extract/print cover fns for operands. */ |
||
1279 | const char * (*parse_operand) |
||
1280 | (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); |
||
1281 | #ifdef __BFD_H_SEEN__ |
||
1282 | const char * (*insert_operand) |
||
1283 | (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, |
||
1284 | CGEN_INSN_BYTES_PTR, bfd_vma pc_); |
||
1285 | int (*extract_operand) |
||
1286 | (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, |
||
1287 | CGEN_FIELDS *fields_, bfd_vma pc_); |
||
1288 | void (*print_operand) |
||
1289 | (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, |
||
1290 | void const *attrs_, bfd_vma pc_, int length_); |
||
1291 | #else |
||
1292 | const char * (*insert_operand) (); |
||
1293 | int (*extract_operand) (); |
||
1294 | void (*print_operand) (); |
||
1295 | #endif |
||
1296 | #define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) |
||
1297 | #define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) |
||
1298 | #define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) |
||
1299 | #define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) |
||
1300 | |||
1301 | /* Size of CGEN_FIELDS struct. */ |
||
1302 | unsigned int sizeof_fields; |
||
1303 | #define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) |
||
1304 | |||
1305 | /* Set the bitsize field. */ |
||
1306 | void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); |
||
1307 | #define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) |
||
1308 | |||
1309 | /* CGEN_FIELDS accessors. */ |
||
1310 | int (*get_int_operand) |
||
1311 | (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); |
||
1312 | void (*set_int_operand) |
||
1313 | (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); |
||
1314 | #ifdef __BFD_H_SEEN__ |
||
1315 | bfd_vma (*get_vma_operand) |
||
1316 | (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); |
||
1317 | void (*set_vma_operand) |
||
1318 | (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); |
||
1319 | #else |
||
1320 | long (*get_vma_operand) (); |
||
1321 | void (*set_vma_operand) (); |
||
1322 | #endif |
||
1323 | #define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) |
||
1324 | #define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) |
||
1325 | #define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) |
||
1326 | #define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) |
||
1327 | |||
1328 | /* Instruction parse/insert/extract/print handlers. */ |
||
1329 | /* FIXME: make these types uppercase. */ |
||
1330 | cgen_parse_fn * const *parse_handlers; |
||
1331 | cgen_insert_fn * const *insert_handlers; |
||
1332 | cgen_extract_fn * const *extract_handlers; |
||
1333 | cgen_print_fn * const *print_handlers; |
||
1334 | #define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) |
||
1335 | #define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) |
||
1336 | #define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) |
||
1337 | #define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) |
||
1338 | |||
1339 | /* Return non-zero if insn should be added to hash table. */ |
||
1340 | int (* asm_hash_p) (const CGEN_INSN *); |
||
1341 | |||
1342 | /* Assembler hash function. */ |
||
1343 | unsigned int (* asm_hash) (const char *); |
||
1344 | |||
1345 | /* Number of entries in assembler hash table. */ |
||
1346 | unsigned int asm_hash_size; |
||
1347 | |||
1348 | /* Return non-zero if insn should be added to hash table. */ |
||
1349 | int (* dis_hash_p) (const CGEN_INSN *); |
||
1350 | |||
1351 | /* Disassembler hash function. */ |
||
1352 | unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); |
||
1353 | |||
1354 | /* Number of entries in disassembler hash table. */ |
||
1355 | unsigned int dis_hash_size; |
||
1356 | |||
1357 | /* Assembler instruction hash table. */ |
||
1358 | CGEN_INSN_LIST **asm_hash_table; |
||
1359 | CGEN_INSN_LIST *asm_hash_table_entries; |
||
1360 | |||
1361 | /* Disassembler instruction hash table. */ |
||
1362 | CGEN_INSN_LIST **dis_hash_table; |
||
1363 | CGEN_INSN_LIST *dis_hash_table_entries; |
||
1364 | |||
1365 | /* This field could be turned into a bitfield if room for other flags is needed. */ |
||
1366 | unsigned int signed_overflow_ok_p; |
||
1367 | |||
1368 | } CGEN_CPU_TABLE; |
||
1369 | |||
1370 | /* wip */ |
||
1371 | #ifndef CGEN_WORD_ENDIAN |
||
1372 | #define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) |
||
1373 | #endif |
||
1374 | #ifndef CGEN_INSN_WORD_ENDIAN |
||
1375 | #define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) |
||
1376 | #endif |
||
1377 | |||
1378 | /* Prototypes of major functions. */ |
||
1379 | /* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. |
||
1380 | Not the init fns though, as that would drag in things that mightn't be |
||
1381 | used and might not even exist. */ |
||
1382 | |||
1383 | /* Argument types to cpu_open. */ |
||
1384 | |||
1385 | enum cgen_cpu_open_arg { |
||
1386 | CGEN_CPU_OPEN_END, |
||
1387 | /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ |
||
1388 | CGEN_CPU_OPEN_ISAS, |
||
1389 | /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ |
||
1390 | CGEN_CPU_OPEN_MACHS, |
||
1391 | /* Select machine, arg is mach's bfd name. |
||
1392 | Multiple machines can be specified by repeated use. */ |
||
1393 | CGEN_CPU_OPEN_BFDMACH, |
||
1394 | /* Select endian, arg is CGEN_ENDIAN_*. */ |
||
1395 | CGEN_CPU_OPEN_ENDIAN |
||
1396 | }; |
||
1397 | |||
1398 | /* Open a cpu descriptor table for use. |
||
1399 | ??? We only support ISO C stdargs here, not K&R. |
||
1400 | Laziness, plus experiment to see if anything requires K&R - eventually |
||
1401 | K&R will no longer be supported - e.g. GDB is currently trying this. */ |
||
1402 | |||
1403 | extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); |
||
1404 | |||
1405 | /* Cover fn to handle simple case. */ |
||
1406 | |||
1407 | extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) |
||
1408 | (const char *mach_name_, enum cgen_endian endian_); |
||
1409 | |||
1410 | /* Close it. */ |
||
1411 | |||
1412 | extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); |
||
1413 | |||
1414 | /* Initialize the opcode table for use. |
||
1415 | Called by init_asm/init_dis. */ |
||
1416 | |||
1417 | extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); |
||
1418 | |||
1419 | /* build the insn selection regex. |
||
1420 | called by init_opcode_table */ |
||
1421 | |||
1422 | extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); |
||
1423 | |||
1424 | /* Initialize the ibld table for use. |
||
1425 | Called by init_asm/init_dis. */ |
||
1426 | |||
1427 | extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); |
||
1428 | |||
1429 | /* Initialize an cpu table for assembler or disassembler use. |
||
1430 | These must be called immediately after cpu_open. */ |
||
1431 | |||
1432 | extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); |
||
1433 | extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); |
||
1434 | |||
1435 | /* Initialize the operand instance table for use. */ |
||
1436 | |||
1437 | extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); |
||
1438 | |||
1439 | /* Assemble an instruction. */ |
||
1440 | |||
1441 | extern const CGEN_INSN * CGEN_SYM (assemble_insn) |
||
1442 | (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, |
||
1443 | CGEN_INSN_BYTES_PTR, char **); |
||
1444 | |||
1445 | extern const CGEN_KEYWORD CGEN_SYM (operand_mach); |
||
1446 | extern int CGEN_SYM (get_mach) (const char *); |
||
1447 | |||
1448 | /* Operand index computation. */ |
||
1449 | extern const CGEN_INSN * cgen_lookup_insn |
||
1450 | (CGEN_CPU_DESC, const CGEN_INSN * insn_, |
||
1451 | CGEN_INSN_INT int_value_, unsigned char *bytes_value_, |
||
1452 | int length_, CGEN_FIELDS *fields_, int alias_p_); |
||
1453 | extern void cgen_get_insn_operands |
||
1454 | (CGEN_CPU_DESC, const CGEN_INSN * insn_, |
||
1455 | const CGEN_FIELDS *fields_, int *indices_); |
||
1456 | extern const CGEN_INSN * cgen_lookup_get_insn_operands |
||
1457 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
||
1458 | CGEN_INSN_INT int_value_, unsigned char *bytes_value_, |
||
1459 | int length_, int *indices_, CGEN_FIELDS *fields_); |
||
1460 | |||
1461 | /* Cover fns to bfd_get/set. */ |
||
1462 | |||
1463 | extern CGEN_INSN_INT cgen_get_insn_value |
||
1464 | (CGEN_CPU_DESC, unsigned char *, int); |
||
1465 | extern void cgen_put_insn_value |
||
1466 | (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); |
||
1467 | |||
1468 | /* Read in a cpu description file. |
||
1469 | ??? For future concerns, including adding instructions to the assembler/ |
||
1470 | disassembler at run-time. */ |
||
1471 | |||
1472 | extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); |
||
1473 | |||
1474 | /* Allow signed overflow of instruction fields. */ |
||
1475 | extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); |
||
1476 | |||
1477 | /* Generate an error message if a signed field in an instruction overflows. */ |
||
1478 | extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); |
||
1479 | |||
1480 | /* Will an error message be generated if a signed field in an instruction overflows ? */ |
||
1481 | extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); |
||
1482 | |||
6324 | serge | 1483 | #ifdef __cplusplus |
1484 | } |
||
1485 | #endif |
||
1486 | |||
5191 | serge | 1487 | #endif /* OPCODE_CGEN_H */><>><>>>>><> |