Rev 5191 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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5191 | serge | 1 | /* Opcode table for the Atmel AVR micro controllers. |
2 | |||
6324 | serge | 3 | Copyright (C) 2000-2015 Free Software Foundation, Inc. |
5191 | serge | 4 | Contributed by Denis Chertykov |
5 | |||
6 | This program is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 3, or (at your option) |
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9 | any later version. |
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10 | |||
11 | This program is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |||
16 | You should have received a copy of the GNU General Public License |
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17 | along with this program; if not, write to the Free Software |
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18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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19 | MA 02110-1301, USA. */ |
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20 | |||
21 | #define AVR_ISA_1200 0x0001 /* In the beginning there was ... */ |
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22 | #define AVR_ISA_LPM 0x0002 /* device has LPM */ |
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23 | #define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ |
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24 | #define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ |
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6324 | serge | 25 | #define AVR_ISA_TINY 0x0010 /* device has Tiny core specific encodings */ |
5191 | serge | 26 | #define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL |
27 | supported, no 8K wrap on RJMP and RCALL) */ |
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28 | #define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ |
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29 | #define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ |
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30 | #define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ |
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31 | #define AVR_ISA_SPM 0x0200 /* device can program itself */ |
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32 | #define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ |
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33 | #define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ |
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34 | #define AVR_ISA_MOVW 0x1000 /* device has MOVW */ |
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35 | #define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */ |
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36 | #define AVR_ISA_DES 0x4000 /* device has DES */ |
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37 | #define AVR_ISA_RMW 0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */ |
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38 | |||
39 | #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) |
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40 | #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) |
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6324 | serge | 41 | #define AVR_ISA_2xxxa (AVR_ISA_1200 | AVR_ISA_SRAM) |
5191 | serge | 42 | /* For the attiny26 which is missing LPM Rd,Z+. */ |
43 | #define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX) |
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44 | #define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX) |
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45 | #define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \ |
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46 | AVR_ISA_SPM | AVR_ISA_BRK) |
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47 | #define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) |
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48 | #define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) |
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49 | #define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \ |
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50 | AVR_ISA_LPMX | AVR_ISA_SPM) |
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51 | #define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK) |
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52 | #define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \ |
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53 | AVR_ISA_LPMX | AVR_ISA_SPM) |
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54 | #define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX) |
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55 | #define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) |
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56 | #define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) |
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57 | #define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND) |
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58 | #define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES) |
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59 | #define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW) |
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60 | |||
61 | #define AVR_ISA_AVR1 AVR_ISA_TINY1 |
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62 | #define AVR_ISA_AVR2 AVR_ISA_2xxx |
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63 | #define AVR_ISA_AVR25 AVR_ISA_TINY2 |
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64 | #define AVR_ISA_AVR3 AVR_ISA_M603 |
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65 | #define AVR_ISA_AVR31 AVR_ISA_M103 |
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66 | #define AVR_ISA_AVR35 (AVR_ISA_AVR3 | AVR_ISA_MOVW | \ |
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67 | AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK) |
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68 | #define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35) |
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69 | #define AVR_ISA_AVR4 AVR_ISA_PWMx |
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70 | #define AVR_ISA_AVR5 AVR_ISA_M323 |
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71 | #define AVR_ISA_AVR51 AVR_ISA_M128 |
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72 | #define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \ |
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73 | AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \ |
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74 | AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \ |
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75 | AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW) |
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76 | |||
6324 | serge | 77 | #define AVR_ISA_AVRTINY (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM | \ |
78 | AVR_ISA_TINY) |
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79 | |||
5191 | serge | 80 | #define REGISTER_P(x) ((x) == 'r' \ |
81 | || (x) == 'd' \ |
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82 | || (x) == 'w' \ |
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83 | || (x) == 'a' \ |
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84 | || (x) == 'v') |
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85 | |||
86 | /* Undefined combination of operands - does the register |
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87 | operand overlap with pre-decremented or post-incremented |
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88 | pointer register (like ld r31,Z+)? */ |
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89 | #define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \ |
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90 | ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \ |
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91 | ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \ |
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92 | ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2) |
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93 | |||
94 | /* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */ |
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95 | #define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \ |
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96 | ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00) |
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97 | |||
98 | /* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as |
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99 | `ld r,b' or `st b,r' respectively - next opcode entry)? */ |
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100 | #define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) |
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101 | |||
6324 | serge | 102 | /* Constraint letters: |
5191 | serge | 103 | r - any register |
104 | d - `ldi' register (r16-r31) |
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105 | v - `movw' even register (r0, r2, ..., r28, r30) |
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106 | a - `fmul' register (r16-r23) |
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107 | w - `adiw' register (r24,r26,r28,r30) |
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108 | e - pointer registers (X,Y,Z) |
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109 | b - base pointer register and displacement ([YZ]+disp) |
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110 | z - Z pointer register (for [e]lpm Rd,Z[+]) |
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111 | M - immediate value from 0 to 255 |
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112 | n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible |
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113 | s - immediate value from 0 to 7 |
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114 | P - Port address value from 0 to 63. (in, out) |
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115 | p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) |
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116 | K - immediate value from 0 to 63 (used in `adiw', `sbiw') |
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117 | i - immediate value |
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6324 | serge | 118 | j - 7 bit immediate value from 0x40 to 0xBF (for 16-bit 'lds'/'sts') |
5191 | serge | 119 | l - signed pc relative offset from -64 to 63 |
120 | L - signed pc relative offset from -2048 to 2047 |
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121 | h - absolute code address (call, jmp) |
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122 | S - immediate value from 0 to 7 (S = s << 4) |
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123 | E - immediate value from 0 to 15, shifted left by 4 (des) |
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124 | ? - use this opcode entry if no parameters, else use next opcode entry |
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125 | |||
126 | Order is important - some binary opcodes have more than one name, |
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127 | the disassembler will only see the first match. |
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128 | |||
129 | Remaining undefined opcodes (1699 total - some of them might work |
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130 | as normal instructions if not all of the bits are decoded): |
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131 | |||
132 | 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) |
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133 | "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] |
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134 | "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 |
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135 | "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 |
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136 | "1001010x001x1001" (4) 0x9[45][23]9 |
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137 | "1001010x01xx1001" (8) 0x9[45][4-7]9 |
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138 | "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9 |
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139 | "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b |
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140 | "10010101001x1000" (2) 0x95[23]8 |
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141 | "1001010101xx1000" (4) 0x95[4-7]8 |
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142 | "1001010110111000" (1) 0x95b8 |
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143 | "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) |
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144 | "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] |
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145 | */ |
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146 | |||
147 | AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488) |
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148 | AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8) |
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149 | AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8) |
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150 | AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8) |
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151 | AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8) |
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152 | AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8) |
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153 | AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8) |
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154 | AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498) |
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155 | |||
156 | AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408) |
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157 | AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458) |
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158 | AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478) |
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159 | AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428) |
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160 | AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448) |
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161 | AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) |
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162 | AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) |
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163 | AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) |
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164 | |||
6324 | serge | 165 | /* Same as {cl,se}[chinstvz] above. */ |
5191 | serge | 166 | AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) |
167 | AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) |
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168 | |||
6324 | serge | 169 | AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxxa,0x9509) |
170 | AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxxa,0x9409) |
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5191 | serge | 171 | |
172 | AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) |
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173 | AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) |
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174 | AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8) |
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175 | AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006) |
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176 | |||
177 | AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) |
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178 | AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) |
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179 | AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) |
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180 | AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) |
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181 | AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) |
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182 | AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) |
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183 | AVR_INSN (spm, "?", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) |
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184 | AVR_INSN (spm, "z", "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8) |
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185 | |||
186 | AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) |
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187 | AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) |
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188 | AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) |
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189 | AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400) |
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190 | AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400) |
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191 | AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000) |
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192 | AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) |
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193 | AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00) |
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194 | AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00) |
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195 | AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) |
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196 | AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) |
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197 | AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) |
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198 | |||
6324 | serge | 199 | /* Shorthand for {eor,add,adc,and} r,r above. */ |
5191 | serge | 200 | AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) |
201 | AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) |
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202 | AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) |
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203 | AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) |
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204 | |||
205 | AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) |
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206 | /*XXX special case*/ |
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207 | AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) |
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208 | |||
209 | AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000) |
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210 | AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f) |
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211 | |||
212 | AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) |
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213 | AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) |
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214 | |||
215 | AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000) |
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216 | AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000) |
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217 | AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000) |
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218 | |||
219 | AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00) |
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220 | AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00) |
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221 | AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800) |
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222 | AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00) |
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223 | |||
224 | AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000) |
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225 | AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800) |
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226 | |||
227 | AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600) |
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228 | AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700) |
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229 | |||
230 | AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800) |
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231 | AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00) |
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232 | AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900) |
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233 | AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00) |
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234 | |||
235 | AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) |
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236 | AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) |
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237 | AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001) |
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238 | AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404) |
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239 | AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405) |
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240 | AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005) |
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241 | AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407) |
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242 | AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007) |
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243 | AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) |
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244 | AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004) |
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245 | AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002) |
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246 | AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401) |
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247 | AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402) |
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248 | AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) |
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249 | AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406) |
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250 | AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) |
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251 | AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) |
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252 | AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) |
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253 | |||
6324 | serge | 254 | /* Same as br?? above. */ |
5191 | serge | 255 | AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) |
256 | AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) |
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257 | |||
258 | AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000) |
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259 | AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000) |
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260 | |||
261 | AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e) |
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262 | AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c) |
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263 | |||
264 | AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405) |
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265 | AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400) |
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266 | AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) |
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267 | AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) |
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268 | AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) |
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269 | AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) |
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6324 | serge | 270 | AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxxa,0x900f) |
271 | AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxxa,0x920f) |
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5191 | serge | 272 | AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) |
273 | AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) |
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274 | |||
6324 | serge | 275 | /* Atomic memory operations for XMEGA. List before `sts'. */ |
5191 | serge | 276 | AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204) |
277 | AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205) |
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278 | AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206) |
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279 | AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207) |
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280 | |||
6324 | serge | 281 | /* Known to be decoded as `nop' by the old core. */ |
5191 | serge | 282 | AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) |
283 | AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) |
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284 | AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) |
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285 | AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) |
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286 | AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) |
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287 | AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) |
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288 | |||
6324 | serge | 289 | AVR_INSN (sts, "j,d", "10101kkkddddkkkk", 1, AVR_ISA_TINY, 0xA800) |
290 | AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) |
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291 | AVR_INSN (lds, "d,j", "10100kkkddddkkkk", 1, AVR_ISA_TINY, 0xA000) |
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292 | AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) |
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5191 | serge | 293 | |
6324 | serge | 294 | /* Special case for b+0, `e' must be next entry after `b', |
295 | b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ |
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5191 | serge | 296 | AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) |
297 | AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) |
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298 | AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) |
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299 | AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) |
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300 | |||
6324 | serge | 301 | /* These are for devices that don't exist yet |
302 | (>128K program memory, PC = EIND:Z). */ |
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5191 | serge | 303 | AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) |
304 | AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) |
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305 | |||
6324 | serge | 306 | /* DES instruction for encryption and decryption. */ |
5191 | serge | 307 | AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B)><> |
308 |