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5191 | serge | 1 | /* alpha.h -- Header file for Alpha opcode table |
6324 | serge | 2 | Copyright (C) 1996-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Contributed by Richard Henderson |
4 | patterned after the PPC opcode table written by Ian Lance Taylor. |
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5 | |||
6 | This file is part of GDB, GAS, and the GNU binutils. |
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7 | |||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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9 | them and/or modify them under the terms of the GNU General Public |
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10 | License as published by the Free Software Foundation; either version 3, |
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11 | or (at your option) any later version. |
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12 | |||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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16 | the GNU General Public License for more details. |
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17 | |||
18 | You should have received a copy of the GNU General Public License |
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19 | along with this file; see the file COPYING3. If not, write to the Free |
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20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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21 | MA 02110-1301, USA. */ |
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22 | |||
23 | #ifndef OPCODE_ALPHA_H |
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24 | #define OPCODE_ALPHA_H |
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25 | |||
26 | /* The opcode table is an array of struct alpha_opcode. */ |
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27 | |||
28 | struct alpha_opcode |
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29 | { |
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30 | /* The opcode name. */ |
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31 | const char *name; |
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32 | |||
33 | /* The opcode itself. Those bits which will be filled in with |
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34 | operands are zeroes. */ |
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35 | unsigned opcode; |
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36 | |||
37 | /* The opcode mask. This is used by the disassembler. This is a |
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38 | mask containing ones indicating those bits which must match the |
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39 | opcode field, and zeroes indicating those bits which need not |
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40 | match (and are presumably filled in by operands). */ |
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41 | unsigned mask; |
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42 | |||
43 | /* One bit flags for the opcode. These are primarily used to |
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44 | indicate specific processors and environments support the |
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45 | instructions. The defined values are listed below. */ |
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46 | unsigned flags; |
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47 | |||
48 | /* An array of operand codes. Each code is an index into the |
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49 | operand table. They appear in the order which the operands must |
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50 | appear in assembly code, and are terminated by a zero. */ |
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51 | unsigned char operands[4]; |
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52 | }; |
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53 | |||
54 | /* The table itself is sorted by major opcode number, and is otherwise |
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55 | in the order in which the disassembler should consider |
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56 | instructions. */ |
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57 | extern const struct alpha_opcode alpha_opcodes[]; |
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58 | extern const unsigned alpha_num_opcodes; |
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59 | |||
60 | /* Values defined for the flags field of a struct alpha_opcode. */ |
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61 | |||
62 | /* CPU Availability */ |
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63 | #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ |
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64 | #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ |
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65 | #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ |
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66 | #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ |
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67 | #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ |
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68 | #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ |
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69 | #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ |
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70 | |||
71 | #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) |
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72 | |||
73 | /* A macro to extract the major opcode from an instruction. */ |
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74 | #define AXP_OP(i) (((i) >> 26) & 0x3F) |
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75 | |||
76 | /* The total number of major opcodes. */ |
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77 | #define AXP_NOPS 0x40 |
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78 | |||
79 | |||
80 | /* The operands table is an array of struct alpha_operand. */ |
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81 | |||
82 | struct alpha_operand |
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83 | { |
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84 | /* The number of bits in the operand. */ |
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85 | unsigned int bits : 5; |
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86 | |||
87 | /* How far the operand is left shifted in the instruction. */ |
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88 | unsigned int shift : 5; |
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89 | |||
90 | /* The default relocation type for this operand. */ |
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91 | signed int default_reloc : 16; |
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92 | |||
93 | /* One bit syntax flags. */ |
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94 | unsigned int flags : 16; |
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95 | |||
96 | /* Insertion function. This is used by the assembler. To insert an |
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97 | operand value into an instruction, check this field. |
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98 | |||
99 | If it is NULL, execute |
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100 | i |= (op & ((1 << o->bits) - 1)) << o->shift; |
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101 | (i is the instruction which we are filling in, o is a pointer to |
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102 | this structure, and op is the opcode value; this assumes twos |
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103 | complement arithmetic). |
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104 | |||
105 | If this field is not NULL, then simply call it with the |
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106 | instruction and the operand value. It will return the new value |
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107 | of the instruction. If the ERRMSG argument is not NULL, then if |
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108 | the operand value is illegal, *ERRMSG will be set to a warning |
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109 | string (the operand will be inserted in any case). If the |
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110 | operand value is legal, *ERRMSG will be unchanged (most operands |
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111 | can accept any value). */ |
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112 | unsigned (*insert) (unsigned instruction, int op, const char **errmsg); |
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113 | |||
114 | /* Extraction function. This is used by the disassembler. To |
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115 | extract this operand type from an instruction, check this field. |
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116 | |||
117 | If it is NULL, compute |
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118 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
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119 | if ((o->flags & AXP_OPERAND_SIGNED) != 0 |
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120 | && (op & (1 << (o->bits - 1))) != 0) |
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121 | op -= 1 << o->bits; |
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122 | (i is the instruction, o is a pointer to this structure, and op |
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123 | is the result; this assumes twos complement arithmetic). |
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124 | |||
125 | If this field is not NULL, then simply call it with the |
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126 | instruction value. It will return the value of the operand. If |
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127 | the INVALID argument is not NULL, *INVALID will be set to |
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128 | non-zero if this operand type can not actually be extracted from |
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129 | this operand (i.e., the instruction does not match). If the |
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130 | operand is valid, *INVALID will not be changed. */ |
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131 | int (*extract) (unsigned instruction, int *invalid); |
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132 | }; |
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133 | |||
134 | /* Elements in the table are retrieved by indexing with values from |
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135 | the operands field of the alpha_opcodes table. */ |
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136 | |||
137 | extern const struct alpha_operand alpha_operands[]; |
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138 | extern const unsigned alpha_num_operands; |
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139 | |||
140 | /* Values defined for the flags field of a struct alpha_operand. */ |
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141 | |||
142 | /* Mask for selecting the type for typecheck purposes */ |
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143 | #define AXP_OPERAND_TYPECHECK_MASK \ |
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144 | (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ |
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145 | AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ |
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146 | AXP_OPERAND_UNSIGNED) |
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147 | |||
148 | /* This operand does not actually exist in the assembler input. This |
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149 | is used to support extended mnemonics, for which two operands fields |
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150 | are identical. The assembler should call the insert function with |
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151 | any op value. The disassembler should call the extract function, |
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152 | ignore the return value, and check the value placed in the invalid |
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153 | argument. */ |
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154 | #define AXP_OPERAND_FAKE 01 |
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155 | |||
156 | /* The operand should be wrapped in parentheses rather than separated |
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157 | from the previous by a comma. This is used for the load and store |
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158 | instructions which want their operands to look like "Ra,disp(Rb)". */ |
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159 | #define AXP_OPERAND_PARENS 02 |
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160 | |||
161 | /* Used in combination with PARENS, this supresses the supression of |
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162 | the comma. This is used for "jmp Ra,(Rb),hint". */ |
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163 | #define AXP_OPERAND_COMMA 04 |
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164 | |||
165 | /* This operand names an integer register. */ |
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166 | #define AXP_OPERAND_IR 010 |
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167 | |||
168 | /* This operand names a floating point register. */ |
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169 | #define AXP_OPERAND_FPR 020 |
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170 | |||
171 | /* This operand is a relative branch displacement. The disassembler |
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172 | prints these symbolically if possible. */ |
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173 | #define AXP_OPERAND_RELATIVE 040 |
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174 | |||
175 | /* This operand takes signed values. */ |
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176 | #define AXP_OPERAND_SIGNED 0100 |
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177 | |||
178 | /* This operand takes unsigned values. This exists primarily so that |
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179 | a flags value of 0 can be treated as end-of-arguments. */ |
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180 | #define AXP_OPERAND_UNSIGNED 0200 |
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181 | |||
182 | /* Supress overflow detection on this field. This is used for hints. */ |
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183 | #define AXP_OPERAND_NOOVERFLOW 0400 |
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184 | |||
185 | /* Mask for optional argument default value. */ |
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186 | #define AXP_OPERAND_OPTIONAL_MASK 07000 |
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187 | |||
188 | /* This operand defaults to zero. This is used for jump hints. */ |
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189 | #define AXP_OPERAND_DEFAULT_ZERO 01000 |
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190 | |||
191 | /* This operand should default to the first (real) operand and is used |
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192 | in conjunction with AXP_OPERAND_OPTIONAL. This allows |
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193 | "and $0,3,$0" to be written as "and $0,3", etc. I don't like |
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194 | it, but it's what DEC does. */ |
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195 | #define AXP_OPERAND_DEFAULT_FIRST 02000 |
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196 | |||
197 | /* Similarly, this operand should default to the second (real) operand. |
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198 | This allows "negl $0" instead of "negl $0,$0". */ |
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199 | #define AXP_OPERAND_DEFAULT_SECOND 04000 |
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200 | |||
201 | |||
202 | /* Register common names */ |
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203 | |||
204 | #define AXP_REG_V0 0 |
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205 | #define AXP_REG_T0 1 |
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206 | #define AXP_REG_T1 2 |
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207 | #define AXP_REG_T2 3 |
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208 | #define AXP_REG_T3 4 |
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209 | #define AXP_REG_T4 5 |
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210 | #define AXP_REG_T5 6 |
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211 | #define AXP_REG_T6 7 |
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212 | #define AXP_REG_T7 8 |
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213 | #define AXP_REG_S0 9 |
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214 | #define AXP_REG_S1 10 |
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215 | #define AXP_REG_S2 11 |
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216 | #define AXP_REG_S3 12 |
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217 | #define AXP_REG_S4 13 |
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218 | #define AXP_REG_S5 14 |
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219 | #define AXP_REG_FP 15 |
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220 | #define AXP_REG_A0 16 |
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221 | #define AXP_REG_A1 17 |
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222 | #define AXP_REG_A2 18 |
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223 | #define AXP_REG_A3 19 |
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224 | #define AXP_REG_A4 20 |
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225 | #define AXP_REG_A5 21 |
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226 | #define AXP_REG_T8 22 |
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227 | #define AXP_REG_T9 23 |
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228 | #define AXP_REG_T10 24 |
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229 | #define AXP_REG_T11 25 |
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230 | #define AXP_REG_RA 26 |
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231 | #define AXP_REG_PV 27 |
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232 | #define AXP_REG_T12 27 |
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233 | #define AXP_REG_AT 28 |
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234 | #define AXP_REG_GP 29 |
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235 | #define AXP_REG_SP 30 |
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236 | #define AXP_REG_ZERO 31 |
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237 | |||
238 | #endif /* OPCODE_ALPHA_H */><>><>><>><>><> |