WebSVN – Kolibri OS – Blame – /contrib/toolchain/binutils/gas/config/tc-i386.c

Rev	Author	Line No.	Line
5222	serge	1	/* tc-i386.c -- Assemble code for the Intel 80386
		2	Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
		3	2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
		4	2012
		5	Free Software Foundation, Inc.
		6
		7	This file is part of GAS, the GNU Assembler.
		8
		9	GAS is free software; you can redistribute it and/or modify
		10	it under the terms of the GNU General Public License as published by
		11	the Free Software Foundation; either version 3, or (at your option)
		12	any later version.
		13
		14	GAS is distributed in the hope that it will be useful,
		15	but WITHOUT ANY WARRANTY; without even the implied warranty of
		16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		17	GNU General Public License for more details.
		18
		19	You should have received a copy of the GNU General Public License
		20	along with GAS; see the file COPYING. If not, write to the Free
		21	Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
		22	02110-1301, USA. */
		23
		24	/* Intel 80386 machine specific gas.
		25	Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
		26	x86_64 support by Jan Hubicka (jh@suse.cz)
		27	VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
		28	Bugs & suggestions are completely welcome. This is free software.
		29	Please help us make it better. */
		30
		31	#include "as.h"
		32	#include "safe-ctype.h"
		33	#include "subsegs.h"
		34	#include "dwarf2dbg.h"
		35	#include "dw2gencfi.h"
		36	#include "elf/x86-64.h"
		37	#include "opcodes/i386-init.h"
		38
		39	#ifndef REGISTER_WARNINGS
		40	#define REGISTER_WARNINGS 1
		41	#endif
		42
		43	#ifndef INFER_ADDR_PREFIX
		44	#define INFER_ADDR_PREFIX 1
		45	#endif
		46
		47	#ifndef DEFAULT_ARCH
		48	#define DEFAULT_ARCH "i386"
		49	#endif
		50
		51	#ifndef INLINE
		52	#if __GNUC__ >= 2
		53	#define INLINE __inline__
		54	#else
		55	#define INLINE
		56	#endif
		57	#endif
		58
		59	/* Prefixes will be emitted in the order defined below.
		60	WAIT_PREFIX must be the first prefix since FWAIT is really is an
		61	instruction, and so must come before any prefixes.
		62	The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
		63	REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
		64	#define WAIT_PREFIX 0
		65	#define SEG_PREFIX 1
		66	#define ADDR_PREFIX 2
		67	#define DATA_PREFIX 3
		68	#define REP_PREFIX 4
		69	#define HLE_PREFIX REP_PREFIX
		70	#define BND_PREFIX REP_PREFIX
		71	#define LOCK_PREFIX 5
		72	#define REX_PREFIX 6 /* must come last. */
		73	#define MAX_PREFIXES 7 /* max prefixes per opcode */
		74
		75	/* we define the syntax here (modulo base,index,scale syntax) */
		76	#define REGISTER_PREFIX '%'
		77	#define IMMEDIATE_PREFIX '$'
		78	#define ABSOLUTE_PREFIX '*'
		79
		80	/* these are the instruction mnemonic suffixes in AT&T syntax or
		81	memory operand size in Intel syntax. */
		82	#define WORD_MNEM_SUFFIX 'w'
		83	#define BYTE_MNEM_SUFFIX 'b'
		84	#define SHORT_MNEM_SUFFIX 's'
		85	#define LONG_MNEM_SUFFIX 'l'
		86	#define QWORD_MNEM_SUFFIX 'q'
		87	#define XMMWORD_MNEM_SUFFIX 'x'
		88	#define YMMWORD_MNEM_SUFFIX 'y'
		89	#define ZMMWORD_MNEM_SUFFIX 'z'
		90	/* Intel Syntax. Use a non-ascii letter since since it never appears
		91	in instructions. */
		92	#define LONG_DOUBLE_MNEM_SUFFIX '\1'
		93
		94	#define END_OF_INSN '\0'
		95
		96	/*
		97	'templates' is for grouping together 'template' structures for opcodes
		98	of the same name. This is only used for storing the insns in the grand
		99	ole hash table of insns.
		100	The templates themselves start at START and range up to (but not including)
		101	END.
		102	*/
		103	typedef struct
		104	{
		105	const insn_template *start;
		106	const insn_template *end;
		107	}
		108	templates;
		109
		110	/* 386 operand encoding bytes: see 386 book for details of this. */
		111	typedef struct
		112	{
		113	unsigned int regmem; /* codes register or memory operand */
		114	unsigned int reg; /* codes register operand (or extended opcode) */
		115	unsigned int mode; /* how to interpret regmem & reg */
		116	}
		117	modrm_byte;
		118
		119	/* x86-64 extension prefix. */
		120	typedef int rex_byte;
		121
		122	/* 386 opcode byte to code indirect addressing. */
		123	typedef struct
		124	{
		125	unsigned base;
		126	unsigned index;
		127	unsigned scale;
		128	}
		129	sib_byte;
		130
		131	/* x86 arch names, types and features */
		132	typedef struct
		133	{
		134	const char name; / arch name */
		135	unsigned int len; /* arch string length */
		136	enum processor_type type; /* arch type */
		137	i386_cpu_flags flags; /* cpu feature flags */
		138	unsigned int skip; /* show_arch should skip this. */
		139	unsigned int negated; /* turn off indicated flags. */
		140	}
		141	arch_entry;
		142
		143	static void update_code_flag (int, int);
		144	static void set_code_flag (int);
		145	static void set_16bit_gcc_code_flag (int);
		146	static void set_intel_syntax (int);
		147	static void set_intel_mnemonic (int);
		148	static void set_allow_index_reg (int);
		149	static void set_check (int);
		150	static void set_cpu_arch (int);
		151	#ifdef TE_PE
		152	static void pe_directive_secrel (int);
		153	#endif
		154	static void signed_cons (int);
		155	static char *output_invalid (int c);
		156	static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
		157	const char *);
		158	static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
		159	const char *);
		160	static int i386_att_operand (char *);
		161	static int i386_intel_operand (char *, int);
		162	static int i386_intel_simplify (expressionS *);
		163	static int i386_intel_parse_name (const char , expressionS );
		164	static const reg_entry parse_register (char , char **);
		165	static char parse_insn (char , char *);
		166	static char parse_operands (char , const char *);
		167	static void swap_operands (void);
		168	static void swap_2_operands (int, int);
		169	static void optimize_imm (void);
		170	static void optimize_disp (void);
		171	static const insn_template *match_template (void);
		172	static int check_string (void);
		173	static int process_suffix (void);
		174	static int check_byte_reg (void);
		175	static int check_long_reg (void);
		176	static int check_qword_reg (void);
		177	static int check_word_reg (void);
		178	static int finalize_imm (void);
		179	static int process_operands (void);
		180	static const seg_entry *build_modrm_byte (void);
		181	static void output_insn (void);
		182	static void output_imm (fragS *, offsetT);
		183	static void output_disp (fragS *, offsetT);
		184	#ifndef I386COFF
		185	static void s_bss (int);
		186	#endif
		187	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		188	static void handle_large_common (int small ATTRIBUTE_UNUSED);
		189	#endif
		190
		191	static const char *default_arch = DEFAULT_ARCH;
		192
		193	/* This struct describes rounding control and SAE in the instruction. */
		194	struct RC_Operation
		195	{
		196	enum rc_type
		197	{
		198	rne = 0,
		199	rd,
		200	ru,
		201	rz,
		202	saeonly
		203	} type;
		204	int operand;
		205	};
		206
		207	static struct RC_Operation rc_op;
		208
		209	/* The struct describes masking, applied to OPERAND in the instruction.
		210	MASK is a pointer to the corresponding mask register. ZEROING tells
		211	whether merging or zeroing mask is used. */
		212	struct Mask_Operation
		213	{
		214	const reg_entry *mask;
		215	unsigned int zeroing;
		216	/* The operand where this operation is associated. */
		217	int operand;
		218	};
		219
		220	static struct Mask_Operation mask_op;
		221
		222	/* The struct describes broadcasting, applied to OPERAND. FACTOR is
		223	broadcast factor. */
		224	struct Broadcast_Operation
		225	{
		226	/* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
		227	int type;
		228
		229	/* Index of broadcasted operand. */
		230	int operand;
		231	};
		232
		233	static struct Broadcast_Operation broadcast_op;
		234
		235	/* VEX prefix. */
		236	typedef struct
		237	{
		238	/* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
		239	unsigned char bytes[4];
		240	unsigned int length;
		241	/* Destination or source register specifier. */
		242	const reg_entry *register_specifier;
		243	} vex_prefix;
		244
		245	/* 'md_assemble ()' gathers together information and puts it into a
		246	i386_insn. */
		247
		248	union i386_op
		249	{
		250	expressionS *disps;
		251	expressionS *imms;
		252	const reg_entry *regs;
		253	};
		254
		255	enum i386_error
		256	{
		257	operand_size_mismatch,
		258	operand_type_mismatch,
		259	register_type_mismatch,
		260	number_of_operands_mismatch,
		261	invalid_instruction_suffix,
		262	bad_imm4,
		263	old_gcc_only,
		264	unsupported_with_intel_mnemonic,
		265	unsupported_syntax,
		266	unsupported,
		267	invalid_vsib_address,
		268	invalid_vector_register_set,
		269	unsupported_vector_index_register,
		270	unsupported_broadcast,
		271	broadcast_not_on_src_operand,
		272	broadcast_needed,
		273	unsupported_masking,
		274	mask_not_on_destination,
		275	no_default_mask,
		276	unsupported_rc_sae,
		277	rc_sae_operand_not_last_imm,
		278	invalid_register_operand,
		279	try_vector_disp8
		280	};
		281
		282	struct _i386_insn
		283	{
		284	/* TM holds the template for the insn were currently assembling. */
		285	insn_template tm;
		286
		287	/* SUFFIX holds the instruction size suffix for byte, word, dword
		288	or qword, if given. */
		289	char suffix;
		290
		291	/* OPERANDS gives the number of given operands. */
		292	unsigned int operands;
		293
		294	/* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
		295	of given register, displacement, memory operands and immediate
		296	operands. */
		297	unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
		298
		299	/* TYPES [i] is the type (see above #defines) which tells us how to
		300	use OP[i] for the corresponding operand. */
		301	i386_operand_type types[MAX_OPERANDS];
		302
		303	/* Displacement expression, immediate expression, or register for each
		304	operand. */
		305	union i386_op op[MAX_OPERANDS];
		306
		307	/* Flags for operands. */
		308	unsigned int flags[MAX_OPERANDS];
		309	#define Operand_PCrel 1
		310
		311	/* Relocation type for operand */
		312	enum bfd_reloc_code_real reloc[MAX_OPERANDS];
		313
		314	/* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
		315	the base index byte below. */
		316	const reg_entry *base_reg;
		317	const reg_entry *index_reg;
		318	unsigned int log2_scale_factor;
		319
		320	/* SEG gives the seg_entries of this insn. They are zero unless
		321	explicit segment overrides are given. */
		322	const seg_entry *seg[2];
		323
		324	/* PREFIX holds all the given prefix opcodes (usually null).
		325	PREFIXES is the number of prefix opcodes. */
		326	unsigned int prefixes;
		327	unsigned char prefix[MAX_PREFIXES];
		328
		329	/* RM and SIB are the modrm byte and the sib byte where the
		330	addressing modes of this insn are encoded. */
		331	modrm_byte rm;
		332	rex_byte rex;
		333	rex_byte vrex;
		334	sib_byte sib;
		335	vex_prefix vex;
		336
		337	/* Masking attributes. */
		338	struct Mask_Operation *mask;
		339
		340	/* Rounding control and SAE attributes. */
		341	struct RC_Operation *rounding;
		342
		343	/* Broadcasting attributes. */
		344	struct Broadcast_Operation *broadcast;
		345
		346	/* Compressed disp8N attribute. /
		347	unsigned int memshift;
		348
		349	/* Swap operand in encoding. */
		350	unsigned int swap_operand;
		351
		352	/* Prefer 8bit or 32bit displacement in encoding. */
		353	enum
		354	{
		355	disp_encoding_default = 0,
		356	disp_encoding_8bit,
		357	disp_encoding_32bit
		358	} disp_encoding;
		359
		360	/* REP prefix. */
		361	const char *rep_prefix;
		362
		363	/* HLE prefix. */
		364	const char *hle_prefix;
		365
		366	/* Have BND prefix. */
		367	const char *bnd_prefix;
		368
		369	/* Need VREX to support upper 16 registers. */
		370	int need_vrex;
		371
		372	/* Error message. */
		373	enum i386_error error;
		374	};
		375
		376	typedef struct _i386_insn i386_insn;
		377
		378	/* Link RC type with corresponding string, that'll be looked for in
		379	asm. */
		380	struct RC_name
		381	{
		382	enum rc_type type;
		383	const char *name;
		384	unsigned int len;
		385	};
		386
		387	static const struct RC_name RC_NamesTable[] =
		388	{
		389	{ rne, STRING_COMMA_LEN ("rn-sae") },
		390	{ rd, STRING_COMMA_LEN ("rd-sae") },
		391	{ ru, STRING_COMMA_LEN ("ru-sae") },
		392	{ rz, STRING_COMMA_LEN ("rz-sae") },
		393	{ saeonly, STRING_COMMA_LEN ("sae") },
		394	};
		395
		396	/* List of chars besides those in app.c:symbol_chars that can start an
		397	operand. Used to prevent the scrubber eating vital white-space. */
		398	const char extra_symbol_chars[] = "*%-([{"
		399	#ifdef LEX_AT
		400	"@"
		401	#endif
		402	#ifdef LEX_QM
		403	"?"
		404	#endif
		405	;
		406
		407	#if (defined (TE_I386AIX) \
		408	\|\| ((defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)) \
		409	&& !defined (TE_GNU) \
		410	&& !defined (TE_LINUX) \
		411	&& !defined (TE_NACL) \
		412	&& !defined (TE_NETWARE) \
		413	&& !defined (TE_FreeBSD) \
		414	&& !defined (TE_DragonFly) \
		415	&& !defined (TE_NetBSD)))
		416	/* This array holds the chars that always start a comment. If the
		417	pre-processor is disabled, these aren't very useful. The option
		418	--divide will remove '/' from this list. */
		419	const char *i386_comment_chars = "#/";
		420	#define SVR4_COMMENT_CHARS 1
		421	#define PREFIX_SEPARATOR '\\'
		422
		423	#else
		424	const char *i386_comment_chars = "#";
		425	#define PREFIX_SEPARATOR '/'
		426	#endif
		427
		428	/* This array holds the chars that only start a comment at the beginning of
		429	a line. If the line seems to have the form '# 123 filename'
		430	.line and .file directives will appear in the pre-processed output.
		431	Note that input_file.c hand checks for '#' at the beginning of the
		432	first line of the input file. This is because the compiler outputs
		433	#NO_APP at the beginning of its output.
		434	Also note that comments started like this one will always work if
		435	'/' isn't otherwise defined. */
		436	const char line_comment_chars[] = "#/";
		437
		438	const char line_separator_chars[] = ";";
		439
		440	/* Chars that can be used to separate mant from exp in floating point
		441	nums. */
		442	const char EXP_CHARS[] = "eE";
		443
		444	/* Chars that mean this number is a floating point constant
		445	As in 0f12.456
		446	or 0d1.2345e12. */
		447	const char FLT_CHARS[] = "fFdDxX";
		448
		449	/* Tables for lexical analysis. */
		450	static char mnemonic_chars[256];
		451	static char register_chars[256];
		452	static char operand_chars[256];
		453	static char identifier_chars[256];
		454	static char digit_chars[256];
		455
		456	/* Lexical macros. */
		457	#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
		458	#define is_operand_char(x) (operand_chars[(unsigned char) x])
		459	#define is_register_char(x) (register_chars[(unsigned char) x])
		460	#define is_space_char(x) ((x) == ' ')
		461	#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
		462	#define is_digit_char(x) (digit_chars[(unsigned char) x])
		463
		464	/* All non-digit non-letter characters that may occur in an operand. */
		465	static char operand_special_chars[] = "%$-+(,)*._~/<>\|&^!:[@]";
		466
		467	/* md_assemble() always leaves the strings it's passed unaltered. To
		468	effect this we maintain a stack of saved characters that we've smashed
		469	with '\0's (indicating end of strings for various sub-fields of the
		470	assembler instruction). */
		471	static char save_stack[32];
		472	static char *save_stack_p;
		473	#define END_STRING_AND_SAVE(s) \
		474	do { save_stack_p++ = (s); *(s) = '\0'; } while (0)
		475	#define RESTORE_END_STRING(s) \
		476	do { (s) = --save_stack_p; } while (0)
		477
		478	/* The instruction we're assembling. */
		479	static i386_insn i;
		480
		481	/* Possible templates for current insn. */
		482	static const templates *current_templates;
		483
		484	/* Per instruction expressionS buffers: max displacements & immediates. */
		485	static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
		486	static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
		487
		488	/* Current operand we are working on. */
		489	static int this_operand = -1;
		490
		491	/* We support four different modes. FLAG_CODE variable is used to distinguish
		492	these. */
		493
		494	enum flag_code {
		495	CODE_32BIT,
		496	CODE_16BIT,
		497	CODE_64BIT };
		498
		499	static enum flag_code flag_code;
		500	static unsigned int object_64bit;
		501	static unsigned int disallow_64bit_reloc;
		502	static int use_rela_relocations = 0;
		503
		504	#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
		505	\|\| defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) \
		506	\|\| defined (TE_PE) \|\| defined (TE_PEP) \|\| defined (OBJ_MACH_O))
		507
		508	/* The ELF ABI to use. */
		509	enum x86_elf_abi
		510	{
		511	I386_ABI,
		512	X86_64_ABI,
		513	X86_64_X32_ABI
		514	};
		515
		516	static enum x86_elf_abi x86_elf_abi = I386_ABI;
		517	#endif
		518
		519	/* 1 for intel syntax,
		520
		521	static int intel_syntax = 0;
		522
		523	/* 1 for intel mnemonic,
		524
		525	static int intel_mnemonic = !SYSV386_COMPAT;
		526
		527	/* 1 if support old (<= 2.8.1) versions of gcc. */
		528	static int old_gcc = OLDGCC_COMPAT;
		529
		530	/* 1 if pseudo registers are permitted. */
		531	static int allow_pseudo_reg = 0;
		532
		533	/* 1 if register prefix % not required. */
		534	static int allow_naked_reg = 0;
		535
		536	/* 1 if the assembler should add BND prefix for all control-tranferring
		537	instructions supporting it, even if this prefix wasn't specified
		538	explicitly. */
		539	static int add_bnd_prefix = 0;
		540
		541	/* 1 if pseudo index register, eiz/riz, is allowed . */
		542	static int allow_index_reg = 0;
		543
		544	static enum check_kind
		545	{
		546	check_none = 0,
		547	check_warning,
		548	check_error
		549	}
		550	sse_check, operand_check = check_warning;
		551
		552	/* Register prefix used for error message. */
		553	static const char *register_prefix = "%";
		554
		555	/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
		556	leave, push, and pop instructions so that gcc has the same stack
		557	frame as in 32 bit mode. */
		558	static char stackop_size = '\0';
		559
		560	/* Non-zero to optimize code alignment. */
		561	int optimize_align_code = 1;
		562
		563	/* Non-zero to quieten some warnings. */
		564	static int quiet_warnings = 0;
		565
		566	/* CPU name. */
		567	static const char *cpu_arch_name = NULL;
		568	static char *cpu_sub_arch_name = NULL;
		569
		570	/* CPU feature flags. */
		571	static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
		572
		573	/* If we have selected a cpu we are generating instructions for. */
		574	static int cpu_arch_tune_set = 0;
		575
		576	/* Cpu we are generating instructions for. */
		577	enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
		578
		579	/* CPU feature flags of cpu we are generating instructions for. */
		580	static i386_cpu_flags cpu_arch_tune_flags;
		581
		582	/* CPU instruction set architecture used. */
		583	enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
		584
		585	/* CPU feature flags of instruction set architecture used. */
		586	i386_cpu_flags cpu_arch_isa_flags;
		587
		588	/* If set, conditional jumps are not automatically promoted to handle
		589	larger than a byte offset. */
		590	static unsigned int no_cond_jump_promotion = 0;
		591
		592	/* Encode SSE instructions with VEX prefix. */
		593	static unsigned int sse2avx;
		594
		595	/* Encode scalar AVX instructions with specific vector length. */
		596	static enum
		597	{
		598	vex128 = 0,
		599	vex256
		600	} avxscalar;
		601
		602	/* Encode scalar EVEX LIG instructions with specific vector length. */
		603	static enum
		604	{
		605	evexl128 = 0,
		606	evexl256,
		607	evexl512
		608	} evexlig;
		609
		610	/* Encode EVEX WIG instructions with specific evex.w. */
		611	static enum
		612	{
		613	evexw0 = 0,
		614	evexw1
		615	} evexwig;
		616
		617	/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
		618	static symbolS *GOT_symbol;
		619
		620	/* The dwarf2 return column, adjusted for 32 or 64 bit. */
		621	unsigned int x86_dwarf2_return_column;
		622
		623	/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
		624	int x86_cie_data_alignment;
		625
		626	/* Interface to relax_segment.
		627	There are 3 major relax states for 386 jump insns because the
		628	different types of jumps add different sizes to frags when we're
		629	figuring out what sort of jump to choose to reach a given label. */
		630
		631	/* Types. */
		632	#define UNCOND_JUMP 0
		633	#define COND_JUMP 1
		634	#define COND_JUMP86 2
		635
		636	/* Sizes. */
		637	#define CODE16 1
		638	#define SMALL 0
		639	#define SMALL16 (SMALL \| CODE16)
		640	#define BIG 2
		641	#define BIG16 (BIG \| CODE16)
		642
		643	#ifndef INLINE
		644	#ifdef __GNUC__
		645	#define INLINE __inline__
		646	#else
		647	#define INLINE
		648	#endif
		649	#endif
		650
		651	#define ENCODE_RELAX_STATE(type, size) \
		652	((relax_substateT) (((type) << 2) \| (size)))
		653	#define TYPE_FROM_RELAX_STATE(s) \
		654	((s) >> 2)
		655	#define DISP_SIZE_FROM_RELAX_STATE(s) \
		656	((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
		657
		658	/* This table is used by relax_frag to promote short jumps to long
		659	ones where necessary. SMALL (short) jumps may be promoted to BIG
		660	(32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
		661	don't allow a short jump in a 32 bit code segment to be promoted to
		662	a 16 bit offset jump because it's slower (requires data size
		663	prefix), and doesn't work, unless the destination is in the bottom
		664	64k of the code segment (The top 16 bits of eip are zeroed). */
		665
		666	const relax_typeS md_relax_table[] =
		667	{
		668	/* The fields are:
		669	1) most positive reach of this state,
		670	2) most negative reach of this state,
		671	3) how many bytes this mode will have in the variable part of the frag
		672	4) which index into the table to try if we can't fit into this one. */
		673
		674	/* UNCOND_JUMP states. */
		675	{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
		676	{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
		677	/* dword jmp adds 4 bytes to frag:
		678
		679	{0, 0, 4, 0},
		680	/* word jmp adds 2 byte2 to frag:
		681
		682	{0, 0, 2, 0},
		683
		684	/* COND_JUMP states. */
		685	{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
		686	{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
		687	/* dword conditionals adds 5 bytes to frag:
		688	1 extra opcode byte, 4 displacement bytes. */
		689	{0, 0, 5, 0},
		690	/* word conditionals add 3 bytes to frag:
		691	1 extra opcode byte, 2 displacement bytes. */
		692	{0, 0, 3, 0},
		693
		694	/* COND_JUMP86 states. */
		695	{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
		696	{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
		697	/* dword conditionals adds 5 bytes to frag:
		698	1 extra opcode byte, 4 displacement bytes. */
		699	{0, 0, 5, 0},
		700	/* word conditionals add 4 bytes to frag:
		701	1 displacement byte and a 3 byte long branch insn. */
		702	{0, 0, 4, 0}
		703	};
		704
		705	static const arch_entry cpu_arch[] =
		706	{
		707	/* Do not replace the first two entries - i386_target_format()
		708	relies on them being there in this order. */
		709	{ STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
		710	CPU_GENERIC32_FLAGS, 0, 0 },
		711	{ STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
		712	CPU_GENERIC64_FLAGS, 0, 0 },
		713	{ STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
		714	CPU_NONE_FLAGS, 0, 0 },
		715	{ STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
		716	CPU_I186_FLAGS, 0, 0 },
		717	{ STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
		718	CPU_I286_FLAGS, 0, 0 },
		719	{ STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
		720	CPU_I386_FLAGS, 0, 0 },
		721	{ STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
		722	CPU_I486_FLAGS, 0, 0 },
		723	{ STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
		724	CPU_I586_FLAGS, 0, 0 },
		725	{ STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
		726	CPU_I686_FLAGS, 0, 0 },
		727	{ STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
		728	CPU_I586_FLAGS, 0, 0 },
		729	{ STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
		730	CPU_PENTIUMPRO_FLAGS, 0, 0 },
		731	{ STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
		732	CPU_P2_FLAGS, 0, 0 },
		733	{ STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
		734	CPU_P3_FLAGS, 0, 0 },
		735	{ STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
		736	CPU_P4_FLAGS, 0, 0 },
		737	{ STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
		738	CPU_CORE_FLAGS, 0, 0 },
		739	{ STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
		740	CPU_NOCONA_FLAGS, 0, 0 },
		741	{ STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
		742	CPU_CORE_FLAGS, 1, 0 },
		743	{ STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
		744	CPU_CORE_FLAGS, 0, 0 },
		745	{ STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
		746	CPU_CORE2_FLAGS, 1, 0 },
		747	{ STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
		748	CPU_CORE2_FLAGS, 0, 0 },
		749	{ STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
		750	CPU_COREI7_FLAGS, 0, 0 },
		751	{ STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
		752	CPU_L1OM_FLAGS, 0, 0 },
		753	{ STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
		754	CPU_K1OM_FLAGS, 0, 0 },
		755	{ STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
		756	CPU_K6_FLAGS, 0, 0 },
		757	{ STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
		758	CPU_K6_2_FLAGS, 0, 0 },
		759	{ STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
		760	CPU_ATHLON_FLAGS, 0, 0 },
		761	{ STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
		762	CPU_K8_FLAGS, 1, 0 },
		763	{ STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
		764	CPU_K8_FLAGS, 0, 0 },
		765	{ STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
		766	CPU_K8_FLAGS, 0, 0 },
		767	{ STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
		768	CPU_AMDFAM10_FLAGS, 0, 0 },
		769	{ STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
		770	CPU_BDVER1_FLAGS, 0, 0 },
		771	{ STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
		772	CPU_BDVER2_FLAGS, 0, 0 },
		773	{ STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
		774	CPU_BDVER3_FLAGS, 0, 0 },
		775	{ STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
		776	CPU_BTVER1_FLAGS, 0, 0 },
		777	{ STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
		778	CPU_BTVER2_FLAGS, 0, 0 },
		779	{ STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
		780	CPU_8087_FLAGS, 0, 0 },
		781	{ STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
		782	CPU_287_FLAGS, 0, 0 },
		783	{ STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
		784	CPU_387_FLAGS, 0, 0 },
		785	{ STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
		786	CPU_ANY87_FLAGS, 0, 1 },
		787	{ STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
		788	CPU_MMX_FLAGS, 0, 0 },
		789	{ STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
		790	CPU_3DNOWA_FLAGS, 0, 1 },
		791	{ STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
		792	CPU_SSE_FLAGS, 0, 0 },
		793	{ STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
		794	CPU_SSE2_FLAGS, 0, 0 },
		795	{ STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
		796	CPU_SSE3_FLAGS, 0, 0 },
		797	{ STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
		798	CPU_SSSE3_FLAGS, 0, 0 },
		799	{ STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
		800	CPU_SSE4_1_FLAGS, 0, 0 },
		801	{ STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
		802	CPU_SSE4_2_FLAGS, 0, 0 },
		803	{ STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
		804	CPU_SSE4_2_FLAGS, 0, 0 },
		805	{ STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
		806	CPU_ANY_SSE_FLAGS, 0, 1 },
		807	{ STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
		808	CPU_AVX_FLAGS, 0, 0 },
		809	{ STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
		810	CPU_AVX2_FLAGS, 0, 0 },
		811	{ STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
		812	CPU_AVX512F_FLAGS, 0, 0 },
		813	{ STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
		814	CPU_AVX512CD_FLAGS, 0, 0 },
		815	{ STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
		816	CPU_AVX512ER_FLAGS, 0, 0 },
		817	{ STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
		818	CPU_AVX512PF_FLAGS, 0, 0 },
		819	{ STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
		820	CPU_ANY_AVX_FLAGS, 0, 1 },
		821	{ STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
		822	CPU_VMX_FLAGS, 0, 0 },
		823	{ STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
		824	CPU_VMFUNC_FLAGS, 0, 0 },
		825	{ STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
		826	CPU_SMX_FLAGS, 0, 0 },
		827	{ STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
		828	CPU_XSAVE_FLAGS, 0, 0 },
		829	{ STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
		830	CPU_XSAVEOPT_FLAGS, 0, 0 },
		831	{ STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
		832	CPU_AES_FLAGS, 0, 0 },
		833	{ STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
		834	CPU_PCLMUL_FLAGS, 0, 0 },
		835	{ STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
		836	CPU_PCLMUL_FLAGS, 1, 0 },
		837	{ STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
		838	CPU_FSGSBASE_FLAGS, 0, 0 },
		839	{ STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
		840	CPU_RDRND_FLAGS, 0, 0 },
		841	{ STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
		842	CPU_F16C_FLAGS, 0, 0 },
		843	{ STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
		844	CPU_BMI2_FLAGS, 0, 0 },
		845	{ STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
		846	CPU_FMA_FLAGS, 0, 0 },
		847	{ STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
		848	CPU_FMA4_FLAGS, 0, 0 },
		849	{ STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
		850	CPU_XOP_FLAGS, 0, 0 },
		851	{ STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
		852	CPU_LWP_FLAGS, 0, 0 },
		853	{ STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
		854	CPU_MOVBE_FLAGS, 0, 0 },
		855	{ STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
		856	CPU_CX16_FLAGS, 0, 0 },
		857	{ STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
		858	CPU_EPT_FLAGS, 0, 0 },
		859	{ STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
		860	CPU_LZCNT_FLAGS, 0, 0 },
		861	{ STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
		862	CPU_HLE_FLAGS, 0, 0 },
		863	{ STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
		864	CPU_RTM_FLAGS, 0, 0 },
		865	{ STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
		866	CPU_INVPCID_FLAGS, 0, 0 },
		867	{ STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
		868	CPU_CLFLUSH_FLAGS, 0, 0 },
		869	{ STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
		870	CPU_NOP_FLAGS, 0, 0 },
		871	{ STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
		872	CPU_SYSCALL_FLAGS, 0, 0 },
		873	{ STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
		874	CPU_RDTSCP_FLAGS, 0, 0 },
		875	{ STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
		876	CPU_3DNOW_FLAGS, 0, 0 },
		877	{ STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
		878	CPU_3DNOWA_FLAGS, 0, 0 },
		879	{ STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
		880	CPU_PADLOCK_FLAGS, 0, 0 },
		881	{ STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
		882	CPU_SVME_FLAGS, 1, 0 },
		883	{ STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
		884	CPU_SVME_FLAGS, 0, 0 },
		885	{ STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
		886	CPU_SSE4A_FLAGS, 0, 0 },
		887	{ STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
		888	CPU_ABM_FLAGS, 0, 0 },
		889	{ STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
		890	CPU_BMI_FLAGS, 0, 0 },
		891	{ STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
		892	CPU_TBM_FLAGS, 0, 0 },
		893	{ STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
		894	CPU_ADX_FLAGS, 0, 0 },
		895	{ STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
		896	CPU_RDSEED_FLAGS, 0, 0 },
		897	{ STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
		898	CPU_PRFCHW_FLAGS, 0, 0 },
		899	{ STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
		900	CPU_SMAP_FLAGS, 0, 0 },
		901	{ STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
		902	CPU_MPX_FLAGS, 0, 0 },
		903	{ STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
		904	CPU_SHA_FLAGS, 0, 0 },
		905	};
		906
		907	#ifdef I386COFF
		908	/* Like s_lcomm_internal in gas/read.c but the alignment string
		909	is allowed to be optional. */
		910
		911	static symbolS *
		912	pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
		913	{
		914	addressT align = 0;
		915
		916	SKIP_WHITESPACE ();
		917
		918	if (needs_align
		919	&& *input_line_pointer == ',')
		920	{
		921	align = parse_align (needs_align - 1);
		922
		923	if (align == (addressT) -1)
		924	return NULL;
		925	}
		926	else
		927	{
		928	if (size >= 8)
		929	align = 3;
		930	else if (size >= 4)
		931	align = 2;
		932	else if (size >= 2)
		933	align = 1;
		934	else
		935	align = 0;
		936	}
		937
		938	bss_alloc (symbolP, size, align);
		939	return symbolP;
		940	}
		941
		942	static void
		943	pe_lcomm (int needs_align)
		944	{
		945	s_comm_internal (needs_align * 2, pe_lcomm_internal);
		946	}
		947	#endif
		948
		949	const pseudo_typeS md_pseudo_table[] =
		950	{
		951	#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
		952	{"align", s_align_bytes, 0},
		953	#else
		954	{"align", s_align_ptwo, 0},
		955	#endif
		956	{"arch", set_cpu_arch, 0},
		957	#ifndef I386COFF
		958	{"bss", s_bss, 0},
		959	#else
		960	{"lcomm", pe_lcomm, 1},
		961	#endif
		962	{"ffloat", float_cons, 'f'},
		963	{"dfloat", float_cons, 'd'},
		964	{"tfloat", float_cons, 'x'},
		965	{"value", cons, 2},
		966	{"slong", signed_cons, 4},
		967	{"noopt", s_ignore, 0},
		968	{"optim", s_ignore, 0},
		969	{"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
		970	{"code16", set_code_flag, CODE_16BIT},
		971	{"code32", set_code_flag, CODE_32BIT},
		972	{"code64", set_code_flag, CODE_64BIT},
		973	{"intel_syntax", set_intel_syntax, 1},
		974	{"att_syntax", set_intel_syntax, 0},
		975	{"intel_mnemonic", set_intel_mnemonic, 1},
		976	{"att_mnemonic", set_intel_mnemonic, 0},
		977	{"allow_index_reg", set_allow_index_reg, 1},
		978	{"disallow_index_reg", set_allow_index_reg, 0},
		979	{"sse_check", set_check, 0},
		980	{"operand_check", set_check, 1},
		981	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		982	{"largecomm", handle_large_common, 0},
		983	#else
		984	{"file", (void (*) (int)) dwarf2_directive_file, 0},
		985	{"loc", dwarf2_directive_loc, 0},
		986	{"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
		987	#endif
		988	#ifdef TE_PE
		989	{"secrel32", pe_directive_secrel, 0},
		990	#endif
		991	{0, 0, 0}
		992	};
		993
		994	/* For interface with expression (). */
		995	extern char *input_line_pointer;
		996
		997	/* Hash table for instruction mnemonic lookup. */
		998	static struct hash_control *op_hash;
		999
		1000	/* Hash table for register lookup. */
		1001	static struct hash_control *reg_hash;
		1002
		1003	void
		1004	i386_align_code (fragS *fragP, int count)
		1005	{
		1006	/* Various efficient no-op patterns for aligning code labels.
		1007	Note: Don't try to assemble the instructions in the comments.
		1008	0L and 0w are not legal. */
		1009	static const char f32_1[] =
		1010	{0x90}; /* nop */
		1011	static const char f32_2[] =
		1012	{0x66,0x90}; /* xchg %ax,%ax */
		1013	static const char f32_3[] =
		1014	{0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
		1015	static const char f32_4[] =
		1016	{0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
		1017	static const char f32_5[] =
		1018	{0x90, /* nop */
		1019	0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
		1020	static const char f32_6[] =
		1021	{0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
		1022	static const char f32_7[] =
		1023	{0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
		1024	static const char f32_8[] =
		1025	{0x90, /* nop */
		1026	0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
		1027	static const char f32_9[] =
		1028	{0x89,0xf6, /* movl %esi,%esi */
		1029	0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
		1030	static const char f32_10[] =
		1031	{0x8d,0x76,0x00, /* leal 0(%esi),%esi */
		1032	0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
		1033	static const char f32_11[] =
		1034	{0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
		1035	0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
		1036	static const char f32_12[] =
		1037	{0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
		1038	0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
		1039	static const char f32_13[] =
		1040	{0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
		1041	0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
		1042	static const char f32_14[] =
		1043	{0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
		1044	0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
		1045	static const char f16_3[] =
		1046	{0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
		1047	static const char f16_4[] =
		1048	{0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
		1049	static const char f16_5[] =
		1050	{0x90, /* nop */
		1051	0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
		1052	static const char f16_6[] =
		1053	{0x89,0xf6, /* mov %si,%si */
		1054	0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
		1055	static const char f16_7[] =
		1056	{0x8d,0x74,0x00, /* lea 0(%si),%si */
		1057	0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
		1058	static const char f16_8[] =
		1059	{0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
		1060	0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
		1061	static const char jump_31[] =
		1062	{0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
		1063	0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
		1064	0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
		1065	0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
		1066	static const char *const f32_patt[] = {
		1067	f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
		1068	f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
		1069	};
		1070	static const char *const f16_patt[] = {
		1071	f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
		1072	};
		1073	/* nopl (%[re]ax) */
		1074	static const char alt_3[] =
		1075	{0x0f,0x1f,0x00};
		1076	/* nopl 0(%[re]ax) */
		1077	static const char alt_4[] =
		1078	{0x0f,0x1f,0x40,0x00};
		1079	/* nopl 0(%[re]ax,%[re]ax,1) */
		1080	static const char alt_5[] =
		1081	{0x0f,0x1f,0x44,0x00,0x00};
		1082	/* nopw 0(%[re]ax,%[re]ax,1) */
		1083	static const char alt_6[] =
		1084	{0x66,0x0f,0x1f,0x44,0x00,0x00};
		1085	/* nopl 0L(%[re]ax) */
		1086	static const char alt_7[] =
		1087	{0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
		1088	/* nopl 0L(%[re]ax,%[re]ax,1) */
		1089	static const char alt_8[] =
		1090	{0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1091	/* nopw 0L(%[re]ax,%[re]ax,1) */
		1092	static const char alt_9[] =
		1093	{0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1094	/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
		1095	static const char alt_10[] =
		1096	{0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1097	/* data16
		1098	nopw %cs:0L(%[re]ax,%[re]ax,1) */
		1099	static const char alt_long_11[] =
		1100	{0x66,
		1101	0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1102	/* data16
		1103	data16
		1104	nopw %cs:0L(%[re]ax,%[re]ax,1) */
		1105	static const char alt_long_12[] =
		1106	{0x66,
		1107	0x66,
		1108	0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1109	/* data16
		1110	data16
		1111	data16
		1112	nopw %cs:0L(%[re]ax,%[re]ax,1) */
		1113	static const char alt_long_13[] =
		1114	{0x66,
		1115	0x66,
		1116	0x66,
		1117	0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1118	/* data16
		1119	data16
		1120	data16
		1121	data16
		1122	nopw %cs:0L(%[re]ax,%[re]ax,1) */
		1123	static const char alt_long_14[] =
		1124	{0x66,
		1125	0x66,
		1126	0x66,
		1127	0x66,
		1128	0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1129	/* data16
		1130	data16
		1131	data16
		1132	data16
		1133	data16
		1134	nopw %cs:0L(%[re]ax,%[re]ax,1) */
		1135	static const char alt_long_15[] =
		1136	{0x66,
		1137	0x66,
		1138	0x66,
		1139	0x66,
		1140	0x66,
		1141	0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1142	/* nopl 0(%[re]ax,%[re]ax,1)
		1143	nopw 0(%[re]ax,%[re]ax,1) */
		1144	static const char alt_short_11[] =
		1145	{0x0f,0x1f,0x44,0x00,0x00,
		1146	0x66,0x0f,0x1f,0x44,0x00,0x00};
		1147	/* nopw 0(%[re]ax,%[re]ax,1)
		1148	nopw 0(%[re]ax,%[re]ax,1) */
		1149	static const char alt_short_12[] =
		1150	{0x66,0x0f,0x1f,0x44,0x00,0x00,
		1151	0x66,0x0f,0x1f,0x44,0x00,0x00};
		1152	/* nopw 0(%[re]ax,%[re]ax,1)
		1153	nopl 0L(%[re]ax) */
		1154	static const char alt_short_13[] =
		1155	{0x66,0x0f,0x1f,0x44,0x00,0x00,
		1156	0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
		1157	/* nopl 0L(%[re]ax)
		1158	nopl 0L(%[re]ax) */
		1159	static const char alt_short_14[] =
		1160	{0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
		1161	0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
		1162	/* nopl 0L(%[re]ax)
		1163	nopl 0L(%[re]ax,%[re]ax,1) */
		1164	static const char alt_short_15[] =
		1165	{0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
		1166	0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
		1167	static const char *const alt_short_patt[] = {
		1168	f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
		1169	alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
		1170	alt_short_14, alt_short_15
		1171	};
		1172	static const char *const alt_long_patt[] = {
		1173	f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
		1174	alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
		1175	alt_long_14, alt_long_15
		1176	};
		1177
		1178	/* Only align for at least a positive non-zero boundary. */
		1179	if (count <= 0 \|\| count > MAX_MEM_FOR_RS_ALIGN_CODE)
		1180	return;
		1181
		1182	/* We need to decide which NOP sequence to use for 32bit and
		1183	64bit. When -mtune= is used:
		1184
		1185	1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
		1186	PROCESSOR_GENERIC32, f32_patt will be used.
		1187	2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
		1188	PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
		1189	PROCESSOR_GENERIC64, alt_long_patt will be used.
		1190	3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
		1191	PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
		1192	will be used.
		1193
		1194	When -mtune= isn't used, alt_long_patt will be used if
		1195	cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
		1196	be used.
		1197
		1198	When -march= or .arch is used, we can't use anything beyond
		1199	cpu_arch_isa_flags. */
		1200
		1201	if (flag_code == CODE_16BIT)
		1202	{
		1203	if (count > 8)
		1204	{
		1205	memcpy (fragP->fr_literal + fragP->fr_fix,
		1206	jump_31, count);
		1207	/* Adjust jump offset. */
		1208	fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
		1209	}
		1210	else
		1211	memcpy (fragP->fr_literal + fragP->fr_fix,
		1212	f16_patt[count - 1], count);
		1213	}
		1214	else
		1215	{
		1216	const char const patt = NULL;
		1217
		1218	if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
		1219	{
		1220	/* PROCESSOR_UNKNOWN means that all ISAs may be used. */
		1221	switch (cpu_arch_tune)
		1222	{
		1223	case PROCESSOR_UNKNOWN:
		1224	/* We use cpu_arch_isa_flags to check if we SHOULD
		1225	optimize with nops. */
		1226	if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
		1227	patt = alt_long_patt;
		1228	else
		1229	patt = f32_patt;
		1230	break;
		1231	case PROCESSOR_PENTIUM4:
		1232	case PROCESSOR_NOCONA:
		1233	case PROCESSOR_CORE:
		1234	case PROCESSOR_CORE2:
		1235	case PROCESSOR_COREI7:
		1236	case PROCESSOR_L1OM:
		1237	case PROCESSOR_K1OM:
		1238	case PROCESSOR_GENERIC64:
		1239	patt = alt_long_patt;
		1240	break;
		1241	case PROCESSOR_K6:
		1242	case PROCESSOR_ATHLON:
		1243	case PROCESSOR_K8:
		1244	case PROCESSOR_AMDFAM10:
		1245	case PROCESSOR_BD:
		1246	case PROCESSOR_BT:
		1247	patt = alt_short_patt;
		1248	break;
		1249	case PROCESSOR_I386:
		1250	case PROCESSOR_I486:
		1251	case PROCESSOR_PENTIUM:
		1252	case PROCESSOR_PENTIUMPRO:
		1253	case PROCESSOR_GENERIC32:
		1254	patt = f32_patt;
		1255	break;
		1256	}
		1257	}
		1258	else
		1259	{
		1260	switch (fragP->tc_frag_data.tune)
		1261	{
		1262	case PROCESSOR_UNKNOWN:
		1263	/* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
		1264	PROCESSOR_UNKNOWN. */
		1265	abort ();
		1266	break;
		1267
		1268	case PROCESSOR_I386:
		1269	case PROCESSOR_I486:
		1270	case PROCESSOR_PENTIUM:
		1271	case PROCESSOR_K6:
		1272	case PROCESSOR_ATHLON:
		1273	case PROCESSOR_K8:
		1274	case PROCESSOR_AMDFAM10:
		1275	case PROCESSOR_BD:
		1276	case PROCESSOR_BT:
		1277	case PROCESSOR_GENERIC32:
		1278	/* We use cpu_arch_isa_flags to check if we CAN optimize
		1279	with nops. */
		1280	if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
		1281	patt = alt_short_patt;
		1282	else
		1283	patt = f32_patt;
		1284	break;
		1285	case PROCESSOR_PENTIUMPRO:
		1286	case PROCESSOR_PENTIUM4:
		1287	case PROCESSOR_NOCONA:
		1288	case PROCESSOR_CORE:
		1289	case PROCESSOR_CORE2:
		1290	case PROCESSOR_COREI7:
		1291	case PROCESSOR_L1OM:
		1292	case PROCESSOR_K1OM:
		1293	if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
		1294	patt = alt_long_patt;
		1295	else
		1296	patt = f32_patt;
		1297	break;
		1298	case PROCESSOR_GENERIC64:
		1299	patt = alt_long_patt;
		1300	break;
		1301	}
		1302	}
		1303
		1304	if (patt == f32_patt)
		1305	{
		1306	/* If the padding is less than 15 bytes, we use the normal
		1307	ones. Otherwise, we use a jump instruction and adjust
		1308	its offset. */
		1309	int limit;
		1310
		1311	/* For 64bit, the limit is 3 bytes. */
		1312	if (flag_code == CODE_64BIT
		1313	&& fragP->tc_frag_data.isa_flags.bitfield.cpulm)
		1314	limit = 3;
		1315	else
		1316	limit = 15;
		1317	if (count < limit)
		1318	memcpy (fragP->fr_literal + fragP->fr_fix,
		1319	patt[count - 1], count);
		1320	else
		1321	{
		1322	memcpy (fragP->fr_literal + fragP->fr_fix,
		1323	jump_31, count);
		1324	/* Adjust jump offset. */
		1325	fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
		1326	}
		1327	}
		1328	else
		1329	{
		1330	/* Maximum length of an instruction is 15 byte. If the
		1331	padding is greater than 15 bytes and we don't use jump,
		1332	we have to break it into smaller pieces. */
		1333	int padding = count;
		1334	while (padding > 15)
		1335	{
		1336	padding -= 15;
		1337	memcpy (fragP->fr_literal + fragP->fr_fix + padding,
		1338	patt [14], 15);
		1339	}
		1340
		1341	if (padding)
		1342	memcpy (fragP->fr_literal + fragP->fr_fix,
		1343	patt [padding - 1], padding);
		1344	}
		1345	}
		1346	fragP->fr_var = count;
		1347	}
		1348
		1349	static INLINE int
		1350	operand_type_all_zero (const union i386_operand_type *x)
		1351	{
		1352	switch (ARRAY_SIZE(x->array))
		1353	{
		1354	case 3:
		1355	if (x->array[2])
		1356	return 0;
		1357	case 2:
		1358	if (x->array[1])
		1359	return 0;
		1360	case 1:
		1361	return !x->array[0];
		1362	default:
		1363	abort ();
		1364	}
		1365	}
		1366
		1367	static INLINE void
		1368	operand_type_set (union i386_operand_type *x, unsigned int v)
		1369	{
		1370	switch (ARRAY_SIZE(x->array))
		1371	{
		1372	case 3:
		1373	x->array[2] = v;
		1374	case 2:
		1375	x->array[1] = v;
		1376	case 1:
		1377	x->array[0] = v;
		1378	break;
		1379	default:
		1380	abort ();
		1381	}
		1382	}
		1383
		1384	static INLINE int
		1385	operand_type_equal (const union i386_operand_type *x,
		1386	const union i386_operand_type *y)
		1387	{
		1388	switch (ARRAY_SIZE(x->array))
		1389	{
		1390	case 3:
		1391	if (x->array[2] != y->array[2])
		1392	return 0;
		1393	case 2:
		1394	if (x->array[1] != y->array[1])
		1395	return 0;
		1396	case 1:
		1397	return x->array[0] == y->array[0];
		1398	break;
		1399	default:
		1400	abort ();
		1401	}
		1402	}
		1403
		1404	static INLINE int
		1405	cpu_flags_all_zero (const union i386_cpu_flags *x)
		1406	{
		1407	switch (ARRAY_SIZE(x->array))
		1408	{
		1409	case 3:
		1410	if (x->array[2])
		1411	return 0;
		1412	case 2:
		1413	if (x->array[1])
		1414	return 0;
		1415	case 1:
		1416	return !x->array[0];
		1417	default:
		1418	abort ();
		1419	}
		1420	}
		1421
		1422	static INLINE void
		1423	cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
		1424	{
		1425	switch (ARRAY_SIZE(x->array))
		1426	{
		1427	case 3:
		1428	x->array[2] = v;
		1429	case 2:
		1430	x->array[1] = v;
		1431	case 1:
		1432	x->array[0] = v;
		1433	break;
		1434	default:
		1435	abort ();
		1436	}
		1437	}
		1438
		1439	static INLINE int
		1440	cpu_flags_equal (const union i386_cpu_flags *x,
		1441	const union i386_cpu_flags *y)
		1442	{
		1443	switch (ARRAY_SIZE(x->array))
		1444	{
		1445	case 3:
		1446	if (x->array[2] != y->array[2])
		1447	return 0;
		1448	case 2:
		1449	if (x->array[1] != y->array[1])
		1450	return 0;
		1451	case 1:
		1452	return x->array[0] == y->array[0];
		1453	break;
		1454	default:
		1455	abort ();
		1456	}
		1457	}
		1458
		1459	static INLINE int
		1460	cpu_flags_check_cpu64 (i386_cpu_flags f)
		1461	{
		1462	return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
		1463	\|\| (flag_code != CODE_64BIT && f.bitfield.cpu64));
		1464	}
		1465
		1466	static INLINE i386_cpu_flags
		1467	cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
		1468	{
		1469	switch (ARRAY_SIZE (x.array))
		1470	{
		1471	case 3:
		1472	x.array [2] &= y.array [2];
		1473	case 2:
		1474	x.array [1] &= y.array [1];
		1475	case 1:
		1476	x.array [0] &= y.array [0];
		1477	break;
		1478	default:
		1479	abort ();
		1480	}
		1481	return x;
		1482	}
		1483
		1484	static INLINE i386_cpu_flags
		1485	cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
		1486	{
		1487	switch (ARRAY_SIZE (x.array))
		1488	{
		1489	case 3:
		1490	x.array [2] \|= y.array [2];
		1491	case 2:
		1492	x.array [1] \|= y.array [1];
		1493	case 1:
		1494	x.array [0] \|= y.array [0];
		1495	break;
		1496	default:
		1497	abort ();
		1498	}
		1499	return x;
		1500	}
		1501
		1502	static INLINE i386_cpu_flags
		1503	cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
		1504	{
		1505	switch (ARRAY_SIZE (x.array))
		1506	{
		1507	case 3:
		1508	x.array [2] &= ~y.array [2];
		1509	case 2:
		1510	x.array [1] &= ~y.array [1];
		1511	case 1:
		1512	x.array [0] &= ~y.array [0];
		1513	break;
		1514	default:
		1515	abort ();
		1516	}
		1517	return x;
		1518	}
		1519
		1520	#define CPU_FLAGS_ARCH_MATCH 0x1
		1521	#define CPU_FLAGS_64BIT_MATCH 0x2
		1522	#define CPU_FLAGS_AES_MATCH 0x4
		1523	#define CPU_FLAGS_PCLMUL_MATCH 0x8
		1524	#define CPU_FLAGS_AVX_MATCH 0x10
		1525
		1526	#define CPU_FLAGS_32BIT_MATCH \
		1527	(CPU_FLAGS_ARCH_MATCH \| CPU_FLAGS_AES_MATCH \
		1528	\| CPU_FLAGS_PCLMUL_MATCH \| CPU_FLAGS_AVX_MATCH)
		1529	#define CPU_FLAGS_PERFECT_MATCH \
		1530	(CPU_FLAGS_32BIT_MATCH \| CPU_FLAGS_64BIT_MATCH)
		1531
		1532	/* Return CPU flags match bits. */
		1533
		1534	static int
		1535	cpu_flags_match (const insn_template *t)
		1536	{
		1537	i386_cpu_flags x = t->cpu_flags;
		1538	int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
		1539
		1540	x.bitfield.cpu64 = 0;
		1541	x.bitfield.cpuno64 = 0;
		1542
		1543	if (cpu_flags_all_zero (&x))
		1544	{
		1545	/* This instruction is available on all archs. */
		1546	match \|= CPU_FLAGS_32BIT_MATCH;
		1547	}
		1548	else
		1549	{
		1550	/* This instruction is available only on some archs. */
		1551	i386_cpu_flags cpu = cpu_arch_flags;
		1552
		1553	cpu.bitfield.cpu64 = 0;
		1554	cpu.bitfield.cpuno64 = 0;
		1555	cpu = cpu_flags_and (x, cpu);
		1556	if (!cpu_flags_all_zero (&cpu))
		1557	{
		1558	if (x.bitfield.cpuavx)
		1559	{
		1560	/* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
		1561	if (cpu.bitfield.cpuavx)
		1562	{
		1563	/* Check SSE2AVX. */
		1564	if (!t->opcode_modifier.sse2avx\|\| sse2avx)
		1565	{
		1566	match \|= (CPU_FLAGS_ARCH_MATCH
		1567	\| CPU_FLAGS_AVX_MATCH);
		1568	/* Check AES. */
		1569	if (!x.bitfield.cpuaes \|\| cpu.bitfield.cpuaes)
		1570	match \|= CPU_FLAGS_AES_MATCH;
		1571	/* Check PCLMUL. */
		1572	if (!x.bitfield.cpupclmul
		1573	\|\| cpu.bitfield.cpupclmul)
		1574	match \|= CPU_FLAGS_PCLMUL_MATCH;
		1575	}
		1576	}
		1577	else
		1578	match \|= CPU_FLAGS_ARCH_MATCH;
		1579	}
		1580	else
		1581	match \|= CPU_FLAGS_32BIT_MATCH;
		1582	}
		1583	}
		1584	return match;
		1585	}
		1586
		1587	static INLINE i386_operand_type
		1588	operand_type_and (i386_operand_type x, i386_operand_type y)
		1589	{
		1590	switch (ARRAY_SIZE (x.array))
		1591	{
		1592	case 3:
		1593	x.array [2] &= y.array [2];
		1594	case 2:
		1595	x.array [1] &= y.array [1];
		1596	case 1:
		1597	x.array [0] &= y.array [0];
		1598	break;
		1599	default:
		1600	abort ();
		1601	}
		1602	return x;
		1603	}
		1604
		1605	static INLINE i386_operand_type
		1606	operand_type_or (i386_operand_type x, i386_operand_type y)
		1607	{
		1608	switch (ARRAY_SIZE (x.array))
		1609	{
		1610	case 3:
		1611	x.array [2] \|= y.array [2];
		1612	case 2:
		1613	x.array [1] \|= y.array [1];
		1614	case 1:
		1615	x.array [0] \|= y.array [0];
		1616	break;
		1617	default:
		1618	abort ();
		1619	}
		1620	return x;
		1621	}
		1622
		1623	static INLINE i386_operand_type
		1624	operand_type_xor (i386_operand_type x, i386_operand_type y)
		1625	{
		1626	switch (ARRAY_SIZE (x.array))
		1627	{
		1628	case 3:
		1629	x.array [2] ^= y.array [2];
		1630	case 2:
		1631	x.array [1] ^= y.array [1];
		1632	case 1:
		1633	x.array [0] ^= y.array [0];
		1634	break;
		1635	default:
		1636	abort ();
		1637	}
		1638	return x;
		1639	}
		1640
		1641	static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
		1642	static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
		1643	static const i386_operand_type control = OPERAND_TYPE_CONTROL;
		1644	static const i386_operand_type inoutportreg
		1645	= OPERAND_TYPE_INOUTPORTREG;
		1646	static const i386_operand_type reg16_inoutportreg
		1647	= OPERAND_TYPE_REG16_INOUTPORTREG;
		1648	static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
		1649	static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
		1650	static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
		1651	static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
		1652	static const i386_operand_type anydisp
		1653	= OPERAND_TYPE_ANYDISP;
		1654	static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
		1655	static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
		1656	static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
		1657	static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
		1658	static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
		1659	static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
		1660	static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
		1661	static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
		1662	static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
		1663	static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
		1664	static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
		1665	static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
		1666	static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
		1667	static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
		1668	static const i386_operand_type regbnd = OPERAND_TYPE_REGBND;
		1669	static const i386_operand_type vec_disp8 = OPERAND_TYPE_VEC_DISP8;
		1670
		1671	enum operand_type
		1672	{
		1673	reg,
		1674	imm,
		1675	disp,
		1676	anymem
		1677	};
		1678
		1679	static INLINE int
		1680	operand_type_check (i386_operand_type t, enum operand_type c)
		1681	{
		1682	switch (c)
		1683	{
		1684	case reg:
		1685	return (t.bitfield.reg8
		1686	\|\| t.bitfield.reg16
		1687	\|\| t.bitfield.reg32
		1688	\|\| t.bitfield.reg64);
		1689
		1690	case imm:
		1691	return (t.bitfield.imm8
		1692	\|\| t.bitfield.imm8s
		1693	\|\| t.bitfield.imm16
		1694	\|\| t.bitfield.imm32
		1695	\|\| t.bitfield.imm32s
		1696	\|\| t.bitfield.imm64);
		1697
		1698	case disp:
		1699	return (t.bitfield.disp8
		1700	\|\| t.bitfield.disp16
		1701	\|\| t.bitfield.disp32
		1702	\|\| t.bitfield.disp32s
		1703	\|\| t.bitfield.disp64);
		1704
		1705	case anymem:
		1706	return (t.bitfield.disp8
		1707	\|\| t.bitfield.disp16
		1708	\|\| t.bitfield.disp32
		1709	\|\| t.bitfield.disp32s
		1710	\|\| t.bitfield.disp64
		1711	\|\| t.bitfield.baseindex);
		1712
		1713	default:
		1714	abort ();
		1715	}
		1716
		1717	return 0;
		1718	}
		1719
		1720	/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
		1721	operand J for instruction template T. */
		1722
		1723	static INLINE int
		1724	match_reg_size (const insn_template *t, unsigned int j)
		1725	{
		1726	return !((i.types[j].bitfield.byte
		1727	&& !t->operand_types[j].bitfield.byte)
		1728	\|\| (i.types[j].bitfield.word
		1729	&& !t->operand_types[j].bitfield.word)
		1730	\|\| (i.types[j].bitfield.dword
		1731	&& !t->operand_types[j].bitfield.dword)
		1732	\|\| (i.types[j].bitfield.qword
		1733	&& !t->operand_types[j].bitfield.qword));
		1734	}
		1735
		1736	/* Return 1 if there is no conflict in any size on operand J for
		1737	instruction template T. */
		1738
		1739	static INLINE int
		1740	match_mem_size (const insn_template *t, unsigned int j)
		1741	{
		1742	return (match_reg_size (t, j)
		1743	&& !((i.types[j].bitfield.unspecified
		1744	&& !t->operand_types[j].bitfield.unspecified)
		1745	\|\| (i.types[j].bitfield.fword
		1746	&& !t->operand_types[j].bitfield.fword)
		1747	\|\| (i.types[j].bitfield.tbyte
		1748	&& !t->operand_types[j].bitfield.tbyte)
		1749	\|\| (i.types[j].bitfield.xmmword
		1750	&& !t->operand_types[j].bitfield.xmmword)
		1751	\|\| (i.types[j].bitfield.ymmword
		1752	&& !t->operand_types[j].bitfield.ymmword)
		1753	\|\| (i.types[j].bitfield.zmmword
		1754	&& !t->operand_types[j].bitfield.zmmword)));
		1755	}
		1756
		1757	/* Return 1 if there is no size conflict on any operands for
		1758	instruction template T. */
		1759
		1760	static INLINE int
		1761	operand_size_match (const insn_template *t)
		1762	{
		1763	unsigned int j;
		1764	int match = 1;
		1765
		1766	/* Don't check jump instructions. */
		1767	if (t->opcode_modifier.jump
		1768	\|\| t->opcode_modifier.jumpbyte
		1769	\|\| t->opcode_modifier.jumpdword
		1770	\|\| t->opcode_modifier.jumpintersegment)
		1771	return match;
		1772
		1773	/* Check memory and accumulator operand size. */
		1774	for (j = 0; j < i.operands; j++)
		1775	{
		1776	if (t->operand_types[j].bitfield.anysize)
		1777	continue;
		1778
		1779	if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
		1780	{
		1781	match = 0;
		1782	break;
		1783	}
		1784
		1785	if (i.types[j].bitfield.mem && !match_mem_size (t, j))
		1786	{
		1787	match = 0;
		1788	break;
		1789	}
		1790	}
		1791
		1792	if (match)
		1793	return match;
		1794	else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
		1795	{
		1796	mismatch:
		1797	i.error = operand_size_mismatch;
		1798	return 0;
		1799	}
		1800
		1801	/* Check reverse. */
		1802	gas_assert (i.operands == 2);
		1803
		1804	match = 1;
		1805	for (j = 0; j < 2; j++)
		1806	{
		1807	if (t->operand_types[j].bitfield.acc
		1808	&& !match_reg_size (t, j ? 0 : 1))
		1809	goto mismatch;
		1810
		1811	if (i.types[j].bitfield.mem
		1812	&& !match_mem_size (t, j ? 0 : 1))
		1813	goto mismatch;
		1814	}
		1815
		1816	return match;
		1817	}
		1818
		1819	static INLINE int
		1820	operand_type_match (i386_operand_type overlap,
		1821	i386_operand_type given)
		1822	{
		1823	i386_operand_type temp = overlap;
		1824
		1825	temp.bitfield.jumpabsolute = 0;
		1826	temp.bitfield.unspecified = 0;
		1827	temp.bitfield.byte = 0;
		1828	temp.bitfield.word = 0;
		1829	temp.bitfield.dword = 0;
		1830	temp.bitfield.fword = 0;
		1831	temp.bitfield.qword = 0;
		1832	temp.bitfield.tbyte = 0;
		1833	temp.bitfield.xmmword = 0;
		1834	temp.bitfield.ymmword = 0;
		1835	temp.bitfield.zmmword = 0;
		1836	if (operand_type_all_zero (&temp))
		1837	goto mismatch;
		1838
		1839	if (given.bitfield.baseindex == overlap.bitfield.baseindex
		1840	&& given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
		1841	return 1;
		1842
		1843	mismatch:
		1844	i.error = operand_type_mismatch;
		1845	return 0;
		1846	}
		1847
		1848	/* If given types g0 and g1 are registers they must be of the same type
		1849	unless the expected operand type register overlap is null.
		1850	Note that Acc in a template matches every size of reg. */
		1851
		1852	static INLINE int
		1853	operand_type_register_match (i386_operand_type m0,
		1854	i386_operand_type g0,
		1855	i386_operand_type t0,
		1856	i386_operand_type m1,
		1857	i386_operand_type g1,
		1858	i386_operand_type t1)
		1859	{
		1860	if (!operand_type_check (g0, reg))
		1861	return 1;
		1862
		1863	if (!operand_type_check (g1, reg))
		1864	return 1;
		1865
		1866	if (g0.bitfield.reg8 == g1.bitfield.reg8
		1867	&& g0.bitfield.reg16 == g1.bitfield.reg16
		1868	&& g0.bitfield.reg32 == g1.bitfield.reg32
		1869	&& g0.bitfield.reg64 == g1.bitfield.reg64)
		1870	return 1;
		1871
		1872	if (m0.bitfield.acc)
		1873	{
		1874	t0.bitfield.reg8 = 1;
		1875	t0.bitfield.reg16 = 1;
		1876	t0.bitfield.reg32 = 1;
		1877	t0.bitfield.reg64 = 1;
		1878	}
		1879
		1880	if (m1.bitfield.acc)
		1881	{
		1882	t1.bitfield.reg8 = 1;
		1883	t1.bitfield.reg16 = 1;
		1884	t1.bitfield.reg32 = 1;
		1885	t1.bitfield.reg64 = 1;
		1886	}
		1887
		1888	if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
		1889	&& !(t0.bitfield.reg16 & t1.bitfield.reg16)
		1890	&& !(t0.bitfield.reg32 & t1.bitfield.reg32)
		1891	&& !(t0.bitfield.reg64 & t1.bitfield.reg64))
		1892	return 1;
		1893
		1894	i.error = register_type_mismatch;
		1895
		1896	return 0;
		1897	}
		1898
		1899	static INLINE unsigned int
		1900	register_number (const reg_entry *r)
		1901	{
		1902	unsigned int nr = r->reg_num;
		1903
		1904	if (r->reg_flags & RegRex)
		1905	nr += 8;
		1906
		1907	return nr;
		1908	}
		1909
		1910	static INLINE unsigned int
		1911	mode_from_disp_size (i386_operand_type t)
		1912	{
		1913	if (t.bitfield.disp8 \|\| t.bitfield.vec_disp8)
		1914	return 1;
		1915	else if (t.bitfield.disp16
		1916	\|\| t.bitfield.disp32
		1917	\|\| t.bitfield.disp32s)
		1918	return 2;
		1919	else
		1920	return 0;
		1921	}
		1922
		1923	static INLINE int
		1924	fits_in_signed_byte (offsetT num)
		1925	{
		1926	return (num >= -128) && (num <= 127);
		1927	}
		1928
		1929	static INLINE int
		1930	fits_in_unsigned_byte (offsetT num)
		1931	{
		1932	return (num & 0xff) == num;
		1933	}
		1934
		1935	static INLINE int
		1936	fits_in_unsigned_word (offsetT num)
		1937	{
		1938	return (num & 0xffff) == num;
		1939	}
		1940
		1941	static INLINE int
		1942	fits_in_signed_word (offsetT num)
		1943	{
		1944	return (-32768 <= num) && (num <= 32767);
		1945	}
		1946
		1947	static INLINE int
		1948	fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
		1949	{
		1950	#ifndef BFD64
		1951	return 1;
		1952	#else
		1953	return (!(((offsetT) -1 << 31) & num)
		1954	\|\| (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
		1955	#endif
		1956	} /* fits_in_signed_long() */
		1957
		1958	static INLINE int
		1959	fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
		1960	{
		1961	#ifndef BFD64
		1962	return 1;
		1963	#else
		1964	return (num & (((offsetT) 2 << 31) - 1)) == num;
		1965	#endif
		1966	} /* fits_in_unsigned_long() */
		1967
		1968	static INLINE int
		1969	fits_in_vec_disp8 (offsetT num)
		1970	{
		1971	int shift = i.memshift;
		1972	unsigned int mask;
		1973
		1974	if (shift == -1)
		1975	abort ();
		1976
		1977	mask = (1 << shift) - 1;
		1978
		1979	/* Return 0 if NUM isn't properly aligned. */
		1980	if ((num & mask))
		1981	return 0;
		1982
		1983	/* Check if NUM will fit in 8bit after shift. */
		1984	return fits_in_signed_byte (num >> shift);
		1985	}
		1986
		1987	static INLINE int
		1988	fits_in_imm4 (offsetT num)
		1989	{
		1990	return (num & 0xf) == num;
		1991	}
		1992
		1993	static i386_operand_type
		1994	smallest_imm_type (offsetT num)
		1995	{
		1996	i386_operand_type t;
		1997
		1998	operand_type_set (&t, 0);
		1999	t.bitfield.imm64 = 1;
		2000
		2001	if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
		2002	{
		2003	/* This code is disabled on the 486 because all the Imm1 forms
		2004	in the opcode table are slower on the i486. They're the
		2005	versions with the implicitly specified single-position
		2006	displacement, which has another syntax if you really want to
		2007	use that form. */
		2008	t.bitfield.imm1 = 1;
		2009	t.bitfield.imm8 = 1;
		2010	t.bitfield.imm8s = 1;
		2011	t.bitfield.imm16 = 1;
		2012	t.bitfield.imm32 = 1;
		2013	t.bitfield.imm32s = 1;
		2014	}
		2015	else if (fits_in_signed_byte (num))
		2016	{
		2017	t.bitfield.imm8 = 1;
		2018	t.bitfield.imm8s = 1;
		2019	t.bitfield.imm16 = 1;
		2020	t.bitfield.imm32 = 1;
		2021	t.bitfield.imm32s = 1;
		2022	}
		2023	else if (fits_in_unsigned_byte (num))
		2024	{
		2025	t.bitfield.imm8 = 1;
		2026	t.bitfield.imm16 = 1;
		2027	t.bitfield.imm32 = 1;
		2028	t.bitfield.imm32s = 1;
		2029	}
		2030	else if (fits_in_signed_word (num) \|\| fits_in_unsigned_word (num))
		2031	{
		2032	t.bitfield.imm16 = 1;
		2033	t.bitfield.imm32 = 1;
		2034	t.bitfield.imm32s = 1;
		2035	}
		2036	else if (fits_in_signed_long (num))
		2037	{
		2038	t.bitfield.imm32 = 1;
		2039	t.bitfield.imm32s = 1;
		2040	}
		2041	else if (fits_in_unsigned_long (num))
		2042	t.bitfield.imm32 = 1;
		2043
		2044	return t;
		2045	}
		2046
		2047	static offsetT
		2048	offset_in_range (offsetT val, int size)
		2049	{
		2050	addressT mask;
		2051
		2052	switch (size)
		2053	{
		2054	case 1: mask = ((addressT) 1 << 8) - 1; break;
		2055	case 2: mask = ((addressT) 1 << 16) - 1; break;
		2056	case 4: mask = ((addressT) 2 << 31) - 1; break;
		2057	#ifdef BFD64
		2058	case 8: mask = ((addressT) 2 << 63) - 1; break;
		2059	#endif
		2060	default: abort ();
		2061	}
		2062
		2063	#ifdef BFD64
		2064	/* If BFD64, sign extend val for 32bit address mode. */
		2065	if (flag_code != CODE_64BIT
		2066	\|\| i.prefix[ADDR_PREFIX])
		2067	if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
		2068	val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
		2069	#endif
		2070
		2071	if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
		2072	{
		2073	char buf1[40], buf2[40];
		2074
		2075	sprint_value (buf1, val);
		2076	sprint_value (buf2, val & mask);
		2077	as_warn (_("%s shortened to %s"), buf1, buf2);
		2078	}
		2079	return val & mask;
		2080	}
		2081
		2082	enum PREFIX_GROUP
		2083	{
		2084	PREFIX_EXIST = 0,
		2085	PREFIX_LOCK,
		2086	PREFIX_REP,
		2087	PREFIX_OTHER
		2088	};
		2089
		2090	/* Returns
		2091	a. PREFIX_EXIST if attempting to add a prefix where one from the
		2092	same class already exists.
		2093	b. PREFIX_LOCK if lock prefix is added.
		2094	c. PREFIX_REP if rep/repne prefix is added.
		2095	d. PREFIX_OTHER if other prefix is added.
		2096	*/
		2097
		2098	static enum PREFIX_GROUP
		2099	add_prefix (unsigned int prefix)
		2100	{
		2101	enum PREFIX_GROUP ret = PREFIX_OTHER;
		2102	unsigned int q;
		2103
		2104	if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
		2105	&& flag_code == CODE_64BIT)
		2106	{
		2107	if ((i.prefix[REX_PREFIX] & prefix & REX_W)
		2108	\|\| ((i.prefix[REX_PREFIX] & (REX_R \| REX_X \| REX_B))
		2109	&& (prefix & (REX_R \| REX_X \| REX_B))))
		2110	ret = PREFIX_EXIST;
		2111	q = REX_PREFIX;
		2112	}
		2113	else
		2114	{
		2115	switch (prefix)
		2116	{
		2117	default:
		2118	abort ();
		2119
		2120	case CS_PREFIX_OPCODE:
		2121	case DS_PREFIX_OPCODE:
		2122	case ES_PREFIX_OPCODE:
		2123	case FS_PREFIX_OPCODE:
		2124	case GS_PREFIX_OPCODE:
		2125	case SS_PREFIX_OPCODE:
		2126	q = SEG_PREFIX;
		2127	break;
		2128
		2129	case REPNE_PREFIX_OPCODE:
		2130	case REPE_PREFIX_OPCODE:
		2131	q = REP_PREFIX;
		2132	ret = PREFIX_REP;
		2133	break;
		2134
		2135	case LOCK_PREFIX_OPCODE:
		2136	q = LOCK_PREFIX;
		2137	ret = PREFIX_LOCK;
		2138	break;
		2139
		2140	case FWAIT_OPCODE:
		2141	q = WAIT_PREFIX;
		2142	break;
		2143
		2144	case ADDR_PREFIX_OPCODE:
		2145	q = ADDR_PREFIX;
		2146	break;
		2147
		2148	case DATA_PREFIX_OPCODE:
		2149	q = DATA_PREFIX;
		2150	break;
		2151	}
		2152	if (i.prefix[q] != 0)
		2153	ret = PREFIX_EXIST;
		2154	}
		2155
		2156	if (ret)
		2157	{
		2158	if (!i.prefix[q])
		2159	++i.prefixes;
		2160	i.prefix[q] \|= prefix;
		2161	}
		2162	else
		2163	as_bad (_("same type of prefix used twice"));
		2164
		2165	return ret;
		2166	}
		2167
		2168	static void
		2169	update_code_flag (int value, int check)
		2170	{
		2171	PRINTF_LIKE ((*as_error));
		2172
		2173	flag_code = (enum flag_code) value;
		2174	if (flag_code == CODE_64BIT)
		2175	{
		2176	cpu_arch_flags.bitfield.cpu64 = 1;
		2177	cpu_arch_flags.bitfield.cpuno64 = 0;
		2178	}
		2179	else
		2180	{
		2181	cpu_arch_flags.bitfield.cpu64 = 0;
		2182	cpu_arch_flags.bitfield.cpuno64 = 1;
		2183	}
		2184	if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
		2185	{
		2186	if (check)
		2187	as_error = as_fatal;
		2188	else
		2189	as_error = as_bad;
		2190	(*as_error) (_("64bit mode not supported on `%s'."),
		2191	cpu_arch_name ? cpu_arch_name : default_arch);
		2192	}
		2193	if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
		2194	{
		2195	if (check)
		2196	as_error = as_fatal;
		2197	else
		2198	as_error = as_bad;
		2199	(*as_error) (_("32bit mode not supported on `%s'."),
		2200	cpu_arch_name ? cpu_arch_name : default_arch);
		2201	}
		2202	stackop_size = '\0';
		2203	}
		2204
		2205	static void
		2206	set_code_flag (int value)
		2207	{
		2208	update_code_flag (value, 0);
		2209	}
		2210
		2211	static void
		2212	set_16bit_gcc_code_flag (int new_code_flag)
		2213	{
		2214	flag_code = (enum flag_code) new_code_flag;
		2215	if (flag_code != CODE_16BIT)
		2216	abort ();
		2217	cpu_arch_flags.bitfield.cpu64 = 0;
		2218	cpu_arch_flags.bitfield.cpuno64 = 1;
		2219	stackop_size = LONG_MNEM_SUFFIX;
		2220	}
		2221
		2222	static void
		2223	set_intel_syntax (int syntax_flag)
		2224	{
		2225	/* Find out if register prefixing is specified. */
		2226	int ask_naked_reg = 0;
		2227
		2228	SKIP_WHITESPACE ();
		2229	if (!is_end_of_line[(unsigned char) *input_line_pointer])
		2230	{
		2231	char *string = input_line_pointer;
		2232	int e = get_symbol_end ();
		2233
		2234	if (strcmp (string, "prefix") == 0)
		2235	ask_naked_reg = 1;
		2236	else if (strcmp (string, "noprefix") == 0)
		2237	ask_naked_reg = -1;
		2238	else
		2239	as_bad (_("bad argument to syntax directive."));
		2240	*input_line_pointer = e;
		2241	}
		2242	demand_empty_rest_of_line ();
		2243
		2244	intel_syntax = syntax_flag;
		2245
		2246	if (ask_naked_reg == 0)
		2247	allow_naked_reg = (intel_syntax
		2248	&& (bfd_get_symbol_leading_char (stdoutput) != '\0'));
		2249	else
		2250	allow_naked_reg = (ask_naked_reg < 0);
		2251
		2252	expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
		2253
		2254	identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
		2255	identifier_chars['$'] = intel_syntax ? '$' : 0;
		2256	register_prefix = allow_naked_reg ? "" : "%";
		2257	}
		2258
		2259	static void
		2260	set_intel_mnemonic (int mnemonic_flag)
		2261	{
		2262	intel_mnemonic = mnemonic_flag;
		2263	}
		2264
		2265	static void
		2266	set_allow_index_reg (int flag)
		2267	{
		2268	allow_index_reg = flag;
		2269	}
		2270
		2271	static void
		2272	set_check (int what)
		2273	{
		2274	enum check_kind *kind;
		2275	const char *str;
		2276
		2277	if (what)
		2278	{
		2279	kind = &operand_check;
		2280	str = "operand";
		2281	}
		2282	else
		2283	{
		2284	kind = &sse_check;
		2285	str = "sse";
		2286	}
		2287
		2288	SKIP_WHITESPACE ();
		2289
		2290	if (!is_end_of_line[(unsigned char) *input_line_pointer])
		2291	{
		2292	char *string = input_line_pointer;
		2293	int e = get_symbol_end ();
		2294
		2295	if (strcmp (string, "none") == 0)
		2296	*kind = check_none;
		2297	else if (strcmp (string, "warning") == 0)
		2298	*kind = check_warning;
		2299	else if (strcmp (string, "error") == 0)
		2300	*kind = check_error;
		2301	else
		2302	as_bad (_("bad argument to %s_check directive."), str);
		2303	*input_line_pointer = e;
		2304	}
		2305	else
		2306	as_bad (_("missing argument for %s_check directive"), str);
		2307
		2308	demand_empty_rest_of_line ();
		2309	}
		2310
		2311	static void
		2312	check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
		2313	i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
		2314	{
		2315	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		2316	static const char *arch;
		2317
		2318	/* Intel LIOM is only supported on ELF. */
		2319	if (!IS_ELF)
		2320	return;
		2321
		2322	if (!arch)
		2323	{
		2324	/* Use cpu_arch_name if it is set in md_parse_option. Otherwise
		2325	use default_arch. */
		2326	arch = cpu_arch_name;
		2327	if (!arch)
		2328	arch = default_arch;
		2329	}
		2330
		2331	/* If we are targeting Intel L1OM, we must enable it. */
		2332	if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
		2333	\|\| new_flag.bitfield.cpul1om)
		2334	return;
		2335
		2336	/* If we are targeting Intel K1OM, we must enable it. */
		2337	if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
		2338	\|\| new_flag.bitfield.cpuk1om)
		2339	return;
		2340
		2341	as_bad (_("`%s' is not supported on `%s'"), name, arch);
		2342	#endif
		2343	}
		2344
		2345	static void
		2346	set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
		2347	{
		2348	SKIP_WHITESPACE ();
		2349
		2350	if (!is_end_of_line[(unsigned char) *input_line_pointer])
		2351	{
		2352	char *string = input_line_pointer;
		2353	int e = get_symbol_end ();
		2354	unsigned int j;
		2355	i386_cpu_flags flags;
		2356
		2357	for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
		2358	{
		2359	if (strcmp (string, cpu_arch[j].name) == 0)
		2360	{
		2361	check_cpu_arch_compatible (string, cpu_arch[j].flags);
		2362
		2363	if (*string != '.')
		2364	{
		2365	cpu_arch_name = cpu_arch[j].name;
		2366	cpu_sub_arch_name = NULL;
		2367	cpu_arch_flags = cpu_arch[j].flags;
		2368	if (flag_code == CODE_64BIT)
		2369	{
		2370	cpu_arch_flags.bitfield.cpu64 = 1;
		2371	cpu_arch_flags.bitfield.cpuno64 = 0;
		2372	}
		2373	else
		2374	{
		2375	cpu_arch_flags.bitfield.cpu64 = 0;
		2376	cpu_arch_flags.bitfield.cpuno64 = 1;
		2377	}
		2378	cpu_arch_isa = cpu_arch[j].type;
		2379	cpu_arch_isa_flags = cpu_arch[j].flags;
		2380	if (!cpu_arch_tune_set)
		2381	{
		2382	cpu_arch_tune = cpu_arch_isa;
		2383	cpu_arch_tune_flags = cpu_arch_isa_flags;
		2384	}
		2385	break;
		2386	}
		2387
		2388	if (!cpu_arch[j].negated)
		2389	flags = cpu_flags_or (cpu_arch_flags,
		2390	cpu_arch[j].flags);
		2391	else
		2392	flags = cpu_flags_and_not (cpu_arch_flags,
		2393	cpu_arch[j].flags);
		2394	if (!cpu_flags_equal (&flags, &cpu_arch_flags))
		2395	{
		2396	if (cpu_sub_arch_name)
		2397	{
		2398	char *name = cpu_sub_arch_name;
		2399	cpu_sub_arch_name = concat (name,
		2400	cpu_arch[j].name,
		2401	(const char *) NULL);
		2402	free (name);
		2403	}
		2404	else
		2405	cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
		2406	cpu_arch_flags = flags;
		2407	cpu_arch_isa_flags = flags;
		2408	}
		2409	*input_line_pointer = e;
		2410	demand_empty_rest_of_line ();
		2411	return;
		2412	}
		2413	}
		2414	if (j >= ARRAY_SIZE (cpu_arch))
		2415	as_bad (_("no such architecture: `%s'"), string);
		2416
		2417	*input_line_pointer = e;
		2418	}
		2419	else
		2420	as_bad (_("missing cpu architecture"));
		2421
		2422	no_cond_jump_promotion = 0;
		2423	if (*input_line_pointer == ','
		2424	&& !is_end_of_line[(unsigned char) input_line_pointer[1]])
		2425	{
		2426	char *string = ++input_line_pointer;
		2427	int e = get_symbol_end ();
		2428
		2429	if (strcmp (string, "nojumps") == 0)
		2430	no_cond_jump_promotion = 1;
		2431	else if (strcmp (string, "jumps") == 0)
		2432	;
		2433	else
		2434	as_bad (_("no such architecture modifier: `%s'"), string);
		2435
		2436	*input_line_pointer = e;
		2437	}
		2438
		2439	demand_empty_rest_of_line ();
		2440	}
		2441
		2442	enum bfd_architecture
		2443	i386_arch (void)
		2444	{
		2445	if (cpu_arch_isa == PROCESSOR_L1OM)
		2446	{
		2447	if (OUTPUT_FLAVOR != bfd_target_elf_flavour
		2448	\|\| flag_code != CODE_64BIT)
		2449	as_fatal (_("Intel L1OM is 64bit ELF only"));
		2450	return bfd_arch_l1om;
		2451	}
		2452	else if (cpu_arch_isa == PROCESSOR_K1OM)
		2453	{
		2454	if (OUTPUT_FLAVOR != bfd_target_elf_flavour
		2455	\|\| flag_code != CODE_64BIT)
		2456	as_fatal (_("Intel K1OM is 64bit ELF only"));
		2457	return bfd_arch_k1om;
		2458	}
		2459	else
		2460	return bfd_arch_i386;
		2461	}
		2462
		2463	unsigned long
		2464	i386_mach (void)
		2465	{
		2466	if (!strncmp (default_arch, "x86_64", 6))
		2467	{
		2468	if (cpu_arch_isa == PROCESSOR_L1OM)
		2469	{
		2470	if (OUTPUT_FLAVOR != bfd_target_elf_flavour
		2471	\|\| default_arch[6] != '\0')
		2472	as_fatal (_("Intel L1OM is 64bit ELF only"));
		2473	return bfd_mach_l1om;
		2474	}
		2475	else if (cpu_arch_isa == PROCESSOR_K1OM)
		2476	{
		2477	if (OUTPUT_FLAVOR != bfd_target_elf_flavour
		2478	\|\| default_arch[6] != '\0')
		2479	as_fatal (_("Intel K1OM is 64bit ELF only"));
		2480	return bfd_mach_k1om;
		2481	}
		2482	else if (default_arch[6] == '\0')
		2483	return bfd_mach_x86_64;
		2484	else
		2485	return bfd_mach_x64_32;
		2486	}
		2487	else if (!strcmp (default_arch, "i386"))
		2488	return bfd_mach_i386_i386;
		2489	else
		2490	as_fatal (_("unknown architecture"));
		2491	}
		2492
		2493	void
		2494	md_begin (void)
		2495	{
		2496	const char *hash_err;
		2497
		2498	/* Initialize op_hash hash table. */
		2499	op_hash = hash_new ();
		2500
		2501	{
		2502	const insn_template *optab;
		2503	templates *core_optab;
		2504
		2505	/* Setup for loop. */
		2506	optab = i386_optab;
		2507	core_optab = (templates *) xmalloc (sizeof (templates));
		2508	core_optab->start = optab;
		2509
		2510	while (1)
		2511	{
		2512	++optab;
		2513	if (optab->name == NULL
		2514	\|\| strcmp (optab->name, (optab - 1)->name) != 0)
		2515	{
		2516	/* different name --> ship out current template list;
		2517	add to hash table; & begin anew. */
		2518	core_optab->end = optab;
		2519	hash_err = hash_insert (op_hash,
		2520	(optab - 1)->name,
		2521	(void *) core_optab);
		2522	if (hash_err)
		2523	{
		2524	as_fatal (_("can't hash %s: %s"),
		2525	(optab - 1)->name,
		2526	hash_err);
		2527	}
		2528	if (optab->name == NULL)
		2529	break;
		2530	core_optab = (templates *) xmalloc (sizeof (templates));
		2531	core_optab->start = optab;
		2532	}
		2533	}
		2534	}
		2535
		2536	/* Initialize reg_hash hash table. */
		2537	reg_hash = hash_new ();
		2538	{
		2539	const reg_entry *regtab;
		2540	unsigned int regtab_size = i386_regtab_size;
		2541
		2542	for (regtab = i386_regtab; regtab_size--; regtab++)
		2543	{
		2544	hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
		2545	if (hash_err)
		2546	as_fatal (_("can't hash %s: %s"),
		2547	regtab->reg_name,
		2548	hash_err);
		2549	}
		2550	}
		2551
		2552	/* Fill in lexical tables: mnemonic_chars, operand_chars. */
		2553	{
		2554	int c;
		2555	char *p;
		2556
		2557	for (c = 0; c < 256; c++)
		2558	{
		2559	if (ISDIGIT (c))
		2560	{
		2561	digit_chars[c] = c;
		2562	mnemonic_chars[c] = c;
		2563	register_chars[c] = c;
		2564	operand_chars[c] = c;
		2565	}
		2566	else if (ISLOWER (c))
		2567	{
		2568	mnemonic_chars[c] = c;
		2569	register_chars[c] = c;
		2570	operand_chars[c] = c;
		2571	}
		2572	else if (ISUPPER (c))
		2573	{
		2574	mnemonic_chars[c] = TOLOWER (c);
		2575	register_chars[c] = mnemonic_chars[c];
		2576	operand_chars[c] = c;
		2577	}
		2578	else if (c == '{' \|\| c == '}')
		2579	operand_chars[c] = c;
		2580
		2581	if (ISALPHA (c) \|\| ISDIGIT (c))
		2582	identifier_chars[c] = c;
		2583	else if (c >= 128)
		2584	{
		2585	identifier_chars[c] = c;
		2586	operand_chars[c] = c;
		2587	}
		2588	}
		2589
		2590	#ifdef LEX_AT
		2591	identifier_chars['@'] = '@';
		2592	#endif
		2593	#ifdef LEX_QM
		2594	identifier_chars['?'] = '?';
		2595	operand_chars['?'] = '?';
		2596	#endif
		2597	digit_chars['-'] = '-';
		2598	mnemonic_chars['_'] = '_';
		2599	mnemonic_chars['-'] = '-';
		2600	mnemonic_chars['.'] = '.';
		2601	identifier_chars['_'] = '_';
		2602	identifier_chars['.'] = '.';
		2603
		2604	for (p = operand_special_chars; *p != '\0'; p++)
		2605	operand_chars[(unsigned char) p] = p;
		2606	}
		2607
		2608	if (flag_code == CODE_64BIT)
		2609	{
		2610	#if defined (OBJ_COFF) && defined (TE_PE)
		2611	x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
		2612	? 32 : 16);
		2613	#else
		2614	x86_dwarf2_return_column = 16;
		2615	#endif
		2616	x86_cie_data_alignment = -8;
		2617	}
		2618	else
		2619	{
		2620	x86_dwarf2_return_column = 8;
		2621	x86_cie_data_alignment = -4;
		2622	}
		2623	}
		2624
		2625	void
		2626	i386_print_statistics (FILE *file)
		2627	{
		2628	hash_print_statistics (file, "i386 opcode", op_hash);
		2629	hash_print_statistics (file, "i386 register", reg_hash);
		2630	}
		2631
		2632	#ifdef DEBUG386
		2633
		2634	/* Debugging routines for md_assemble. */
		2635	static void pte (insn_template *);
		2636	static void pt (i386_operand_type);
		2637	static void pe (expressionS *);
		2638	static void ps (symbolS *);
		2639
		2640	static void
		2641	pi (char line, i386_insn x)
		2642	{
		2643	unsigned int j;
		2644
		2645	fprintf (stdout, "%s: template ", line);
		2646	pte (&x->tm);
		2647	fprintf (stdout, " address: base %s index %s scale %x\n",
		2648	x->base_reg ? x->base_reg->reg_name : "none",
		2649	x->index_reg ? x->index_reg->reg_name : "none",
		2650	x->log2_scale_factor);
		2651	fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
		2652	x->rm.mode, x->rm.reg, x->rm.regmem);
		2653	fprintf (stdout, " sib: base %x index %x scale %x\n",
		2654	x->sib.base, x->sib.index, x->sib.scale);
		2655	fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
		2656	(x->rex & REX_W) != 0,
		2657	(x->rex & REX_R) != 0,
		2658	(x->rex & REX_X) != 0,
		2659	(x->rex & REX_B) != 0);
		2660	for (j = 0; j < x->operands; j++)
		2661	{
		2662	fprintf (stdout, " #%d: ", j + 1);
		2663	pt (x->types[j]);
		2664	fprintf (stdout, "\n");
		2665	if (x->types[j].bitfield.reg8
		2666	\|\| x->types[j].bitfield.reg16
		2667	\|\| x->types[j].bitfield.reg32
		2668	\|\| x->types[j].bitfield.reg64
		2669	\|\| x->types[j].bitfield.regmmx
		2670	\|\| x->types[j].bitfield.regxmm
		2671	\|\| x->types[j].bitfield.regymm
		2672	\|\| x->types[j].bitfield.regzmm
		2673	\|\| x->types[j].bitfield.sreg2
		2674	\|\| x->types[j].bitfield.sreg3
		2675	\|\| x->types[j].bitfield.control
		2676	\|\| x->types[j].bitfield.debug
		2677	\|\| x->types[j].bitfield.test)
		2678	fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
		2679	if (operand_type_check (x->types[j], imm))
		2680	pe (x->op[j].imms);
		2681	if (operand_type_check (x->types[j], disp))
		2682	pe (x->op[j].disps);
		2683	}
		2684	}
		2685
		2686	static void
		2687	pte (insn_template *t)
		2688	{
		2689	unsigned int j;
		2690	fprintf (stdout, " %d operands ", t->operands);
		2691	fprintf (stdout, "opcode %x ", t->base_opcode);
		2692	if (t->extension_opcode != None)
		2693	fprintf (stdout, "ext %x ", t->extension_opcode);
		2694	if (t->opcode_modifier.d)
		2695	fprintf (stdout, "D");
		2696	if (t->opcode_modifier.w)
		2697	fprintf (stdout, "W");
		2698	fprintf (stdout, "\n");
		2699	for (j = 0; j < t->operands; j++)
		2700	{
		2701	fprintf (stdout, " #%d type ", j + 1);
		2702	pt (t->operand_types[j]);
		2703	fprintf (stdout, "\n");
		2704	}
		2705	}
		2706
		2707	static void
		2708	pe (expressionS *e)
		2709	{
		2710	fprintf (stdout, " operation %d\n", e->X_op);
		2711	fprintf (stdout, " add_number %ld (%lx)\n",
		2712	(long) e->X_add_number, (long) e->X_add_number);
		2713	if (e->X_add_symbol)
		2714	{
		2715	fprintf (stdout, " add_symbol ");
		2716	ps (e->X_add_symbol);
		2717	fprintf (stdout, "\n");
		2718	}
		2719	if (e->X_op_symbol)
		2720	{
		2721	fprintf (stdout, " op_symbol ");
		2722	ps (e->X_op_symbol);
		2723	fprintf (stdout, "\n");
		2724	}
		2725	}
		2726
		2727	static void
		2728	ps (symbolS *s)
		2729	{
		2730	fprintf (stdout, "%s type %s%s",
		2731	S_GET_NAME (s),
		2732	S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
		2733	segment_name (S_GET_SEGMENT (s)));
		2734	}
		2735
		2736	static struct type_name
		2737	{
		2738	i386_operand_type mask;
		2739	const char *name;
		2740	}
		2741	const type_names[] =
		2742	{
		2743	{ OPERAND_TYPE_REG8, "r8" },
		2744	{ OPERAND_TYPE_REG16, "r16" },
		2745	{ OPERAND_TYPE_REG32, "r32" },
		2746	{ OPERAND_TYPE_REG64, "r64" },
		2747	{ OPERAND_TYPE_IMM8, "i8" },
		2748	{ OPERAND_TYPE_IMM8, "i8s" },
		2749	{ OPERAND_TYPE_IMM16, "i16" },
		2750	{ OPERAND_TYPE_IMM32, "i32" },
		2751	{ OPERAND_TYPE_IMM32S, "i32s" },
		2752	{ OPERAND_TYPE_IMM64, "i64" },
		2753	{ OPERAND_TYPE_IMM1, "i1" },
		2754	{ OPERAND_TYPE_BASEINDEX, "BaseIndex" },
		2755	{ OPERAND_TYPE_DISP8, "d8" },
		2756	{ OPERAND_TYPE_DISP16, "d16" },
		2757	{ OPERAND_TYPE_DISP32, "d32" },
		2758	{ OPERAND_TYPE_DISP32S, "d32s" },
		2759	{ OPERAND_TYPE_DISP64, "d64" },
		2760	{ OPERAND_TYPE_VEC_DISP8, "Vector d8" },
		2761	{ OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
		2762	{ OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
		2763	{ OPERAND_TYPE_CONTROL, "control reg" },
		2764	{ OPERAND_TYPE_TEST, "test reg" },
		2765	{ OPERAND_TYPE_DEBUG, "debug reg" },
		2766	{ OPERAND_TYPE_FLOATREG, "FReg" },
		2767	{ OPERAND_TYPE_FLOATACC, "FAcc" },
		2768	{ OPERAND_TYPE_SREG2, "SReg2" },
		2769	{ OPERAND_TYPE_SREG3, "SReg3" },
		2770	{ OPERAND_TYPE_ACC, "Acc" },
		2771	{ OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
		2772	{ OPERAND_TYPE_REGMMX, "rMMX" },
		2773	{ OPERAND_TYPE_REGXMM, "rXMM" },
		2774	{ OPERAND_TYPE_REGYMM, "rYMM" },
		2775	{ OPERAND_TYPE_REGZMM, "rZMM" },
		2776	{ OPERAND_TYPE_REGMASK, "Mask reg" },
		2777	{ OPERAND_TYPE_ESSEG, "es" },
		2778	};
		2779
		2780	static void
		2781	pt (i386_operand_type t)
		2782	{
		2783	unsigned int j;
		2784	i386_operand_type a;
		2785
		2786	for (j = 0; j < ARRAY_SIZE (type_names); j++)
		2787	{
		2788	a = operand_type_and (t, type_names[j].mask);
		2789	if (!operand_type_all_zero (&a))
		2790	fprintf (stdout, "%s, ", type_names[j].name);
		2791	}
		2792	fflush (stdout);
		2793	}
		2794
		2795	#endif /* DEBUG386 */
		2796
		2797	static bfd_reloc_code_real_type
		2798	reloc (unsigned int size,
		2799	int pcrel,
		2800	int sign,
		2801	int bnd_prefix,
		2802	bfd_reloc_code_real_type other)
		2803	{
		2804	if (other != NO_RELOC)
		2805	{
		2806	reloc_howto_type *rel;
		2807
		2808	if (size == 8)
		2809	switch (other)
		2810	{
		2811	case BFD_RELOC_X86_64_GOT32:
		2812	return BFD_RELOC_X86_64_GOT64;
		2813	break;
		2814	case BFD_RELOC_X86_64_PLTOFF64:
		2815	return BFD_RELOC_X86_64_PLTOFF64;
		2816	break;
		2817	case BFD_RELOC_X86_64_GOTPC32:
		2818	other = BFD_RELOC_X86_64_GOTPC64;
		2819	break;
		2820	case BFD_RELOC_X86_64_GOTPCREL:
		2821	other = BFD_RELOC_X86_64_GOTPCREL64;
		2822	break;
		2823	case BFD_RELOC_X86_64_TPOFF32:
		2824	other = BFD_RELOC_X86_64_TPOFF64;
		2825	break;
		2826	case BFD_RELOC_X86_64_DTPOFF32:
		2827	other = BFD_RELOC_X86_64_DTPOFF64;
		2828	break;
		2829	default:
		2830	break;
		2831	}
		2832
		2833	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		2834	if (other == BFD_RELOC_SIZE32)
		2835	{
		2836	if (size == 8)
		2837	return BFD_RELOC_SIZE64;
		2838	if (pcrel)
		2839	as_bad (_("there are no pc-relative size relocations"));
		2840	}
		2841	#endif
		2842
		2843	/* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
		2844	if (size == 4 && (flag_code != CODE_64BIT \|\| disallow_64bit_reloc))
		2845	sign = -1;
		2846
		2847	rel = bfd_reloc_type_lookup (stdoutput, other);
		2848	if (!rel)
		2849	as_bad (_("unknown relocation (%u)"), other);
		2850	else if (size != bfd_get_reloc_size (rel))
		2851	as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
		2852	bfd_get_reloc_size (rel),
		2853	size);
		2854	else if (pcrel && !rel->pc_relative)
		2855	as_bad (_("non-pc-relative relocation for pc-relative field"));
		2856	else if ((rel->complain_on_overflow == complain_overflow_signed
		2857	&& !sign)
		2858	\|\| (rel->complain_on_overflow == complain_overflow_unsigned
		2859	&& sign > 0))
		2860	as_bad (_("relocated field and relocation type differ in signedness"));
		2861	else
		2862	return other;
		2863	return NO_RELOC;
		2864	}
		2865
		2866	if (pcrel)
		2867	{
		2868	if (!sign)
		2869	as_bad (_("there are no unsigned pc-relative relocations"));
		2870	switch (size)
		2871	{
		2872	case 1: return BFD_RELOC_8_PCREL;
		2873	case 2: return BFD_RELOC_16_PCREL;
		2874	case 4: return (bnd_prefix && object_64bit
		2875	? BFD_RELOC_X86_64_PC32_BND
		2876	: BFD_RELOC_32_PCREL);
		2877	case 8: return BFD_RELOC_64_PCREL;
		2878	}
		2879	as_bad (_("cannot do %u byte pc-relative relocation"), size);
		2880	}
		2881	else
		2882	{
		2883	if (sign > 0)
		2884	switch (size)
		2885	{
		2886	case 4: return BFD_RELOC_X86_64_32S;
		2887	}
		2888	else
		2889	switch (size)
		2890	{
		2891	case 1: return BFD_RELOC_8;
		2892	case 2: return BFD_RELOC_16;
		2893	case 4: return BFD_RELOC_32;
		2894	case 8: return BFD_RELOC_64;
		2895	}
		2896	as_bad (_("cannot do %s %u byte relocation"),
		2897	sign > 0 ? "signed" : "unsigned", size);
		2898	}
		2899
		2900	return NO_RELOC;
		2901	}
		2902
		2903	/* Here we decide which fixups can be adjusted to make them relative to
		2904	the beginning of the section instead of the symbol. Basically we need
		2905	to make sure that the dynamic relocations are done correctly, so in
		2906	some cases we force the original symbol to be used. */
		2907
		2908	int
		2909	tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
		2910	{
		2911	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		2912	if (!IS_ELF)
		2913	return 1;
		2914
		2915	/* Don't adjust pc-relative references to merge sections in 64-bit
		2916	mode. */
		2917	if (use_rela_relocations
		2918	&& (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
		2919	&& fixP->fx_pcrel)
		2920	return 0;
		2921
		2922	/* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
		2923	and changed later by validate_fix. */
		2924	if (GOT_symbol && fixP->fx_subsy == GOT_symbol
		2925	&& fixP->fx_r_type == BFD_RELOC_32_PCREL)
		2926	return 0;
		2927
		2928	/* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
		2929	for size relocations. */
		2930	if (fixP->fx_r_type == BFD_RELOC_SIZE32
		2931	\|\| fixP->fx_r_type == BFD_RELOC_SIZE64
		2932	\|\| fixP->fx_r_type == BFD_RELOC_386_GOTOFF
		2933	\|\| fixP->fx_r_type == BFD_RELOC_386_PLT32
		2934	\|\| fixP->fx_r_type == BFD_RELOC_386_GOT32
		2935	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_GD
		2936	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
		2937	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
		2938	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
		2939	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_IE
		2940	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
		2941	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
		2942	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_LE
		2943	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
		2944	\|\| fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
		2945	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
		2946	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
		2947	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
		2948	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
		2949	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
		2950	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
		2951	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
		2952	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
		2953	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
		2954	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
		2955	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
		2956	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
		2957	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
		2958	\|\| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
		2959	\|\| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
		2960	return 0;
		2961	#endif
		2962	return 1;
		2963	}
		2964
		2965	static int
		2966	intel_float_operand (const char *mnemonic)
		2967	{
		2968	/* Note that the value returned is meaningful only for opcodes with (memory)
		2969	operands, hence the code here is free to improperly handle opcodes that
		2970	have no operands (for better performance and smaller code). */
		2971
		2972	if (mnemonic[0] != 'f')
		2973	return 0; /* non-math */
		2974
		2975	switch (mnemonic[1])
		2976	{
		2977	/* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
		2978	the fs segment override prefix not currently handled because no
		2979	call path can make opcodes without operands get here */
		2980	case 'i':
		2981	return 2 /* integer op */;
		2982	case 'l':
		2983	if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' \|\| mnemonic[3] == 'e'))
		2984	return 3; /* fldcw/fldenv */
		2985	break;
		2986	case 'n':
		2987	if (mnemonic[2] != 'o' /* fnop */)
		2988	return 3; /* non-waiting control op */
		2989	break;
		2990	case 'r':
		2991	if (mnemonic[2] == 's')
		2992	return 3; /* frstor/frstpm */
		2993	break;
		2994	case 's':
		2995	if (mnemonic[2] == 'a')
		2996	return 3; /* fsave */
		2997	if (mnemonic[2] == 't')
		2998	{
		2999	switch (mnemonic[3])
		3000	{
		3001	case 'c': /* fstcw */
		3002	case 'd': /* fstdw */
		3003	case 'e': /* fstenv */
		3004	case 's': /* fsts[gw] */
		3005	return 3;
		3006	}
		3007	}
		3008	break;
		3009	case 'x':
		3010	if (mnemonic[2] == 'r' \|\| mnemonic[2] == 's')
		3011	return 0; /* fxsave/fxrstor are not really math ops */
		3012	break;
		3013	}
		3014
		3015	return 1;
		3016	}
		3017
		3018	/* Build the VEX prefix. */
		3019
		3020	static void
		3021	build_vex_prefix (const insn_template *t)
		3022	{
		3023	unsigned int register_specifier;
		3024	unsigned int implied_prefix;
		3025	unsigned int vector_length;
		3026
		3027	/* Check register specifier. */
		3028	if (i.vex.register_specifier)
		3029	{
		3030	register_specifier =
		3031	~register_number (i.vex.register_specifier) & 0xf;
		3032	gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
		3033	}
		3034	else
		3035	register_specifier = 0xf;
		3036
		3037	/* Use 2-byte VEX prefix by swappping destination and source
		3038	operand. */
		3039	if (!i.swap_operand
		3040	&& i.operands == i.reg_operands
		3041	&& i.tm.opcode_modifier.vexopcode == VEX0F
		3042	&& i.tm.opcode_modifier.s
		3043	&& i.rex == REX_B)
		3044	{
		3045	unsigned int xchg = i.operands - 1;
		3046	union i386_op temp_op;
		3047	i386_operand_type temp_type;
		3048
		3049	temp_type = i.types[xchg];
		3050	i.types[xchg] = i.types[0];
		3051	i.types[0] = temp_type;
		3052	temp_op = i.op[xchg];
		3053	i.op[xchg] = i.op[0];
		3054	i.op[0] = temp_op;
		3055
		3056	gas_assert (i.rm.mode == 3);
		3057
		3058	i.rex = REX_R;
		3059	xchg = i.rm.regmem;
		3060	i.rm.regmem = i.rm.reg;
		3061	i.rm.reg = xchg;
		3062
		3063	/* Use the next insn. */
		3064	i.tm = t[1];
		3065	}
		3066
		3067	if (i.tm.opcode_modifier.vex == VEXScalar)
		3068	vector_length = avxscalar;
		3069	else
		3070	vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
		3071
		3072	switch ((i.tm.base_opcode >> 8) & 0xff)
		3073	{
		3074	case 0:
		3075	implied_prefix = 0;
		3076	break;
		3077	case DATA_PREFIX_OPCODE:
		3078	implied_prefix = 1;
		3079	break;
		3080	case REPE_PREFIX_OPCODE:
		3081	implied_prefix = 2;
		3082	break;
		3083	case REPNE_PREFIX_OPCODE:
		3084	implied_prefix = 3;
		3085	break;
		3086	default:
		3087	abort ();
		3088	}
		3089
		3090	/* Use 2-byte VEX prefix if possible. */
		3091	if (i.tm.opcode_modifier.vexopcode == VEX0F
		3092	&& i.tm.opcode_modifier.vexw != VEXW1
		3093	&& (i.rex & (REX_W \| REX_X \| REX_B)) == 0)
		3094	{
		3095	/* 2-byte VEX prefix. */
		3096	unsigned int r;
		3097
		3098	i.vex.length = 2;
		3099	i.vex.bytes[0] = 0xc5;
		3100
		3101	/* Check the REX.R bit. */
		3102	r = (i.rex & REX_R) ? 0 : 1;
		3103	i.vex.bytes[1] = (r << 7
		3104	\| register_specifier << 3
		3105	\| vector_length << 2
		3106	\| implied_prefix);
		3107	}
		3108	else
		3109	{
		3110	/* 3-byte VEX prefix. */
		3111	unsigned int m, w;
		3112
		3113	i.vex.length = 3;
		3114
		3115	switch (i.tm.opcode_modifier.vexopcode)
		3116	{
		3117	case VEX0F:
		3118	m = 0x1;
		3119	i.vex.bytes[0] = 0xc4;
		3120	break;
		3121	case VEX0F38:
		3122	m = 0x2;
		3123	i.vex.bytes[0] = 0xc4;
		3124	break;
		3125	case VEX0F3A:
		3126	m = 0x3;
		3127	i.vex.bytes[0] = 0xc4;
		3128	break;
		3129	case XOP08:
		3130	m = 0x8;
		3131	i.vex.bytes[0] = 0x8f;
		3132	break;
		3133	case XOP09:
		3134	m = 0x9;
		3135	i.vex.bytes[0] = 0x8f;
		3136	break;
		3137	case XOP0A:
		3138	m = 0xa;
		3139	i.vex.bytes[0] = 0x8f;
		3140	break;
		3141	default:
		3142	abort ();
		3143	}
		3144
		3145	/* The high 3 bits of the second VEX byte are 1's compliment
		3146	of RXB bits from REX. */
		3147	i.vex.bytes[1] = (~i.rex & 0x7) << 5 \| m;
		3148
		3149	/* Check the REX.W bit. */
		3150	w = (i.rex & REX_W) ? 1 : 0;
		3151	if (i.tm.opcode_modifier.vexw)
		3152	{
		3153	if (w)
		3154	abort ();
		3155
		3156	if (i.tm.opcode_modifier.vexw == VEXW1)
		3157	w = 1;
		3158	}
		3159
		3160	i.vex.bytes[2] = (w << 7
		3161	\| register_specifier << 3
		3162	\| vector_length << 2
		3163	\| implied_prefix);
		3164	}
		3165	}
		3166
		3167	/* Build the EVEX prefix. */
		3168
		3169	static void
		3170	build_evex_prefix (void)
		3171	{
		3172	unsigned int register_specifier;
		3173	unsigned int implied_prefix;
		3174	unsigned int m, w;
		3175	rex_byte vrex_used = 0;
		3176
		3177	/* Check register specifier. */
		3178	if (i.vex.register_specifier)
		3179	{
		3180	gas_assert ((i.vrex & REX_X) == 0);
		3181
		3182	register_specifier = i.vex.register_specifier->reg_num;
		3183	if ((i.vex.register_specifier->reg_flags & RegRex))
		3184	register_specifier += 8;
		3185	/* The upper 16 registers are encoded in the fourth byte of the
		3186	EVEX prefix. */
		3187	if (!(i.vex.register_specifier->reg_flags & RegVRex))
		3188	i.vex.bytes[3] = 0x8;
		3189	register_specifier = ~register_specifier & 0xf;
		3190	}
		3191	else
		3192	{
		3193	register_specifier = 0xf;
		3194
		3195	/* Encode upper 16 vector index register in the fourth byte of
		3196	the EVEX prefix. */
		3197	if (!(i.vrex & REX_X))
		3198	i.vex.bytes[3] = 0x8;
		3199	else
		3200	vrex_used \|= REX_X;
		3201	}
		3202
		3203	switch ((i.tm.base_opcode >> 8) & 0xff)
		3204	{
		3205	case 0:
		3206	implied_prefix = 0;
		3207	break;
		3208	case DATA_PREFIX_OPCODE:
		3209	implied_prefix = 1;
		3210	break;
		3211	case REPE_PREFIX_OPCODE:
		3212	implied_prefix = 2;
		3213	break;
		3214	case REPNE_PREFIX_OPCODE:
		3215	implied_prefix = 3;
		3216	break;
		3217	default:
		3218	abort ();
		3219	}
		3220
		3221	/* 4 byte EVEX prefix. */
		3222	i.vex.length = 4;
		3223	i.vex.bytes[0] = 0x62;
		3224
		3225	/* mmmm bits. */
		3226	switch (i.tm.opcode_modifier.vexopcode)
		3227	{
		3228	case VEX0F:
		3229	m = 1;
		3230	break;
		3231	case VEX0F38:
		3232	m = 2;
		3233	break;
		3234	case VEX0F3A:
		3235	m = 3;
		3236	break;
		3237	default:
		3238	abort ();
		3239	break;
		3240	}
		3241
		3242	/* The high 3 bits of the second EVEX byte are 1's compliment of RXB
		3243	bits from REX. */
		3244	i.vex.bytes[1] = (~i.rex & 0x7) << 5 \| m;
		3245
		3246	/* The fifth bit of the second EVEX byte is 1's compliment of the
		3247	REX_R bit in VREX. */
		3248	if (!(i.vrex & REX_R))
		3249	i.vex.bytes[1] \|= 0x10;
		3250	else
		3251	vrex_used \|= REX_R;
		3252
		3253	if ((i.reg_operands + i.imm_operands) == i.operands)
		3254	{
		3255	/* When all operands are registers, the REX_X bit in REX is not
		3256	used. We reuse it to encode the upper 16 registers, which is
		3257	indicated by the REX_B bit in VREX. The REX_X bit is encoded
		3258	as 1's compliment. */
		3259	if ((i.vrex & REX_B))
		3260	{
		3261	vrex_used \|= REX_B;
		3262	i.vex.bytes[1] &= ~0x40;
		3263	}
		3264	}
		3265
		3266	/* EVEX instructions shouldn't need the REX prefix. */
		3267	i.vrex &= ~vrex_used;
		3268	gas_assert (i.vrex == 0);
		3269
		3270	/* Check the REX.W bit. */
		3271	w = (i.rex & REX_W) ? 1 : 0;
		3272	if (i.tm.opcode_modifier.vexw)
		3273	{
		3274	if (i.tm.opcode_modifier.vexw == VEXW1)
		3275	w = 1;
		3276	}
		3277	/* If w is not set it means we are dealing with WIG instruction. */
		3278	else if (!w)
		3279	{
		3280	if (evexwig == evexw1)
		3281	w = 1;
		3282	}
		3283
		3284	/* Encode the U bit. */
		3285	implied_prefix \|= 0x4;
		3286
		3287	/* The third byte of the EVEX prefix. */
		3288	i.vex.bytes[2] = (w << 7 \| register_specifier << 3 \| implied_prefix);
		3289
		3290	/* The fourth byte of the EVEX prefix. */
		3291	/* The zeroing-masking bit. */
		3292	if (i.mask && i.mask->zeroing)
		3293	i.vex.bytes[3] \|= 0x80;
		3294
		3295	/* Don't always set the broadcast bit if there is no RC. */
		3296	if (!i.rounding)
		3297	{
		3298	/* Encode the vector length. */
		3299	unsigned int vec_length;
		3300
		3301	switch (i.tm.opcode_modifier.evex)
		3302	{
		3303	case EVEXLIG: /* LL' is ignored */
		3304	vec_length = evexlig << 5;
		3305	break;
		3306	case EVEX128:
		3307	vec_length = 0 << 5;
		3308	break;
		3309	case EVEX256:
		3310	vec_length = 1 << 5;
		3311	break;
		3312	case EVEX512:
		3313	vec_length = 2 << 5;
		3314	break;
		3315	default:
		3316	abort ();
		3317	break;
		3318	}
		3319	i.vex.bytes[3] \|= vec_length;
		3320	/* Encode the broadcast bit. */
		3321	if (i.broadcast)
		3322	i.vex.bytes[3] \|= 0x10;
		3323	}
		3324	else
		3325	{
		3326	if (i.rounding->type != saeonly)
		3327	i.vex.bytes[3] \|= 0x10 \| (i.rounding->type << 5);
		3328	else
		3329	i.vex.bytes[3] \|= 0x10;
		3330	}
		3331
		3332	if (i.mask && i.mask->mask)
		3333	i.vex.bytes[3] \|= i.mask->mask->reg_num;
		3334	}
		3335
		3336	static void
		3337	process_immext (void)
		3338	{
		3339	expressionS *exp;
		3340
		3341	if ((i.tm.cpu_flags.bitfield.cpusse3 \|\| i.tm.cpu_flags.bitfield.cpusvme)
		3342	&& i.operands > 0)
		3343	{
		3344	/* MONITOR/MWAIT as well as SVME instructions have fixed operands
		3345	with an opcode suffix which is coded in the same place as an
		3346	8-bit immediate field would be.
		3347	Here we check those operands and remove them afterwards. */
		3348	unsigned int x;
		3349
		3350	for (x = 0; x < i.operands; x++)
		3351	if (register_number (i.op[x].regs) != x)
		3352	as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
		3353	register_prefix, i.op[x].regs->reg_name, x + 1,
		3354	i.tm.name);
		3355
		3356	i.operands = 0;
		3357	}
		3358
		3359	/* These AMD 3DNow! and SSE2 instructions have an opcode suffix
		3360	which is coded in the same place as an 8-bit immediate field
		3361	would be. Here we fake an 8-bit immediate operand from the
		3362	opcode suffix stored in tm.extension_opcode.
		3363
		3364	AVX instructions also use this encoding, for some of
		3365	3 argument instructions. */
		3366
		3367	gas_assert (i.imm_operands <= 1
		3368	&& (i.operands <= 2
		3369	\|\| ((i.tm.opcode_modifier.vex
		3370	\|\| i.tm.opcode_modifier.evex)
		3371	&& i.operands <= 4)));
		3372
		3373	exp = &im_expressions[i.imm_operands++];
		3374	i.op[i.operands].imms = exp;
		3375	i.types[i.operands] = imm8;
		3376	i.operands++;
		3377	exp->X_op = O_constant;
		3378	exp->X_add_number = i.tm.extension_opcode;
		3379	i.tm.extension_opcode = None;
		3380	}
		3381
		3382
		3383	static int
		3384	check_hle (void)
		3385	{
		3386	switch (i.tm.opcode_modifier.hleprefixok)
		3387	{
		3388	default:
		3389	abort ();
		3390	case HLEPrefixNone:
		3391	as_bad (_("invalid instruction `%s' after `%s'"),
		3392	i.tm.name, i.hle_prefix);
		3393	return 0;
		3394	case HLEPrefixLock:
		3395	if (i.prefix[LOCK_PREFIX])
		3396	return 1;
		3397	as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
		3398	return 0;
		3399	case HLEPrefixAny:
		3400	return 1;
		3401	case HLEPrefixRelease:
		3402	if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
		3403	{
		3404	as_bad (_("instruction `%s' after `xacquire' not allowed"),
		3405	i.tm.name);
		3406	return 0;
		3407	}
		3408	if (i.mem_operands == 0
		3409	\|\| !operand_type_check (i.types[i.operands - 1], anymem))
		3410	{
		3411	as_bad (_("memory destination needed for instruction `%s'"
		3412	" after `xrelease'"), i.tm.name);
		3413	return 0;
		3414	}
		3415	return 1;
		3416	}
		3417	}
		3418
		3419	/* This is the guts of the machine-dependent assembler. LINE points to a
		3420	machine dependent instruction. This function is supposed to emit
		3421	the frags/bytes it assembles to. */
		3422
		3423	void
		3424	md_assemble (char *line)
		3425	{
		3426	unsigned int j;
		3427	char mnemonic[MAX_MNEM_SIZE];
		3428	const insn_template *t;
		3429
		3430	/* Initialize globals. */
		3431	memset (&i, '\0', sizeof (i));
		3432	for (j = 0; j < MAX_OPERANDS; j++)
		3433	i.reloc[j] = NO_RELOC;
		3434	memset (disp_expressions, '\0', sizeof (disp_expressions));
		3435	memset (im_expressions, '\0', sizeof (im_expressions));
		3436	save_stack_p = save_stack;
		3437
		3438	/* First parse an instruction mnemonic & call i386_operand for the operands.
		3439	We assume that the scrubber has arranged it so that line[0] is the valid
		3440	start of a (possibly prefixed) mnemonic. */
		3441
		3442	line = parse_insn (line, mnemonic);
		3443	if (line == NULL)
		3444	return;
		3445
		3446	line = parse_operands (line, mnemonic);
		3447	this_operand = -1;
		3448	if (line == NULL)
		3449	return;
		3450
		3451	/* Now we've parsed the mnemonic into a set of templates, and have the
		3452	operands at hand. */
		3453
		3454	/* All intel opcodes have reversed operands except for "bound" and
		3455	"enter". We also don't reverse intersegment "jmp" and "call"
		3456	instructions with 2 immediate operands so that the immediate segment
		3457	precedes the offset, as it does when in AT&T mode. */
		3458	if (intel_syntax
		3459	&& i.operands > 1
		3460	&& (strcmp (mnemonic, "bound") != 0)
		3461	&& (strcmp (mnemonic, "invlpga") != 0)
		3462	&& !(operand_type_check (i.types[0], imm)
		3463	&& operand_type_check (i.types[1], imm)))
		3464	swap_operands ();
		3465
		3466	/* The order of the immediates should be reversed
		3467	for 2 immediates extrq and insertq instructions */
		3468	if (i.imm_operands == 2
		3469	&& (strcmp (mnemonic, "extrq") == 0
		3470	\|\| strcmp (mnemonic, "insertq") == 0))
		3471	swap_2_operands (0, 1);
		3472
		3473	if (i.imm_operands)
		3474	optimize_imm ();
		3475
		3476	/* Don't optimize displacement for movabs since it only takes 64bit
		3477	displacement. */
		3478	if (i.disp_operands
		3479	&& i.disp_encoding != disp_encoding_32bit
		3480	&& (flag_code != CODE_64BIT
		3481	\|\| strcmp (mnemonic, "movabs") != 0))
		3482	optimize_disp ();
		3483
		3484	/* Next, we find a template that matches the given insn,
		3485	making sure the overlap of the given operands types is consistent
		3486	with the template operand types. */
		3487
		3488	if (!(t = match_template ()))
		3489	return;
		3490
		3491	if (sse_check != check_none
		3492	&& !i.tm.opcode_modifier.noavx
		3493	&& (i.tm.cpu_flags.bitfield.cpusse
		3494	\|\| i.tm.cpu_flags.bitfield.cpusse2
		3495	\|\| i.tm.cpu_flags.bitfield.cpusse3
		3496	\|\| i.tm.cpu_flags.bitfield.cpussse3
		3497	\|\| i.tm.cpu_flags.bitfield.cpusse4_1
		3498	\|\| i.tm.cpu_flags.bitfield.cpusse4_2))
		3499	{
		3500	(sse_check == check_warning
		3501	? as_warn
		3502	: as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
		3503	}
		3504
		3505	/* Zap movzx and movsx suffix. The suffix has been set from
		3506	"word ptr" or "byte ptr" on the source operand in Intel syntax
		3507	or extracted from mnemonic in AT&T syntax. But we'll use
		3508	the destination register to choose the suffix for encoding. */
		3509	if ((i.tm.base_opcode & ~9) == 0x0fb6)
		3510	{
		3511	/* In Intel syntax, there must be a suffix. In AT&T syntax, if
		3512	there is no suffix, the default will be byte extension. */
		3513	if (i.reg_operands != 2
		3514	&& !i.suffix
		3515	&& intel_syntax)
		3516	as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
		3517
		3518	i.suffix = 0;
		3519	}
		3520
		3521	if (i.tm.opcode_modifier.fwait)
		3522	if (!add_prefix (FWAIT_OPCODE))
		3523	return;
		3524
		3525	/* Check if REP prefix is OK. */
		3526	if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
		3527	{
		3528	as_bad (_("invalid instruction `%s' after `%s'"),
		3529	i.tm.name, i.rep_prefix);
		3530	return;
		3531	}
		3532
		3533	/* Check for lock without a lockable instruction. Destination operand
		3534	must be memory unless it is xchg (0x86). */
		3535	if (i.prefix[LOCK_PREFIX]
		3536	&& (!i.tm.opcode_modifier.islockable
		3537	\|\| i.mem_operands == 0
		3538	\|\| (i.tm.base_opcode != 0x86
		3539	&& !operand_type_check (i.types[i.operands - 1], anymem))))
		3540	{
		3541	as_bad (_("expecting lockable instruction after `lock'"));
		3542	return;
		3543	}
		3544
		3545	/* Check if HLE prefix is OK. */
		3546	if (i.hle_prefix && !check_hle ())
		3547	return;
		3548
		3549	/* Check BND prefix. */
		3550	if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
		3551	as_bad (_("expecting valid branch instruction after `bnd'"));
		3552
		3553	if (i.tm.cpu_flags.bitfield.cpumpx
		3554	&& flag_code == CODE_64BIT
		3555	&& i.prefix[ADDR_PREFIX])
		3556	as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
		3557
		3558	/* Insert BND prefix. */
		3559	if (add_bnd_prefix
		3560	&& i.tm.opcode_modifier.bndprefixok
		3561	&& !i.prefix[BND_PREFIX])
		3562	add_prefix (BND_PREFIX_OPCODE);
		3563
		3564	/* Check string instruction segment overrides. */
		3565	if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
		3566	{
		3567	if (!check_string ())
		3568	return;
		3569	i.disp_operands = 0;
		3570	}
		3571
		3572	if (!process_suffix ())
		3573	return;
		3574
		3575	/* Update operand types. */
		3576	for (j = 0; j < i.operands; j++)
		3577	i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
		3578
		3579	/* Make still unresolved immediate matches conform to size of immediate
		3580	given in i.suffix. */
		3581	if (!finalize_imm ())
		3582	return;
		3583
		3584	if (i.types[0].bitfield.imm1)
		3585	i.imm_operands = 0; /* kludge for shift insns. */
		3586
		3587	/* We only need to check those implicit registers for instructions
		3588	with 3 operands or less. */
		3589	if (i.operands <= 3)
		3590	for (j = 0; j < i.operands; j++)
		3591	if (i.types[j].bitfield.inoutportreg
		3592	\|\| i.types[j].bitfield.shiftcount
		3593	\|\| i.types[j].bitfield.acc
		3594	\|\| i.types[j].bitfield.floatacc)
		3595	i.reg_operands--;
		3596
		3597	/* ImmExt should be processed after SSE2AVX. */
		3598	if (!i.tm.opcode_modifier.sse2avx
		3599	&& i.tm.opcode_modifier.immext)
		3600	process_immext ();
		3601
		3602	/* For insns with operands there are more diddles to do to the opcode. */
		3603	if (i.operands)
		3604	{
		3605	if (!process_operands ())
		3606	return;
		3607	}
		3608	else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
		3609	{
		3610	/* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
		3611	as_warn (_("translating to `%sp'"), i.tm.name);
		3612	}
		3613
		3614	if (i.tm.opcode_modifier.vex)
		3615	build_vex_prefix (t);
		3616
		3617	if (i.tm.opcode_modifier.evex)
		3618	build_evex_prefix ();
		3619
		3620	/* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
		3621	instructions may define INT_OPCODE as well, so avoid this corner
		3622	case for those instructions that use MODRM. */
		3623	if (i.tm.base_opcode == INT_OPCODE
		3624	&& !i.tm.opcode_modifier.modrm
		3625	&& i.op[0].imms->X_add_number == 3)
		3626	{
		3627	i.tm.base_opcode = INT3_OPCODE;
		3628	i.imm_operands = 0;
		3629	}
		3630
		3631	if ((i.tm.opcode_modifier.jump
		3632	\|\| i.tm.opcode_modifier.jumpbyte
		3633	\|\| i.tm.opcode_modifier.jumpdword)
		3634	&& i.op[0].disps->X_op == O_constant)
		3635	{
		3636	/* Convert "jmp constant" (and "call constant") to a jump (call) to
		3637	the absolute address given by the constant. Since ix86 jumps and
		3638	calls are pc relative, we need to generate a reloc. */
		3639	i.op[0].disps->X_add_symbol = &abs_symbol;
		3640	i.op[0].disps->X_op = O_symbol;
		3641	}
		3642
		3643	if (i.tm.opcode_modifier.rex64)
		3644	i.rex \|= REX_W;
		3645
		3646	/* For 8 bit registers we need an empty rex prefix. Also if the
		3647	instruction already has a prefix, we need to convert old
		3648	registers to new ones. */
		3649
		3650	if ((i.types[0].bitfield.reg8
		3651	&& (i.op[0].regs->reg_flags & RegRex64) != 0)
		3652	\|\| (i.types[1].bitfield.reg8
		3653	&& (i.op[1].regs->reg_flags & RegRex64) != 0)
		3654	\|\| ((i.types[0].bitfield.reg8
		3655	\|\| i.types[1].bitfield.reg8)
		3656	&& i.rex != 0))
		3657	{
		3658	int x;
		3659
		3660	i.rex \|= REX_OPCODE;
		3661	for (x = 0; x < 2; x++)
		3662	{
		3663	/* Look for 8 bit operand that uses old registers. */
		3664	if (i.types[x].bitfield.reg8
		3665	&& (i.op[x].regs->reg_flags & RegRex64) == 0)
		3666	{
		3667	/* In case it is "hi" register, give up. */
		3668	if (i.op[x].regs->reg_num > 3)
		3669	as_bad (_("can't encode register '%s%s' in an "
		3670	"instruction requiring REX prefix."),
		3671	register_prefix, i.op[x].regs->reg_name);
		3672
		3673	/* Otherwise it is equivalent to the extended register.
		3674	Since the encoding doesn't change this is merely
		3675	cosmetic cleanup for debug output. */
		3676
		3677	i.op[x].regs = i.op[x].regs + 8;
		3678	}
		3679	}
		3680	}
		3681
		3682	if (i.rex != 0)
		3683	add_prefix (REX_OPCODE \| i.rex);
		3684
		3685	/* We are ready to output the insn. */
		3686	output_insn ();
		3687	}
		3688
		3689	static char *
		3690	parse_insn (char line, char mnemonic)
		3691	{
		3692	char *l = line;
		3693	char *token_start = l;
		3694	char *mnem_p;
		3695	int supported;
		3696	const insn_template *t;
		3697	char *dot_p = NULL;
		3698
		3699	while (1)
		3700	{
		3701	mnem_p = mnemonic;
		3702	while ((mnem_p = mnemonic_chars[(unsigned char) l]) != 0)
		3703	{
		3704	if (*mnem_p == '.')
		3705	dot_p = mnem_p;
		3706	mnem_p++;
		3707	if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
		3708	{
		3709	as_bad (_("no such instruction: `%s'"), token_start);
		3710	return NULL;
		3711	}
		3712	l++;
		3713	}
		3714	if (!is_space_char (*l)
		3715	&& *l != END_OF_INSN
		3716	&& (intel_syntax
		3717	\|\| (*l != PREFIX_SEPARATOR
		3718	&& *l != ',')))
		3719	{
		3720	as_bad (_("invalid character %s in mnemonic"),
		3721	output_invalid (*l));
		3722	return NULL;
		3723	}
		3724	if (token_start == l)
		3725	{
		3726	if (!intel_syntax && *l == PREFIX_SEPARATOR)
		3727	as_bad (_("expecting prefix; got nothing"));
		3728	else
		3729	as_bad (_("expecting mnemonic; got nothing"));
		3730	return NULL;
		3731	}
		3732
		3733	/* Look up instruction (or prefix) via hash table. */
		3734	current_templates = (const templates *) hash_find (op_hash, mnemonic);
		3735
		3736	if (*l != END_OF_INSN
		3737	&& (!is_space_char (*l) \|\| l[1] != END_OF_INSN)
		3738	&& current_templates
		3739	&& current_templates->start->opcode_modifier.isprefix)
		3740	{
		3741	if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
		3742	{
		3743	as_bad ((flag_code != CODE_64BIT
		3744	? _("`%s' is only supported in 64-bit mode")
		3745	: _("`%s' is not supported in 64-bit mode")),
		3746	current_templates->start->name);
		3747	return NULL;
		3748	}
		3749	/* If we are in 16-bit mode, do not allow addr16 or data16.
		3750	Similarly, in 32-bit mode, do not allow addr32 or data32. */
		3751	if ((current_templates->start->opcode_modifier.size16
		3752	\|\| current_templates->start->opcode_modifier.size32)
		3753	&& flag_code != CODE_64BIT
		3754	&& (current_templates->start->opcode_modifier.size32
		3755	^ (flag_code == CODE_16BIT)))
		3756	{
		3757	as_bad (_("redundant %s prefix"),
		3758	current_templates->start->name);
		3759	return NULL;
		3760	}
		3761	/* Add prefix, checking for repeated prefixes. */
		3762	switch (add_prefix (current_templates->start->base_opcode))
		3763	{
		3764	case PREFIX_EXIST:
		3765	return NULL;
		3766	case PREFIX_REP:
		3767	if (current_templates->start->cpu_flags.bitfield.cpuhle)
		3768	i.hle_prefix = current_templates->start->name;
		3769	else if (current_templates->start->cpu_flags.bitfield.cpumpx)
		3770	i.bnd_prefix = current_templates->start->name;
		3771	else
		3772	i.rep_prefix = current_templates->start->name;
		3773	break;
		3774	default:
		3775	break;
		3776	}
		3777	/* Skip past PREFIX_SEPARATOR and reset token_start. */
		3778	token_start = ++l;
		3779	}
		3780	else
		3781	break;
		3782	}
		3783
		3784	if (!current_templates)
		3785	{
		3786	/* Check if we should swap operand or force 32bit displacement in
		3787	encoding. */
		3788	if (mnem_p - 2 == dot_p && dot_p[1] == 's')
		3789	i.swap_operand = 1;
		3790	else if (mnem_p - 3 == dot_p
		3791	&& dot_p[1] == 'd'
		3792	&& dot_p[2] == '8')
		3793	i.disp_encoding = disp_encoding_8bit;
		3794	else if (mnem_p - 4 == dot_p
		3795	&& dot_p[1] == 'd'
		3796	&& dot_p[2] == '3'
		3797	&& dot_p[3] == '2')
		3798	i.disp_encoding = disp_encoding_32bit;
		3799	else
		3800	goto check_suffix;
		3801	mnem_p = dot_p;
		3802	*dot_p = '\0';
		3803	current_templates = (const templates *) hash_find (op_hash, mnemonic);
		3804	}
		3805
		3806	if (!current_templates)
		3807	{
		3808	check_suffix:
		3809	/* See if we can get a match by trimming off a suffix. */
		3810	switch (mnem_p[-1])
		3811	{
		3812	case WORD_MNEM_SUFFIX:
		3813	if (intel_syntax && (intel_float_operand (mnemonic) & 2))
		3814	i.suffix = SHORT_MNEM_SUFFIX;
		3815	else
		3816	case BYTE_MNEM_SUFFIX:
		3817	case QWORD_MNEM_SUFFIX:
		3818	i.suffix = mnem_p[-1];
		3819	mnem_p[-1] = '\0';
		3820	current_templates = (const templates *) hash_find (op_hash,
		3821	mnemonic);
		3822	break;
		3823	case SHORT_MNEM_SUFFIX:
		3824	case LONG_MNEM_SUFFIX:
		3825	if (!intel_syntax)
		3826	{
		3827	i.suffix = mnem_p[-1];
		3828	mnem_p[-1] = '\0';
		3829	current_templates = (const templates *) hash_find (op_hash,
		3830	mnemonic);
		3831	}
		3832	break;
		3833
		3834	/* Intel Syntax. */
		3835	case 'd':
		3836	if (intel_syntax)
		3837	{
		3838	if (intel_float_operand (mnemonic) == 1)
		3839	i.suffix = SHORT_MNEM_SUFFIX;
		3840	else
		3841	i.suffix = LONG_MNEM_SUFFIX;
		3842	mnem_p[-1] = '\0';
		3843	current_templates = (const templates *) hash_find (op_hash,
		3844	mnemonic);
		3845	}
		3846	break;
		3847	}
		3848	if (!current_templates)
		3849	{
		3850	as_bad (_("no such instruction: `%s'"), token_start);
		3851	return NULL;
		3852	}
		3853	}
		3854
		3855	if (current_templates->start->opcode_modifier.jump
		3856	\|\| current_templates->start->opcode_modifier.jumpbyte)
		3857	{
		3858	/* Check for a branch hint. We allow ",pt" and ",pn" for
		3859	predict taken and predict not taken respectively.
		3860	I'm not sure that branch hints actually do anything on loop
		3861	and jcxz insns (JumpByte) for current Pentium4 chips. They
		3862	may work in the future and it doesn't hurt to accept them
		3863	now. */
		3864	if (l[0] == ',' && l[1] == 'p')
		3865	{
		3866	if (l[2] == 't')
		3867	{
		3868	if (!add_prefix (DS_PREFIX_OPCODE))
		3869	return NULL;
		3870	l += 3;
		3871	}
		3872	else if (l[2] == 'n')
		3873	{
		3874	if (!add_prefix (CS_PREFIX_OPCODE))
		3875	return NULL;
		3876	l += 3;
		3877	}
		3878	}
		3879	}
		3880	/* Any other comma loses. */
		3881	if (*l == ',')
		3882	{
		3883	as_bad (_("invalid character %s in mnemonic"),
		3884	output_invalid (*l));
		3885	return NULL;
		3886	}
		3887
		3888	/* Check if instruction is supported on specified architecture. */
		3889	supported = 0;
		3890	for (t = current_templates->start; t < current_templates->end; ++t)
		3891	{
		3892	supported \|= cpu_flags_match (t);
		3893	if (supported == CPU_FLAGS_PERFECT_MATCH)
		3894	goto skip;
		3895	}
		3896
		3897	if (!(supported & CPU_FLAGS_64BIT_MATCH))
		3898	{
		3899	as_bad (flag_code == CODE_64BIT
		3900	? _("`%s' is not supported in 64-bit mode")
		3901	: _("`%s' is only supported in 64-bit mode"),
		3902	current_templates->start->name);
		3903	return NULL;
		3904	}
		3905	if (supported != CPU_FLAGS_PERFECT_MATCH)
		3906	{
		3907	as_bad (_("`%s' is not supported on `%s%s'"),
		3908	current_templates->start->name,
		3909	cpu_arch_name ? cpu_arch_name : default_arch,
		3910	cpu_sub_arch_name ? cpu_sub_arch_name : "");
		3911	return NULL;
		3912	}
		3913
		3914	skip:
		3915	if (!cpu_arch_flags.bitfield.cpui386
		3916	&& (flag_code != CODE_16BIT))
		3917	{
		3918	as_warn (_("use .code16 to ensure correct addressing mode"));
		3919	}
		3920
		3921	return l;
		3922	}
		3923
		3924	static char *
		3925	parse_operands (char l, const char mnemonic)
		3926	{
		3927	char *token_start;
		3928
		3929	/* 1 if operand is pending after ','. */
		3930	unsigned int expecting_operand = 0;
		3931
		3932	/* Non-zero if operand parens not balanced. */
		3933	unsigned int paren_not_balanced;
		3934
		3935	while (*l != END_OF_INSN)
		3936	{
		3937	/* Skip optional white space before operand. */
		3938	if (is_space_char (*l))
		3939	++l;
		3940	if (!is_operand_char (l) && l != END_OF_INSN)
		3941	{
		3942	as_bad (_("invalid character %s before operand %d"),
		3943	output_invalid (*l),
		3944	i.operands + 1);
		3945	return NULL;
		3946	}
		3947	token_start = l; /* after white space */
		3948	paren_not_balanced = 0;
		3949	while (paren_not_balanced \|\| *l != ',')
		3950	{
		3951	if (*l == END_OF_INSN)
		3952	{
		3953	if (paren_not_balanced)
		3954	{
		3955	if (!intel_syntax)
		3956	as_bad (_("unbalanced parenthesis in operand %d."),
		3957	i.operands + 1);
		3958	else
		3959	as_bad (_("unbalanced brackets in operand %d."),
		3960	i.operands + 1);
		3961	return NULL;
		3962	}
		3963	else
		3964	break; /* we are done */
		3965	}
		3966	else if (!is_operand_char (l) && !is_space_char (l))
		3967	{
		3968	as_bad (_("invalid character %s in operand %d"),
		3969	output_invalid (*l),
		3970	i.operands + 1);
		3971	return NULL;
		3972	}
		3973	if (!intel_syntax)
		3974	{
		3975	if (*l == '(')
		3976	++paren_not_balanced;
		3977	if (*l == ')')
		3978	--paren_not_balanced;
		3979	}
		3980	else
		3981	{
		3982	if (*l == '[')
		3983	++paren_not_balanced;
		3984	if (*l == ']')
		3985	--paren_not_balanced;
		3986	}
		3987	l++;
		3988	}
		3989	if (l != token_start)
		3990	{ /* Yes, we've read in another operand. */
		3991	unsigned int operand_ok;
		3992	this_operand = i.operands++;
		3993	i.types[this_operand].bitfield.unspecified = 1;
		3994	if (i.operands > MAX_OPERANDS)
		3995	{
		3996	as_bad (_("spurious operands; (%d operands/instruction max)"),
		3997	MAX_OPERANDS);
		3998	return NULL;
		3999	}
		4000	/* Now parse operand adding info to 'i' as we go along. */
		4001	END_STRING_AND_SAVE (l);
		4002
		4003	if (intel_syntax)
		4004	operand_ok =
		4005	i386_intel_operand (token_start,
		4006	intel_float_operand (mnemonic));
		4007	else
		4008	operand_ok = i386_att_operand (token_start);
		4009
		4010	RESTORE_END_STRING (l);
		4011	if (!operand_ok)
		4012	return NULL;
		4013	}
		4014	else
		4015	{
		4016	if (expecting_operand)
		4017	{
		4018	expecting_operand_after_comma:
		4019	as_bad (_("expecting operand after ','; got nothing"));
		4020	return NULL;
		4021	}
		4022	if (*l == ',')
		4023	{
		4024	as_bad (_("expecting operand before ','; got nothing"));
		4025	return NULL;
		4026	}
		4027	}
		4028
		4029	/* Now l must be either ',' or END_OF_INSN. /
		4030	if (*l == ',')
		4031	{
		4032	if (*++l == END_OF_INSN)
		4033	{
		4034	/* Just skip it, if it's \n complain. */
		4035	goto expecting_operand_after_comma;
		4036	}
		4037	expecting_operand = 1;
		4038	}
		4039	}
		4040	return l;
		4041	}
		4042
		4043	static void
		4044	swap_2_operands (int xchg1, int xchg2)
		4045	{
		4046	union i386_op temp_op;
		4047	i386_operand_type temp_type;
		4048	enum bfd_reloc_code_real temp_reloc;
		4049
		4050	temp_type = i.types[xchg2];
		4051	i.types[xchg2] = i.types[xchg1];
		4052	i.types[xchg1] = temp_type;
		4053	temp_op = i.op[xchg2];
		4054	i.op[xchg2] = i.op[xchg1];
		4055	i.op[xchg1] = temp_op;
		4056	temp_reloc = i.reloc[xchg2];
		4057	i.reloc[xchg2] = i.reloc[xchg1];
		4058	i.reloc[xchg1] = temp_reloc;
		4059
		4060	if (i.mask)
		4061	{
		4062	if (i.mask->operand == xchg1)
		4063	i.mask->operand = xchg2;
		4064	else if (i.mask->operand == xchg2)
		4065	i.mask->operand = xchg1;
		4066	}
		4067	if (i.broadcast)
		4068	{
		4069	if (i.broadcast->operand == xchg1)
		4070	i.broadcast->operand = xchg2;
		4071	else if (i.broadcast->operand == xchg2)
		4072	i.broadcast->operand = xchg1;
		4073	}
		4074	if (i.rounding)
		4075	{
		4076	if (i.rounding->operand == xchg1)
		4077	i.rounding->operand = xchg2;
		4078	else if (i.rounding->operand == xchg2)
		4079	i.rounding->operand = xchg1;
		4080	}
		4081	}
		4082
		4083	static void
		4084	swap_operands (void)
		4085	{
		4086	switch (i.operands)
		4087	{
		4088	case 5:
		4089	case 4:
		4090	swap_2_operands (1, i.operands - 2);
		4091	case 3:
		4092	case 2:
		4093	swap_2_operands (0, i.operands - 1);
		4094	break;
		4095	default:
		4096	abort ();
		4097	}
		4098
		4099	if (i.mem_operands == 2)
		4100	{
		4101	const seg_entry *temp_seg;
		4102	temp_seg = i.seg[0];
		4103	i.seg[0] = i.seg[1];
		4104	i.seg[1] = temp_seg;
		4105	}
		4106	}
		4107
		4108	/* Try to ensure constant immediates are represented in the smallest
		4109	opcode possible. */
		4110	static void
		4111	optimize_imm (void)
		4112	{
		4113	char guess_suffix = 0;
		4114	int op;
		4115
		4116	if (i.suffix)
		4117	guess_suffix = i.suffix;
		4118	else if (i.reg_operands)
		4119	{
		4120	/* Figure out a suffix from the last register operand specified.
		4121	We can't do this properly yet, ie. excluding InOutPortReg,
		4122	but the following works for instructions with immediates.
		4123	In any case, we can't set i.suffix yet. */
		4124	for (op = i.operands; --op >= 0;)
		4125	if (i.types[op].bitfield.reg8)
		4126	{
		4127	guess_suffix = BYTE_MNEM_SUFFIX;
		4128	break;
		4129	}
		4130	else if (i.types[op].bitfield.reg16)
		4131	{
		4132	guess_suffix = WORD_MNEM_SUFFIX;
		4133	break;
		4134	}
		4135	else if (i.types[op].bitfield.reg32)
		4136	{
		4137	guess_suffix = LONG_MNEM_SUFFIX;
		4138	break;
		4139	}
		4140	else if (i.types[op].bitfield.reg64)
		4141	{
		4142	guess_suffix = QWORD_MNEM_SUFFIX;
		4143	break;
		4144	}
		4145	}
		4146	else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
		4147	guess_suffix = WORD_MNEM_SUFFIX;
		4148
		4149	for (op = i.operands; --op >= 0;)
		4150	if (operand_type_check (i.types[op], imm))
		4151	{
		4152	switch (i.op[op].imms->X_op)
		4153	{
		4154	case O_constant:
		4155	/* If a suffix is given, this operand may be shortened. */
		4156	switch (guess_suffix)
		4157	{
		4158	case LONG_MNEM_SUFFIX:
		4159	i.types[op].bitfield.imm32 = 1;
		4160	i.types[op].bitfield.imm64 = 1;
		4161	break;
		4162	case WORD_MNEM_SUFFIX:
		4163	i.types[op].bitfield.imm16 = 1;
		4164	i.types[op].bitfield.imm32 = 1;
		4165	i.types[op].bitfield.imm32s = 1;
		4166	i.types[op].bitfield.imm64 = 1;
		4167	break;
		4168	case BYTE_MNEM_SUFFIX:
		4169	i.types[op].bitfield.imm8 = 1;
		4170	i.types[op].bitfield.imm8s = 1;
		4171	i.types[op].bitfield.imm16 = 1;
		4172	i.types[op].bitfield.imm32 = 1;
		4173	i.types[op].bitfield.imm32s = 1;
		4174	i.types[op].bitfield.imm64 = 1;
		4175	break;
		4176	}
		4177
		4178	/* If this operand is at most 16 bits, convert it
		4179	to a signed 16 bit number before trying to see
		4180	whether it will fit in an even smaller size.
		4181	This allows a 16-bit operand such as $0xffe0 to
		4182	be recognised as within Imm8S range. */
		4183	if ((i.types[op].bitfield.imm16)
		4184	&& (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
		4185	{
		4186	i.op[op].imms->X_add_number =
		4187	(((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
		4188	}
		4189	if ((i.types[op].bitfield.imm32)
		4190	&& ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
		4191	== 0))
		4192	{
		4193	i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
		4194	^ ((offsetT) 1 << 31))
		4195	- ((offsetT) 1 << 31));
		4196	}
		4197	i.types[op]
		4198	= operand_type_or (i.types[op],
		4199	smallest_imm_type (i.op[op].imms->X_add_number));
		4200
		4201	/* We must avoid matching of Imm32 templates when 64bit
		4202	only immediate is available. */
		4203	if (guess_suffix == QWORD_MNEM_SUFFIX)
		4204	i.types[op].bitfield.imm32 = 0;
		4205	break;
		4206
		4207	case O_absent:
		4208	case O_register:
		4209	abort ();
		4210
		4211	/* Symbols and expressions. */
		4212	default:
		4213	/* Convert symbolic operand to proper sizes for matching, but don't
		4214	prevent matching a set of insns that only supports sizes other
		4215	than those matching the insn suffix. */
		4216	{
		4217	i386_operand_type mask, allowed;
		4218	const insn_template *t;
		4219
		4220	operand_type_set (&mask, 0);
		4221	operand_type_set (&allowed, 0);
		4222
		4223	for (t = current_templates->start;
		4224	t < current_templates->end;
		4225	++t)
		4226	allowed = operand_type_or (allowed,
		4227	t->operand_types[op]);
		4228	switch (guess_suffix)
		4229	{
		4230	case QWORD_MNEM_SUFFIX:
		4231	mask.bitfield.imm64 = 1;
		4232	mask.bitfield.imm32s = 1;
		4233	break;
		4234	case LONG_MNEM_SUFFIX:
		4235	mask.bitfield.imm32 = 1;
		4236	break;
		4237	case WORD_MNEM_SUFFIX:
		4238	mask.bitfield.imm16 = 1;
		4239	break;
		4240	case BYTE_MNEM_SUFFIX:
		4241	mask.bitfield.imm8 = 1;
		4242	break;
		4243	default:
		4244	break;
		4245	}
		4246	allowed = operand_type_and (mask, allowed);
		4247	if (!operand_type_all_zero (&allowed))
		4248	i.types[op] = operand_type_and (i.types[op], mask);
		4249	}
		4250	break;
		4251	}
		4252	}
		4253	}
		4254
		4255	/* Try to use the smallest displacement type too. */
		4256	static void
		4257	optimize_disp (void)
		4258	{
		4259	int op;
		4260
		4261	for (op = i.operands; --op >= 0;)
		4262	if (operand_type_check (i.types[op], disp))
		4263	{
		4264	if (i.op[op].disps->X_op == O_constant)
		4265	{
		4266	offsetT op_disp = i.op[op].disps->X_add_number;
		4267
		4268	if (i.types[op].bitfield.disp16
		4269	&& (op_disp & ~(offsetT) 0xffff) == 0)
		4270	{
		4271	/* If this operand is at most 16 bits, convert
		4272	to a signed 16 bit number and don't use 64bit
		4273	displacement. */
		4274	op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
		4275	i.types[op].bitfield.disp64 = 0;
		4276	}
		4277	if (i.types[op].bitfield.disp32
		4278	&& (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
		4279	{
		4280	/* If this operand is at most 32 bits, convert
		4281	to a signed 32 bit number and don't use 64bit
		4282	displacement. */
		4283	op_disp &= (((offsetT) 2 << 31) - 1);
		4284	op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
		4285	i.types[op].bitfield.disp64 = 0;
		4286	}
		4287	if (!op_disp && i.types[op].bitfield.baseindex)
		4288	{
		4289	i.types[op].bitfield.disp8 = 0;
		4290	i.types[op].bitfield.disp16 = 0;
		4291	i.types[op].bitfield.disp32 = 0;
		4292	i.types[op].bitfield.disp32s = 0;
		4293	i.types[op].bitfield.disp64 = 0;
		4294	i.op[op].disps = 0;
		4295	i.disp_operands--;
		4296	}
		4297	else if (flag_code == CODE_64BIT)
		4298	{
		4299	if (fits_in_signed_long (op_disp))
		4300	{
		4301	i.types[op].bitfield.disp64 = 0;
		4302	i.types[op].bitfield.disp32s = 1;
		4303	}
		4304	if (i.prefix[ADDR_PREFIX]
		4305	&& fits_in_unsigned_long (op_disp))
		4306	i.types[op].bitfield.disp32 = 1;
		4307	}
		4308	if ((i.types[op].bitfield.disp32
		4309	\|\| i.types[op].bitfield.disp32s
		4310	\|\| i.types[op].bitfield.disp16)
		4311	&& fits_in_signed_byte (op_disp))
		4312	i.types[op].bitfield.disp8 = 1;
		4313	}
		4314	else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
		4315	\|\| i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
		4316	{
		4317	fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
		4318	i.op[op].disps, 0, i.reloc[op]);
		4319	i.types[op].bitfield.disp8 = 0;
		4320	i.types[op].bitfield.disp16 = 0;
		4321	i.types[op].bitfield.disp32 = 0;
		4322	i.types[op].bitfield.disp32s = 0;
		4323	i.types[op].bitfield.disp64 = 0;
		4324	}
		4325	else
		4326	/* We only support 64bit displacement on constants. */
		4327	i.types[op].bitfield.disp64 = 0;
		4328	}
		4329	}
		4330
		4331	/* Check if operands are valid for the instruction. */
		4332
		4333	static int
		4334	check_VecOperands (const insn_template *t)
		4335	{
		4336	unsigned int op;
		4337
		4338	/* Without VSIB byte, we can't have a vector register for index. */
		4339	if (!t->opcode_modifier.vecsib
		4340	&& i.index_reg
		4341	&& (i.index_reg->reg_type.bitfield.regxmm
		4342	\|\| i.index_reg->reg_type.bitfield.regymm
		4343	\|\| i.index_reg->reg_type.bitfield.regzmm))
		4344	{
		4345	i.error = unsupported_vector_index_register;
		4346	return 1;
		4347	}
		4348
		4349	/* Check if default mask is allowed. */
		4350	if (t->opcode_modifier.nodefmask
		4351	&& (!i.mask \|\| i.mask->mask->reg_num == 0))
		4352	{
		4353	i.error = no_default_mask;
		4354	return 1;
		4355	}
		4356
		4357	/* For VSIB byte, we need a vector register for index, and all vector
		4358	registers must be distinct. */
		4359	if (t->opcode_modifier.vecsib)
		4360	{
		4361	if (!i.index_reg
		4362	\|\| !((t->opcode_modifier.vecsib == VecSIB128
		4363	&& i.index_reg->reg_type.bitfield.regxmm)
		4364	\|\| (t->opcode_modifier.vecsib == VecSIB256
		4365	&& i.index_reg->reg_type.bitfield.regymm)
		4366	\|\| (t->opcode_modifier.vecsib == VecSIB512
		4367	&& i.index_reg->reg_type.bitfield.regzmm)))
		4368	{
		4369	i.error = invalid_vsib_address;
		4370	return 1;
		4371	}
		4372
		4373	gas_assert (i.reg_operands == 2 \|\| i.mask);
		4374	if (i.reg_operands == 2 && !i.mask)
		4375	{
		4376	gas_assert (i.types[0].bitfield.regxmm
		4377	\|\| i.types[0].bitfield.regymm
		4378	\|\| i.types[0].bitfield.regzmm);
		4379	gas_assert (i.types[2].bitfield.regxmm
		4380	\|\| i.types[2].bitfield.regymm
		4381	\|\| i.types[2].bitfield.regzmm);
		4382	if (operand_check == check_none)
		4383	return 0;
		4384	if (register_number (i.op[0].regs)
		4385	!= register_number (i.index_reg)
		4386	&& register_number (i.op[2].regs)
		4387	!= register_number (i.index_reg)
		4388	&& register_number (i.op[0].regs)
		4389	!= register_number (i.op[2].regs))
		4390	return 0;
		4391	if (operand_check == check_error)
		4392	{
		4393	i.error = invalid_vector_register_set;
		4394	return 1;
		4395	}
		4396	as_warn (_("mask, index, and destination registers should be distinct"));
		4397	}
		4398	}
		4399
		4400	/* Check if broadcast is supported by the instruction and is applied
		4401	to the memory operand. */
		4402	if (i.broadcast)
		4403	{
		4404	int broadcasted_opnd_size;
		4405
		4406	/* Check if specified broadcast is supported in this instruction,
		4407	and it's applied to memory operand of DWORD or QWORD type,
		4408	depending on VecESize. */
		4409	if (i.broadcast->type != t->opcode_modifier.broadcast
		4410	\|\| !i.types[i.broadcast->operand].bitfield.mem
		4411	\|\| (t->opcode_modifier.vecesize == 0
		4412	&& !i.types[i.broadcast->operand].bitfield.dword
		4413	&& !i.types[i.broadcast->operand].bitfield.unspecified)
		4414	\|\| (t->opcode_modifier.vecesize == 1
		4415	&& !i.types[i.broadcast->operand].bitfield.qword
		4416	&& !i.types[i.broadcast->operand].bitfield.unspecified))
		4417	goto bad_broadcast;
		4418
		4419	broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
		4420	if (i.broadcast->type == BROADCAST_1TO16)
		4421	broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
		4422	else if (i.broadcast->type == BROADCAST_1TO8)
		4423	broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
		4424	else
		4425	goto bad_broadcast;
		4426
		4427	if ((broadcasted_opnd_size == 256
		4428	&& !t->operand_types[i.broadcast->operand].bitfield.ymmword)
		4429	\|\| (broadcasted_opnd_size == 512
		4430	&& !t->operand_types[i.broadcast->operand].bitfield.zmmword))
		4431	{
		4432	bad_broadcast:
		4433	i.error = unsupported_broadcast;
		4434	return 1;
		4435	}
		4436	}
		4437	/* If broadcast is supported in this instruction, we need to check if
		4438	operand of one-element size isn't specified without broadcast. */
		4439	else if (t->opcode_modifier.broadcast && i.mem_operands)
		4440	{
		4441	/* Find memory operand. */
		4442	for (op = 0; op < i.operands; op++)
		4443	if (operand_type_check (i.types[op], anymem))
		4444	break;
		4445	gas_assert (op < i.operands);
		4446	/* Check size of the memory operand. */
		4447	if ((t->opcode_modifier.vecesize == 0
		4448	&& i.types[op].bitfield.dword)
		4449	\|\| (t->opcode_modifier.vecesize == 1
		4450	&& i.types[op].bitfield.qword))
		4451	{
		4452	i.error = broadcast_needed;
		4453	return 1;
		4454	}
		4455	}
		4456
		4457	/* Check if requested masking is supported. */
		4458	if (i.mask
		4459	&& (!t->opcode_modifier.masking
		4460	\|\| (i.mask->zeroing
		4461	&& t->opcode_modifier.masking == MERGING_MASKING)))
		4462	{
		4463	i.error = unsupported_masking;
		4464	return 1;
		4465	}
		4466
		4467	/* Check if masking is applied to dest operand. */
		4468	if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
		4469	{
		4470	i.error = mask_not_on_destination;
		4471	return 1;
		4472	}
		4473
		4474	/* Check RC/SAE. */
		4475	if (i.rounding)
		4476	{
		4477	if ((i.rounding->type != saeonly
		4478	&& !t->opcode_modifier.staticrounding)
		4479	\|\| (i.rounding->type == saeonly
		4480	&& (t->opcode_modifier.staticrounding
		4481	\|\| !t->opcode_modifier.sae)))
		4482	{
		4483	i.error = unsupported_rc_sae;
		4484	return 1;
		4485	}
		4486	/* If the instruction has several immediate operands and one of
		4487	them is rounding, the rounding operand should be the last
		4488	immediate operand. */
		4489	if (i.imm_operands > 1
		4490	&& i.rounding->operand != (int) (i.imm_operands - 1))
		4491	{
		4492	i.error = rc_sae_operand_not_last_imm;
		4493	return 1;
		4494	}
		4495	}
		4496
		4497	/* Check vector Disp8 operand. */
		4498	if (t->opcode_modifier.disp8memshift)
		4499	{
		4500	if (i.broadcast)
		4501	i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
		4502	else
		4503	i.memshift = t->opcode_modifier.disp8memshift;
		4504
		4505	for (op = 0; op < i.operands; op++)
		4506	if (operand_type_check (i.types[op], disp)
		4507	&& i.op[op].disps->X_op == O_constant)
		4508	{
		4509	offsetT value = i.op[op].disps->X_add_number;
		4510	int vec_disp8_ok = fits_in_vec_disp8 (value);
		4511	if (t->operand_types [op].bitfield.vec_disp8)
		4512	{
		4513	if (vec_disp8_ok)
		4514	i.types[op].bitfield.vec_disp8 = 1;
		4515	else
		4516	{
		4517	/* Vector insn can only have Vec_Disp8/Disp32 in
		4518	32/64bit modes, and Vec_Disp8/Disp16 in 16bit
		4519	mode. */
		4520	i.types[op].bitfield.disp8 = 0;
		4521	if (flag_code != CODE_16BIT)
		4522	i.types[op].bitfield.disp16 = 0;
		4523	}
		4524	}
		4525	else if (flag_code != CODE_16BIT)
		4526	{
		4527	/* One form of this instruction supports vector Disp8.
		4528	Try vector Disp8 if we need to use Disp32. */
		4529	if (vec_disp8_ok && !fits_in_signed_byte (value))
		4530	{
		4531	i.error = try_vector_disp8;
		4532	return 1;
		4533	}
		4534	}
		4535	}
		4536	}
		4537	else
		4538	i.memshift = -1;
		4539
		4540	return 0;
		4541	}
		4542
		4543	/* Check if operands are valid for the instruction. Update VEX
		4544	operand types. */
		4545
		4546	static int
		4547	VEX_check_operands (const insn_template *t)
		4548	{
		4549	/* VREX is only valid with EVEX prefix. */
		4550	if (i.need_vrex && !t->opcode_modifier.evex)
		4551	{
		4552	i.error = invalid_register_operand;
		4553	return 1;
		4554	}
		4555
		4556	if (!t->opcode_modifier.vex)
		4557	return 0;
		4558
		4559	/* Only check VEX_Imm4, which must be the first operand. */
		4560	if (t->operand_types[0].bitfield.vec_imm4)
		4561	{
		4562	if (i.op[0].imms->X_op != O_constant
		4563	\|\| !fits_in_imm4 (i.op[0].imms->X_add_number))
		4564	{
		4565	i.error = bad_imm4;
		4566	return 1;
		4567	}
		4568
		4569	/* Turn off Imm8 so that update_imm won't complain. */
		4570	i.types[0] = vec_imm4;
		4571	}
		4572
		4573	return 0;
		4574	}
		4575
		4576	static const insn_template *
		4577	match_template (void)
		4578	{
		4579	/* Points to template once we've found it. */
		4580	const insn_template *t;
		4581	i386_operand_type overlap0, overlap1, overlap2, overlap3;
		4582	i386_operand_type overlap4;
		4583	unsigned int found_reverse_match;
		4584	i386_opcode_modifier suffix_check;
		4585	i386_operand_type operand_types [MAX_OPERANDS];
		4586	int addr_prefix_disp;
		4587	unsigned int j;
		4588	unsigned int found_cpu_match;
		4589	unsigned int check_register;
		4590	enum i386_error specific_error = 0;
		4591
		4592	#if MAX_OPERANDS != 5
		4593	# error "MAX_OPERANDS must be 5."
		4594	#endif
		4595
		4596	found_reverse_match = 0;
		4597	addr_prefix_disp = -1;
		4598
		4599	memset (&suffix_check, 0, sizeof (suffix_check));
		4600	if (i.suffix == BYTE_MNEM_SUFFIX)
		4601	suffix_check.no_bsuf = 1;
		4602	else if (i.suffix == WORD_MNEM_SUFFIX)
		4603	suffix_check.no_wsuf = 1;
		4604	else if (i.suffix == SHORT_MNEM_SUFFIX)
		4605	suffix_check.no_ssuf = 1;
		4606	else if (i.suffix == LONG_MNEM_SUFFIX)
		4607	suffix_check.no_lsuf = 1;
		4608	else if (i.suffix == QWORD_MNEM_SUFFIX)
		4609	suffix_check.no_qsuf = 1;
		4610	else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
		4611	suffix_check.no_ldsuf = 1;
		4612
		4613	/* Must have right number of operands. */
		4614	i.error = number_of_operands_mismatch;
		4615
		4616	for (t = current_templates->start; t < current_templates->end; t++)
		4617	{
		4618	addr_prefix_disp = -1;
		4619
		4620	if (i.operands != t->operands)
		4621	continue;
		4622
		4623	/* Check processor support. */
		4624	i.error = unsupported;
		4625	found_cpu_match = (cpu_flags_match (t)
		4626	== CPU_FLAGS_PERFECT_MATCH);
		4627	if (!found_cpu_match)
		4628	continue;
		4629
		4630	/* Check old gcc support. */
		4631	i.error = old_gcc_only;
		4632	if (!old_gcc && t->opcode_modifier.oldgcc)
		4633	continue;
		4634
		4635	/* Check AT&T mnemonic. */
		4636	i.error = unsupported_with_intel_mnemonic;
		4637	if (intel_mnemonic && t->opcode_modifier.attmnemonic)
		4638	continue;
		4639
		4640	/* Check AT&T/Intel syntax. */
		4641	i.error = unsupported_syntax;
		4642	if ((intel_syntax && t->opcode_modifier.attsyntax)
		4643	\|\| (!intel_syntax && t->opcode_modifier.intelsyntax))
		4644	continue;
		4645
		4646	/* Check the suffix, except for some instructions in intel mode. */
		4647	i.error = invalid_instruction_suffix;
		4648	if ((!intel_syntax \|\| !t->opcode_modifier.ignoresize)
		4649	&& ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
		4650	\|\| (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
		4651	\|\| (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
		4652	\|\| (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
		4653	\|\| (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
		4654	\|\| (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
		4655	continue;
		4656
		4657	if (!operand_size_match (t))
		4658	continue;
		4659
		4660	for (j = 0; j < MAX_OPERANDS; j++)
		4661	operand_types[j] = t->operand_types[j];
		4662
		4663	/* In general, don't allow 64-bit operands in 32-bit mode. */
		4664	if (i.suffix == QWORD_MNEM_SUFFIX
		4665	&& flag_code != CODE_64BIT
		4666	&& (intel_syntax
		4667	? (!t->opcode_modifier.ignoresize
		4668	&& !intel_float_operand (t->name))
		4669	: intel_float_operand (t->name) != 2)
		4670	&& ((!operand_types[0].bitfield.regmmx
		4671	&& !operand_types[0].bitfield.regxmm
		4672	&& !operand_types[0].bitfield.regymm
		4673	&& !operand_types[0].bitfield.regzmm)
		4674	\|\| (!operand_types[t->operands > 1].bitfield.regmmx
		4675	&& !!operand_types[t->operands > 1].bitfield.regxmm
		4676	&& !!operand_types[t->operands > 1].bitfield.regymm
		4677	&& !!operand_types[t->operands > 1].bitfield.regzmm))
		4678	&& (t->base_opcode != 0x0fc7
		4679	\|\| t->extension_opcode != 1 /* cmpxchg8b */))
		4680	continue;
		4681
		4682	/* In general, don't allow 32-bit operands on pre-386. */
		4683	else if (i.suffix == LONG_MNEM_SUFFIX
		4684	&& !cpu_arch_flags.bitfield.cpui386
		4685	&& (intel_syntax
		4686	? (!t->opcode_modifier.ignoresize
		4687	&& !intel_float_operand (t->name))
		4688	: intel_float_operand (t->name) != 2)
		4689	&& ((!operand_types[0].bitfield.regmmx
		4690	&& !operand_types[0].bitfield.regxmm)
		4691	\|\| (!operand_types[t->operands > 1].bitfield.regmmx
		4692	&& !!operand_types[t->operands > 1].bitfield.regxmm)))
		4693	continue;
		4694
		4695	/* Do not verify operands when there are none. */
		4696	else
		4697	{
		4698	if (!t->operands)
		4699	/* We've found a match; break out of loop. */
		4700	break;
		4701	}
		4702
		4703	/* Address size prefix will turn Disp64/Disp32/Disp16 operand
		4704	into Disp32/Disp16/Disp32 operand. */
		4705	if (i.prefix[ADDR_PREFIX] != 0)
		4706	{
		4707	/* There should be only one Disp operand. */
		4708	switch (flag_code)
		4709	{
		4710	case CODE_16BIT:
		4711	for (j = 0; j < MAX_OPERANDS; j++)
		4712	{
		4713	if (operand_types[j].bitfield.disp16)
		4714	{
		4715	addr_prefix_disp = j;
		4716	operand_types[j].bitfield.disp32 = 1;
		4717	operand_types[j].bitfield.disp16 = 0;
		4718	break;
		4719	}
		4720	}
		4721	break;
		4722	case CODE_32BIT:
		4723	for (j = 0; j < MAX_OPERANDS; j++)
		4724	{
		4725	if (operand_types[j].bitfield.disp32)
		4726	{
		4727	addr_prefix_disp = j;
		4728	operand_types[j].bitfield.disp32 = 0;
		4729	operand_types[j].bitfield.disp16 = 1;
		4730	break;
		4731	}
		4732	}
		4733	break;
		4734	case CODE_64BIT:
		4735	for (j = 0; j < MAX_OPERANDS; j++)
		4736	{
		4737	if (operand_types[j].bitfield.disp64)
		4738	{
		4739	addr_prefix_disp = j;
		4740	operand_types[j].bitfield.disp64 = 0;
		4741	operand_types[j].bitfield.disp32 = 1;
		4742	break;
		4743	}
		4744	}
		4745	break;
		4746	}
		4747	}
		4748
		4749	/* We check register size if needed. */
		4750	check_register = t->opcode_modifier.checkregsize;
		4751	overlap0 = operand_type_and (i.types[0], operand_types[0]);
		4752	switch (t->operands)
		4753	{
		4754	case 1:
		4755	if (!operand_type_match (overlap0, i.types[0]))
		4756	continue;
		4757	break;
		4758	case 2:
		4759	/* xchg %eax, %eax is a special case. It is an aliase for nop
		4760	only in 32bit mode and we can use opcode 0x90. In 64bit
		4761	mode, we can't use 0x90 for xchg %eax, %eax since it should
		4762	zero-extend %eax to %rax. */
		4763	if (flag_code == CODE_64BIT
		4764	&& t->base_opcode == 0x90
		4765	&& operand_type_equal (&i.types [0], &acc32)
		4766	&& operand_type_equal (&i.types [1], &acc32))
		4767	continue;
		4768	if (i.swap_operand)
		4769	{
		4770	/* If we swap operand in encoding, we either match
		4771	the next one or reverse direction of operands. */
		4772	if (t->opcode_modifier.s)
		4773	continue;
		4774	else if (t->opcode_modifier.d)
		4775	goto check_reverse;
		4776	}
		4777
		4778	case 3:
		4779	/* If we swap operand in encoding, we match the next one. */
		4780	if (i.swap_operand && t->opcode_modifier.s)
		4781	continue;
		4782	case 4:
		4783	case 5:
		4784	overlap1 = operand_type_and (i.types[1], operand_types[1]);
		4785	if (!operand_type_match (overlap0, i.types[0])
		4786	\|\| !operand_type_match (overlap1, i.types[1])
		4787	\|\| (check_register
		4788	&& !operand_type_register_match (overlap0, i.types[0],
		4789	operand_types[0],
		4790	overlap1, i.types[1],
		4791	operand_types[1])))
		4792	{
		4793	/* Check if other direction is valid ... */
		4794	if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
		4795	continue;
		4796
		4797	check_reverse:
		4798	/* Try reversing direction of operands. */
		4799	overlap0 = operand_type_and (i.types[0], operand_types[1]);
		4800	overlap1 = operand_type_and (i.types[1], operand_types[0]);
		4801	if (!operand_type_match (overlap0, i.types[0])
		4802	\|\| !operand_type_match (overlap1, i.types[1])
		4803	\|\| (check_register
		4804	&& !operand_type_register_match (overlap0,
		4805	i.types[0],
		4806	operand_types[1],
		4807	overlap1,
		4808	i.types[1],
		4809	operand_types[0])))
		4810	{
		4811	/* Does not match either direction. */
		4812	continue;
		4813	}
		4814	/* found_reverse_match holds which of D or FloatDR
		4815	we've found. */
		4816	if (t->opcode_modifier.d)
		4817	found_reverse_match = Opcode_D;
		4818	else if (t->opcode_modifier.floatd)
		4819	found_reverse_match = Opcode_FloatD;
		4820	else
		4821	found_reverse_match = 0;
		4822	if (t->opcode_modifier.floatr)
		4823	found_reverse_match \|= Opcode_FloatR;
		4824	}
		4825	else
		4826	{
		4827	/* Found a forward 2 operand match here. */
		4828	switch (t->operands)
		4829	{
		4830	case 5:
		4831	overlap4 = operand_type_and (i.types[4],
		4832	operand_types[4]);
		4833	case 4:
		4834	overlap3 = operand_type_and (i.types[3],
		4835	operand_types[3]);
		4836	case 3:
		4837	overlap2 = operand_type_and (i.types[2],
		4838	operand_types[2]);
		4839	break;
		4840	}
		4841
		4842	switch (t->operands)
		4843	{
		4844	case 5:
		4845	if (!operand_type_match (overlap4, i.types[4])
		4846	\|\| !operand_type_register_match (overlap3,
		4847	i.types[3],
		4848	operand_types[3],
		4849	overlap4,
		4850	i.types[4],
		4851	operand_types[4]))
		4852	continue;
		4853	case 4:
		4854	if (!operand_type_match (overlap3, i.types[3])
		4855	\|\| (check_register
		4856	&& !operand_type_register_match (overlap2,
		4857	i.types[2],
		4858	operand_types[2],
		4859	overlap3,
		4860	i.types[3],
		4861	operand_types[3])))
		4862	continue;
		4863	case 3:
		4864	/* Here we make use of the fact that there are no
		4865	reverse match 3 operand instructions, and all 3
		4866	operand instructions only need to be checked for
		4867	register consistency between operands 2 and 3. */
		4868	if (!operand_type_match (overlap2, i.types[2])
		4869	\|\| (check_register
		4870	&& !operand_type_register_match (overlap1,
		4871	i.types[1],
		4872	operand_types[1],
		4873	overlap2,
		4874	i.types[2],
		4875	operand_types[2])))
		4876	continue;
		4877	break;
		4878	}
		4879	}
		4880	/* Found either forward/reverse 2, 3 or 4 operand match here:
		4881	slip through to break. */
		4882	}
		4883	if (!found_cpu_match)
		4884	{
		4885	found_reverse_match = 0;
		4886	continue;
		4887	}
		4888
		4889	/* Check if vector and VEX operands are valid. */
		4890	if (check_VecOperands (t) \|\| VEX_check_operands (t))
		4891	{
		4892	specific_error = i.error;
		4893	continue;
		4894	}
		4895
		4896	/* We've found a match; break out of loop. */
		4897	break;
		4898	}
		4899
		4900	if (t == current_templates->end)
		4901	{
		4902	/* We found no match. */
		4903	const char *err_msg;
		4904	switch (specific_error ? specific_error : i.error)
		4905	{
		4906	default:
		4907	abort ();
		4908	case operand_size_mismatch:
		4909	err_msg = _("operand size mismatch");
		4910	break;
		4911	case operand_type_mismatch:
		4912	err_msg = _("operand type mismatch");
		4913	break;
		4914	case register_type_mismatch:
		4915	err_msg = _("register type mismatch");
		4916	break;
		4917	case number_of_operands_mismatch:
		4918	err_msg = _("number of operands mismatch");
		4919	break;
		4920	case invalid_instruction_suffix:
		4921	err_msg = _("invalid instruction suffix");
		4922	break;
		4923	case bad_imm4:
		4924	err_msg = _("constant doesn't fit in 4 bits");
		4925	break;
		4926	case old_gcc_only:
		4927	err_msg = _("only supported with old gcc");
		4928	break;
		4929	case unsupported_with_intel_mnemonic:
		4930	err_msg = _("unsupported with Intel mnemonic");
		4931	break;
		4932	case unsupported_syntax:
		4933	err_msg = _("unsupported syntax");
		4934	break;
		4935	case unsupported:
		4936	as_bad (_("unsupported instruction `%s'"),
		4937	current_templates->start->name);
		4938	return NULL;
		4939	case invalid_vsib_address:
		4940	err_msg = _("invalid VSIB address");
		4941	break;
		4942	case invalid_vector_register_set:
		4943	err_msg = _("mask, index, and destination registers must be distinct");
		4944	break;
		4945	case unsupported_vector_index_register:
		4946	err_msg = _("unsupported vector index register");
		4947	break;
		4948	case unsupported_broadcast:
		4949	err_msg = _("unsupported broadcast");
		4950	break;
		4951	case broadcast_not_on_src_operand:
		4952	err_msg = _("broadcast not on source memory operand");
		4953	break;
		4954	case broadcast_needed:
		4955	err_msg = _("broadcast is needed for operand of such type");
		4956	break;
		4957	case unsupported_masking:
		4958	err_msg = _("unsupported masking");
		4959	break;
		4960	case mask_not_on_destination:
		4961	err_msg = _("mask not on destination operand");
		4962	break;
		4963	case no_default_mask:
		4964	err_msg = _("default mask isn't allowed");
		4965	break;
		4966	case unsupported_rc_sae:
		4967	err_msg = _("unsupported static rounding/sae");
		4968	break;
		4969	case rc_sae_operand_not_last_imm:
		4970	if (intel_syntax)
		4971	err_msg = _("RC/SAE operand must precede immediate operands");
		4972	else
		4973	err_msg = _("RC/SAE operand must follow immediate operands");
		4974	break;
		4975	case invalid_register_operand:
		4976	err_msg = _("invalid register operand");
		4977	break;
		4978	}
		4979	as_bad (_("%s for `%s'"), err_msg,
		4980	current_templates->start->name);
		4981	return NULL;
		4982	}
		4983
		4984	if (!quiet_warnings)
		4985	{
		4986	if (!intel_syntax
		4987	&& (i.types[0].bitfield.jumpabsolute
		4988	!= operand_types[0].bitfield.jumpabsolute))
		4989	{
		4990	as_warn (_("indirect %s without `*'"), t->name);
		4991	}
		4992
		4993	if (t->opcode_modifier.isprefix
		4994	&& t->opcode_modifier.ignoresize)
		4995	{
		4996	/* Warn them that a data or address size prefix doesn't
		4997	affect assembly of the next line of code. */
		4998	as_warn (_("stand-alone `%s' prefix"), t->name);
		4999	}
		5000	}
		5001
		5002	/* Copy the template we found. */
		5003	i.tm = *t;
		5004
		5005	if (addr_prefix_disp != -1)
		5006	i.tm.operand_types[addr_prefix_disp]
		5007	= operand_types[addr_prefix_disp];
		5008
		5009	if (found_reverse_match)
		5010	{
		5011	/* If we found a reverse match we must alter the opcode
		5012	direction bit. found_reverse_match holds bits to change
		5013	(different for int & float insns). */
		5014
		5015	i.tm.base_opcode ^= found_reverse_match;
		5016
		5017	i.tm.operand_types[0] = operand_types[1];
		5018	i.tm.operand_types[1] = operand_types[0];
		5019	}
		5020
		5021	return t;
		5022	}
		5023
		5024	static int
		5025	check_string (void)
		5026	{
		5027	int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
		5028	if (i.tm.operand_types[mem_op].bitfield.esseg)
		5029	{
		5030	if (i.seg[0] != NULL && i.seg[0] != &es)
		5031	{
		5032	as_bad (_("`%s' operand %d must use `%ses' segment"),
		5033	i.tm.name,
		5034	mem_op + 1,
		5035	register_prefix);
		5036	return 0;
		5037	}
		5038	/* There's only ever one segment override allowed per instruction.
		5039	This instruction possibly has a legal segment override on the
		5040	second operand, so copy the segment to where non-string
		5041	instructions store it, allowing common code. */
		5042	i.seg[0] = i.seg[1];
		5043	}
		5044	else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
		5045	{
		5046	if (i.seg[1] != NULL && i.seg[1] != &es)
		5047	{
		5048	as_bad (_("`%s' operand %d must use `%ses' segment"),
		5049	i.tm.name,
		5050	mem_op + 2,
		5051	register_prefix);
		5052	return 0;
		5053	}
		5054	}
		5055	return 1;
		5056	}
		5057
		5058	static int
		5059	process_suffix (void)
		5060	{
		5061	/* If matched instruction specifies an explicit instruction mnemonic
		5062	suffix, use it. */
		5063	if (i.tm.opcode_modifier.size16)
		5064	i.suffix = WORD_MNEM_SUFFIX;
		5065	else if (i.tm.opcode_modifier.size32)
		5066	i.suffix = LONG_MNEM_SUFFIX;
		5067	else if (i.tm.opcode_modifier.size64)
		5068	i.suffix = QWORD_MNEM_SUFFIX;
		5069	else if (i.reg_operands)
		5070	{
		5071	/* If there's no instruction mnemonic suffix we try to invent one
		5072	based on register operands. */
		5073	if (!i.suffix)
		5074	{
		5075	/* We take i.suffix from the last register operand specified,
		5076	Destination register type is more significant than source
		5077	register type. crc32 in SSE4.2 prefers source register
		5078	type. */
		5079	if (i.tm.base_opcode == 0xf20f38f1)
		5080	{
		5081	if (i.types[0].bitfield.reg16)
		5082	i.suffix = WORD_MNEM_SUFFIX;
		5083	else if (i.types[0].bitfield.reg32)
		5084	i.suffix = LONG_MNEM_SUFFIX;
		5085	else if (i.types[0].bitfield.reg64)
		5086	i.suffix = QWORD_MNEM_SUFFIX;
		5087	}
		5088	else if (i.tm.base_opcode == 0xf20f38f0)
		5089	{
		5090	if (i.types[0].bitfield.reg8)
		5091	i.suffix = BYTE_MNEM_SUFFIX;
		5092	}
		5093
		5094	if (!i.suffix)
		5095	{
		5096	int op;
		5097
		5098	if (i.tm.base_opcode == 0xf20f38f1
		5099	\|\| i.tm.base_opcode == 0xf20f38f0)
		5100	{
		5101	/* We have to know the operand size for crc32. */
		5102	as_bad (_("ambiguous memory operand size for `%s`"),
		5103	i.tm.name);
		5104	return 0;
		5105	}
		5106
		5107	for (op = i.operands; --op >= 0;)
		5108	if (!i.tm.operand_types[op].bitfield.inoutportreg)
		5109	{
		5110	if (i.types[op].bitfield.reg8)
		5111	{
		5112	i.suffix = BYTE_MNEM_SUFFIX;
		5113	break;
		5114	}
		5115	else if (i.types[op].bitfield.reg16)
		5116	{
		5117	i.suffix = WORD_MNEM_SUFFIX;
		5118	break;
		5119	}
		5120	else if (i.types[op].bitfield.reg32)
		5121	{
		5122	i.suffix = LONG_MNEM_SUFFIX;
		5123	break;
		5124	}
		5125	else if (i.types[op].bitfield.reg64)
		5126	{
		5127	i.suffix = QWORD_MNEM_SUFFIX;
		5128	break;
		5129	}
		5130	}
		5131	}
		5132	}
		5133	else if (i.suffix == BYTE_MNEM_SUFFIX)
		5134	{
		5135	if (intel_syntax
		5136	&& i.tm.opcode_modifier.ignoresize
		5137	&& i.tm.opcode_modifier.no_bsuf)
		5138	i.suffix = 0;
		5139	else if (!check_byte_reg ())
		5140	return 0;
		5141	}
		5142	else if (i.suffix == LONG_MNEM_SUFFIX)
		5143	{
		5144	if (intel_syntax
		5145	&& i.tm.opcode_modifier.ignoresize
		5146	&& i.tm.opcode_modifier.no_lsuf)
		5147	i.suffix = 0;
		5148	else if (!check_long_reg ())
		5149	return 0;
		5150	}
		5151	else if (i.suffix == QWORD_MNEM_SUFFIX)
		5152	{
		5153	if (intel_syntax
		5154	&& i.tm.opcode_modifier.ignoresize
		5155	&& i.tm.opcode_modifier.no_qsuf)
		5156	i.suffix = 0;
		5157	else if (!check_qword_reg ())
		5158	return 0;
		5159	}
		5160	else if (i.suffix == WORD_MNEM_SUFFIX)
		5161	{
		5162	if (intel_syntax
		5163	&& i.tm.opcode_modifier.ignoresize
		5164	&& i.tm.opcode_modifier.no_wsuf)
		5165	i.suffix = 0;
		5166	else if (!check_word_reg ())
		5167	return 0;
		5168	}
		5169	else if (i.suffix == XMMWORD_MNEM_SUFFIX
		5170	\|\| i.suffix == YMMWORD_MNEM_SUFFIX
		5171	\|\| i.suffix == ZMMWORD_MNEM_SUFFIX)
		5172	{
		5173	/* Skip if the instruction has x/y/z suffix. match_template
		5174	should check if it is a valid suffix. */
		5175	}
		5176	else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
		5177	/* Do nothing if the instruction is going to ignore the prefix. */
		5178	;
		5179	else
		5180	abort ();
		5181	}
		5182	else if (i.tm.opcode_modifier.defaultsize
		5183	&& !i.suffix
		5184	/* exclude fldenv/frstor/fsave/fstenv */
		5185	&& i.tm.opcode_modifier.no_ssuf)
		5186	{
		5187	i.suffix = stackop_size;
		5188	}
		5189	else if (intel_syntax
		5190	&& !i.suffix
		5191	&& (i.tm.operand_types[0].bitfield.jumpabsolute
		5192	\|\| i.tm.opcode_modifier.jumpbyte
		5193	\|\| i.tm.opcode_modifier.jumpintersegment
		5194	\|\| (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
		5195	&& i.tm.extension_opcode <= 3)))
		5196	{
		5197	switch (flag_code)
		5198	{
		5199	case CODE_64BIT:
		5200	if (!i.tm.opcode_modifier.no_qsuf)
		5201	{
		5202	i.suffix = QWORD_MNEM_SUFFIX;
		5203	break;
		5204	}
		5205	case CODE_32BIT:
		5206	if (!i.tm.opcode_modifier.no_lsuf)
		5207	i.suffix = LONG_MNEM_SUFFIX;
		5208	break;
		5209	case CODE_16BIT:
		5210	if (!i.tm.opcode_modifier.no_wsuf)
		5211	i.suffix = WORD_MNEM_SUFFIX;
		5212	break;
		5213	}
		5214	}
		5215
		5216	if (!i.suffix)
		5217	{
		5218	if (!intel_syntax)
		5219	{
		5220	if (i.tm.opcode_modifier.w)
		5221	{
		5222	as_bad (_("no instruction mnemonic suffix given and "
		5223	"no register operands; can't size instruction"));
		5224	return 0;
		5225	}
		5226	}
		5227	else
		5228	{
		5229	unsigned int suffixes;
		5230
		5231	suffixes = !i.tm.opcode_modifier.no_bsuf;
		5232	if (!i.tm.opcode_modifier.no_wsuf)
		5233	suffixes \|= 1 << 1;
		5234	if (!i.tm.opcode_modifier.no_lsuf)
		5235	suffixes \|= 1 << 2;
		5236	if (!i.tm.opcode_modifier.no_ldsuf)
		5237	suffixes \|= 1 << 3;
		5238	if (!i.tm.opcode_modifier.no_ssuf)
		5239	suffixes \|= 1 << 4;
		5240	if (!i.tm.opcode_modifier.no_qsuf)
		5241	suffixes \|= 1 << 5;
		5242
		5243	/* There are more than suffix matches. */
		5244	if (i.tm.opcode_modifier.w
		5245	\|\| ((suffixes & (suffixes - 1))
		5246	&& !i.tm.opcode_modifier.defaultsize
		5247	&& !i.tm.opcode_modifier.ignoresize))
		5248	{
		5249	as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
		5250	return 0;
		5251	}
		5252	}
		5253	}
		5254
		5255	/* Change the opcode based on the operand size given by i.suffix;
		5256	We don't need to change things for byte insns. */
		5257
		5258	if (i.suffix
		5259	&& i.suffix != BYTE_MNEM_SUFFIX
		5260	&& i.suffix != XMMWORD_MNEM_SUFFIX
		5261	&& i.suffix != YMMWORD_MNEM_SUFFIX
		5262	&& i.suffix != ZMMWORD_MNEM_SUFFIX)
		5263	{
		5264	/* It's not a byte, select word/dword operation. */
		5265	if (i.tm.opcode_modifier.w)
		5266	{
		5267	if (i.tm.opcode_modifier.shortform)
		5268	i.tm.base_opcode \|= 8;
		5269	else
		5270	i.tm.base_opcode \|= 1;
		5271	}
		5272
		5273	/* Now select between word & dword operations via the operand
		5274	size prefix, except for instructions that will ignore this
		5275	prefix anyway. */
		5276	if (i.tm.opcode_modifier.addrprefixop0)
		5277	{
		5278	/* The address size override prefix changes the size of the
		5279	first operand. */
		5280	if ((flag_code == CODE_32BIT
		5281	&& i.op->regs[0].reg_type.bitfield.reg16)
		5282	\|\| (flag_code != CODE_32BIT
		5283	&& i.op->regs[0].reg_type.bitfield.reg32))
		5284	if (!add_prefix (ADDR_PREFIX_OPCODE))
		5285	return 0;
		5286	}
		5287	else if (i.suffix != QWORD_MNEM_SUFFIX
		5288	&& i.suffix != LONG_DOUBLE_MNEM_SUFFIX
		5289	&& !i.tm.opcode_modifier.ignoresize
		5290	&& !i.tm.opcode_modifier.floatmf
		5291	&& ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
		5292	\|\| (flag_code == CODE_64BIT
		5293	&& i.tm.opcode_modifier.jumpbyte)))
		5294	{
		5295	unsigned int prefix = DATA_PREFIX_OPCODE;
		5296
		5297	if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
		5298	prefix = ADDR_PREFIX_OPCODE;
		5299
		5300	if (!add_prefix (prefix))
		5301	return 0;
		5302	}
		5303
		5304	/* Set mode64 for an operand. */
		5305	if (i.suffix == QWORD_MNEM_SUFFIX
		5306	&& flag_code == CODE_64BIT
		5307	&& !i.tm.opcode_modifier.norex64)
		5308	{
		5309	/* Special case for xchg %rax,%rax. It is NOP and doesn't
		5310	need rex64. cmpxchg8b is also a special case. */
		5311	if (! (i.operands == 2
		5312	&& i.tm.base_opcode == 0x90
		5313	&& i.tm.extension_opcode == None
		5314	&& operand_type_equal (&i.types [0], &acc64)
		5315	&& operand_type_equal (&i.types [1], &acc64))
		5316	&& ! (i.operands == 1
		5317	&& i.tm.base_opcode == 0xfc7
		5318	&& i.tm.extension_opcode == 1
		5319	&& !operand_type_check (i.types [0], reg)
		5320	&& operand_type_check (i.types [0], anymem)))
		5321	i.rex \|= REX_W;
		5322	}
		5323
		5324	/* Size floating point instruction. */
		5325	if (i.suffix == LONG_MNEM_SUFFIX)
		5326	if (i.tm.opcode_modifier.floatmf)
		5327	i.tm.base_opcode ^= 4;
		5328	}
		5329
		5330	return 1;
		5331	}
		5332
		5333	static int
		5334	check_byte_reg (void)
		5335	{
		5336	int op;
		5337
		5338	for (op = i.operands; --op >= 0;)
		5339	{
		5340	/* If this is an eight bit register, it's OK. If it's the 16 or
		5341	32 bit version of an eight bit register, we will just use the
		5342	low portion, and that's OK too. */
		5343	if (i.types[op].bitfield.reg8)
		5344	continue;
		5345
		5346	/* I/O port address operands are OK too. */
		5347	if (i.tm.operand_types[op].bitfield.inoutportreg)
		5348	continue;
		5349
		5350	/* crc32 doesn't generate this warning. */
		5351	if (i.tm.base_opcode == 0xf20f38f0)
		5352	continue;
		5353
		5354	if ((i.types[op].bitfield.reg16
		5355	\|\| i.types[op].bitfield.reg32
		5356	\|\| i.types[op].bitfield.reg64)
		5357	&& i.op[op].regs->reg_num < 4
		5358	/* Prohibit these changes in 64bit mode, since the lowering
		5359	would be more complicated. */
		5360	&& flag_code != CODE_64BIT)
		5361	{
		5362	#if REGISTER_WARNINGS
		5363	if (!quiet_warnings)
		5364	as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
		5365	register_prefix,
		5366	(i.op[op].regs + (i.types[op].bitfield.reg16
		5367	? REGNAM_AL - REGNAM_AX
		5368	: REGNAM_AL - REGNAM_EAX))->reg_name,
		5369	register_prefix,
		5370	i.op[op].regs->reg_name,
		5371	i.suffix);
		5372	#endif
		5373	continue;
		5374	}
		5375	/* Any other register is bad. */
		5376	if (i.types[op].bitfield.reg16
		5377	\|\| i.types[op].bitfield.reg32
		5378	\|\| i.types[op].bitfield.reg64
		5379	\|\| i.types[op].bitfield.regmmx
		5380	\|\| i.types[op].bitfield.regxmm
		5381	\|\| i.types[op].bitfield.regymm
		5382	\|\| i.types[op].bitfield.regzmm
		5383	\|\| i.types[op].bitfield.sreg2
		5384	\|\| i.types[op].bitfield.sreg3
		5385	\|\| i.types[op].bitfield.control
		5386	\|\| i.types[op].bitfield.debug
		5387	\|\| i.types[op].bitfield.test
		5388	\|\| i.types[op].bitfield.floatreg
		5389	\|\| i.types[op].bitfield.floatacc)
		5390	{
		5391	as_bad (_("`%s%s' not allowed with `%s%c'"),
		5392	register_prefix,
		5393	i.op[op].regs->reg_name,
		5394	i.tm.name,
		5395	i.suffix);
		5396	return 0;
		5397	}
		5398	}
		5399	return 1;
		5400	}
		5401
		5402	static int
		5403	check_long_reg (void)
		5404	{
		5405	int op;
		5406
		5407	for (op = i.operands; --op >= 0;)
		5408	/* Reject eight bit registers, except where the template requires
		5409	them. (eg. movzb) */
		5410	if (i.types[op].bitfield.reg8
		5411	&& (i.tm.operand_types[op].bitfield.reg16
		5412	\|\| i.tm.operand_types[op].bitfield.reg32
		5413	\|\| i.tm.operand_types[op].bitfield.acc))
		5414	{
		5415	as_bad (_("`%s%s' not allowed with `%s%c'"),
		5416	register_prefix,
		5417	i.op[op].regs->reg_name,
		5418	i.tm.name,
		5419	i.suffix);
		5420	return 0;
		5421	}
		5422	/* Warn if the e prefix on a general reg is missing. */
		5423	else if ((!quiet_warnings \|\| flag_code == CODE_64BIT)
		5424	&& i.types[op].bitfield.reg16
		5425	&& (i.tm.operand_types[op].bitfield.reg32
		5426	\|\| i.tm.operand_types[op].bitfield.acc))
		5427	{
		5428	/* Prohibit these changes in the 64bit mode, since the
		5429	lowering is more complicated. */
		5430	if (flag_code == CODE_64BIT)
		5431	{
		5432	as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
		5433	register_prefix, i.op[op].regs->reg_name,
		5434	i.suffix);
		5435	return 0;
		5436	}
		5437	#if REGISTER_WARNINGS
		5438	else
		5439	as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
		5440	register_prefix,
		5441	(i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
		5442	register_prefix,
		5443	i.op[op].regs->reg_name,
		5444	i.suffix);
		5445	#endif
		5446	}
		5447	/* Warn if the r prefix on a general reg is missing. */
		5448	else if (i.types[op].bitfield.reg64
		5449	&& (i.tm.operand_types[op].bitfield.reg32
		5450	\|\| i.tm.operand_types[op].bitfield.acc))
		5451	{
		5452	if (intel_syntax
		5453	&& i.tm.opcode_modifier.toqword
		5454	&& !i.types[0].bitfield.regxmm)
		5455	{
		5456	/* Convert to QWORD. We want REX byte. */
		5457	i.suffix = QWORD_MNEM_SUFFIX;
		5458	}
		5459	else
		5460	{
		5461	as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
		5462	register_prefix, i.op[op].regs->reg_name,
		5463	i.suffix);
		5464	return 0;
		5465	}
		5466	}
		5467	return 1;
		5468	}
		5469
		5470	static int
		5471	check_qword_reg (void)
		5472	{
		5473	int op;
		5474
		5475	for (op = i.operands; --op >= 0; )
		5476	/* Reject eight bit registers, except where the template requires
		5477	them. (eg. movzb) */
		5478	if (i.types[op].bitfield.reg8
		5479	&& (i.tm.operand_types[op].bitfield.reg16
		5480	\|\| i.tm.operand_types[op].bitfield.reg32
		5481	\|\| i.tm.operand_types[op].bitfield.acc))
		5482	{
		5483	as_bad (_("`%s%s' not allowed with `%s%c'"),
		5484	register_prefix,
		5485	i.op[op].regs->reg_name,
		5486	i.tm.name,
		5487	i.suffix);
		5488	return 0;
		5489	}
		5490	/* Warn if the e prefix on a general reg is missing. */
		5491	else if ((i.types[op].bitfield.reg16
		5492	\|\| i.types[op].bitfield.reg32)
		5493	&& (i.tm.operand_types[op].bitfield.reg32
		5494	\|\| i.tm.operand_types[op].bitfield.acc))
		5495	{
		5496	/* Prohibit these changes in the 64bit mode, since the
		5497	lowering is more complicated. */
		5498	if (intel_syntax
		5499	&& i.tm.opcode_modifier.todword
		5500	&& !i.types[0].bitfield.regxmm)
		5501	{
		5502	/* Convert to DWORD. We don't want REX byte. */
		5503	i.suffix = LONG_MNEM_SUFFIX;
		5504	}
		5505	else
		5506	{
		5507	as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
		5508	register_prefix, i.op[op].regs->reg_name,
		5509	i.suffix);
		5510	return 0;
		5511	}
		5512	}
		5513	return 1;
		5514	}
		5515
		5516	static int
		5517	check_word_reg (void)
		5518	{
		5519	int op;
		5520	for (op = i.operands; --op >= 0;)
		5521	/* Reject eight bit registers, except where the template requires
		5522	them. (eg. movzb) */
		5523	if (i.types[op].bitfield.reg8
		5524	&& (i.tm.operand_types[op].bitfield.reg16
		5525	\|\| i.tm.operand_types[op].bitfield.reg32
		5526	\|\| i.tm.operand_types[op].bitfield.acc))
		5527	{
		5528	as_bad (_("`%s%s' not allowed with `%s%c'"),
		5529	register_prefix,
		5530	i.op[op].regs->reg_name,
		5531	i.tm.name,
		5532	i.suffix);
		5533	return 0;
		5534	}
		5535	/* Warn if the e prefix on a general reg is present. */
		5536	else if ((!quiet_warnings \|\| flag_code == CODE_64BIT)
		5537	&& i.types[op].bitfield.reg32
		5538	&& (i.tm.operand_types[op].bitfield.reg16
		5539	\|\| i.tm.operand_types[op].bitfield.acc))
		5540	{
		5541	/* Prohibit these changes in the 64bit mode, since the
		5542	lowering is more complicated. */
		5543	if (flag_code == CODE_64BIT)
		5544	{
		5545	as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
		5546	register_prefix, i.op[op].regs->reg_name,
		5547	i.suffix);
		5548	return 0;
		5549	}
		5550	else
		5551	#if REGISTER_WARNINGS
		5552	as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
		5553	register_prefix,
		5554	(i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
		5555	register_prefix,
		5556	i.op[op].regs->reg_name,
		5557	i.suffix);
		5558	#endif
		5559	}
		5560	return 1;
		5561	}
		5562
		5563	static int
		5564	update_imm (unsigned int j)
		5565	{
		5566	i386_operand_type overlap = i.types[j];
		5567	if ((overlap.bitfield.imm8
		5568	\|\| overlap.bitfield.imm8s
		5569	\|\| overlap.bitfield.imm16
		5570	\|\| overlap.bitfield.imm32
		5571	\|\| overlap.bitfield.imm32s
		5572	\|\| overlap.bitfield.imm64)
		5573	&& !operand_type_equal (&overlap, &imm8)
		5574	&& !operand_type_equal (&overlap, &imm8s)
		5575	&& !operand_type_equal (&overlap, &imm16)
		5576	&& !operand_type_equal (&overlap, &imm32)
		5577	&& !operand_type_equal (&overlap, &imm32s)
		5578	&& !operand_type_equal (&overlap, &imm64))
		5579	{
		5580	if (i.suffix)
		5581	{
		5582	i386_operand_type temp;
		5583
		5584	operand_type_set (&temp, 0);
		5585	if (i.suffix == BYTE_MNEM_SUFFIX)
		5586	{
		5587	temp.bitfield.imm8 = overlap.bitfield.imm8;
		5588	temp.bitfield.imm8s = overlap.bitfield.imm8s;
		5589	}
		5590	else if (i.suffix == WORD_MNEM_SUFFIX)
		5591	temp.bitfield.imm16 = overlap.bitfield.imm16;
		5592	else if (i.suffix == QWORD_MNEM_SUFFIX)
		5593	{
		5594	temp.bitfield.imm64 = overlap.bitfield.imm64;
		5595	temp.bitfield.imm32s = overlap.bitfield.imm32s;
		5596	}
		5597	else
		5598	temp.bitfield.imm32 = overlap.bitfield.imm32;
		5599	overlap = temp;
		5600	}
		5601	else if (operand_type_equal (&overlap, &imm16_32_32s)
		5602	\|\| operand_type_equal (&overlap, &imm16_32)
		5603	\|\| operand_type_equal (&overlap, &imm16_32s))
		5604	{
		5605	if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
		5606	overlap = imm16;
		5607	else
		5608	overlap = imm32s;
		5609	}
		5610	if (!operand_type_equal (&overlap, &imm8)
		5611	&& !operand_type_equal (&overlap, &imm8s)
		5612	&& !operand_type_equal (&overlap, &imm16)
		5613	&& !operand_type_equal (&overlap, &imm32)
		5614	&& !operand_type_equal (&overlap, &imm32s)
		5615	&& !operand_type_equal (&overlap, &imm64))
		5616	{
		5617	as_bad (_("no instruction mnemonic suffix given; "
		5618	"can't determine immediate size"));
		5619	return 0;
		5620	}
		5621	}
		5622	i.types[j] = overlap;
		5623
		5624	return 1;
		5625	}
		5626
		5627	static int
		5628	finalize_imm (void)
		5629	{
		5630	unsigned int j, n;
		5631
		5632	/* Update the first 2 immediate operands. */
		5633	n = i.operands > 2 ? 2 : i.operands;
		5634	if (n)
		5635	{
		5636	for (j = 0; j < n; j++)
		5637	if (update_imm (j) == 0)
		5638	return 0;
		5639
		5640	/* The 3rd operand can't be immediate operand. */
		5641	gas_assert (operand_type_check (i.types[2], imm) == 0);
		5642	}
		5643
		5644	return 1;
		5645	}
		5646
		5647	static int
		5648	bad_implicit_operand (int xmm)
		5649	{
		5650	const char *ireg = xmm ? "xmm0" : "ymm0";
		5651
		5652	if (intel_syntax)
		5653	as_bad (_("the last operand of `%s' must be `%s%s'"),
		5654	i.tm.name, register_prefix, ireg);
		5655	else
		5656	as_bad (_("the first operand of `%s' must be `%s%s'"),
		5657	i.tm.name, register_prefix, ireg);
		5658	return 0;
		5659	}
		5660
		5661	static int
		5662	process_operands (void)
		5663	{
		5664	/* Default segment register this instruction will use for memory
		5665	accesses. 0 means unknown. This is only for optimizing out
		5666	unnecessary segment overrides. */
		5667	const seg_entry *default_seg = 0;
		5668
		5669	if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
		5670	{
		5671	unsigned int dupl = i.operands;
		5672	unsigned int dest = dupl - 1;
		5673	unsigned int j;
		5674
		5675	/* The destination must be an xmm register. */
		5676	gas_assert (i.reg_operands
		5677	&& MAX_OPERANDS > dupl
		5678	&& operand_type_equal (&i.types[dest], ®xmm));
		5679
		5680	if (i.tm.opcode_modifier.firstxmm0)
		5681	{
		5682	/* The first operand is implicit and must be xmm0. */
		5683	gas_assert (operand_type_equal (&i.types[0], ®xmm));
		5684	if (register_number (i.op[0].regs) != 0)
		5685	return bad_implicit_operand (1);
		5686
		5687	if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
		5688	{
		5689	/* Keep xmm0 for instructions with VEX prefix and 3
		5690	sources. */
		5691	goto duplicate;
		5692	}
		5693	else
		5694	{
		5695	/* We remove the first xmm0 and keep the number of
		5696	operands unchanged, which in fact duplicates the
		5697	destination. */
		5698	for (j = 1; j < i.operands; j++)
		5699	{
		5700	i.op[j - 1] = i.op[j];
		5701	i.types[j - 1] = i.types[j];
		5702	i.tm.operand_types[j - 1] = i.tm.operand_types[j];
		5703	}
		5704	}
		5705	}
		5706	else if (i.tm.opcode_modifier.implicit1stxmm0)
		5707	{
		5708	gas_assert ((MAX_OPERANDS - 1) > dupl
		5709	&& (i.tm.opcode_modifier.vexsources
		5710	== VEX3SOURCES));
		5711
		5712	/* Add the implicit xmm0 for instructions with VEX prefix
		5713	and 3 sources. */
		5714	for (j = i.operands; j > 0; j--)
		5715	{
		5716	i.op[j] = i.op[j - 1];
		5717	i.types[j] = i.types[j - 1];
		5718	i.tm.operand_types[j] = i.tm.operand_types[j - 1];
		5719	}
		5720	i.op[0].regs
		5721	= (const reg_entry *) hash_find (reg_hash, "xmm0");
		5722	i.types[0] = regxmm;
		5723	i.tm.operand_types[0] = regxmm;
		5724
		5725	i.operands += 2;
		5726	i.reg_operands += 2;
		5727	i.tm.operands += 2;
		5728
		5729	dupl++;
		5730	dest++;
		5731	i.op[dupl] = i.op[dest];
		5732	i.types[dupl] = i.types[dest];
		5733	i.tm.operand_types[dupl] = i.tm.operand_types[dest];
		5734	}
		5735	else
		5736	{
		5737	duplicate:
		5738	i.operands++;
		5739	i.reg_operands++;
		5740	i.tm.operands++;
		5741
		5742	i.op[dupl] = i.op[dest];
		5743	i.types[dupl] = i.types[dest];
		5744	i.tm.operand_types[dupl] = i.tm.operand_types[dest];
		5745	}
		5746
		5747	if (i.tm.opcode_modifier.immext)
		5748	process_immext ();
		5749	}
		5750	else if (i.tm.opcode_modifier.firstxmm0)
		5751	{
		5752	unsigned int j;
		5753
		5754	/* The first operand is implicit and must be xmm0/ymm0/zmm0. */
		5755	gas_assert (i.reg_operands
		5756	&& (operand_type_equal (&i.types[0], ®xmm)
		5757	\|\| operand_type_equal (&i.types[0], ®ymm)
		5758	\|\| operand_type_equal (&i.types[0], ®zmm)));
		5759	if (register_number (i.op[0].regs) != 0)
		5760	return bad_implicit_operand (i.types[0].bitfield.regxmm);
		5761
		5762	for (j = 1; j < i.operands; j++)
		5763	{
		5764	i.op[j - 1] = i.op[j];
		5765	i.types[j - 1] = i.types[j];
		5766
		5767	/* We need to adjust fields in i.tm since they are used by
		5768	build_modrm_byte. */
		5769	i.tm.operand_types [j - 1] = i.tm.operand_types [j];
		5770	}
		5771
		5772	i.operands--;
		5773	i.reg_operands--;
		5774	i.tm.operands--;
		5775	}
		5776	else if (i.tm.opcode_modifier.regkludge)
		5777	{
		5778	/* The imul $imm, %reg instruction is converted into
		5779	imul $imm, %reg, %reg, and the clr %reg instruction
		5780	is converted into xor %reg, %reg. */
		5781
		5782	unsigned int first_reg_op;
		5783
		5784	if (operand_type_check (i.types[0], reg))
		5785	first_reg_op = 0;
		5786	else
		5787	first_reg_op = 1;
		5788	/* Pretend we saw the extra register operand. */
		5789	gas_assert (i.reg_operands == 1
		5790	&& i.op[first_reg_op + 1].regs == 0);
		5791	i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
		5792	i.types[first_reg_op + 1] = i.types[first_reg_op];
		5793	i.operands++;
		5794	i.reg_operands++;
		5795	}
		5796
		5797	if (i.tm.opcode_modifier.shortform)
		5798	{
		5799	if (i.types[0].bitfield.sreg2
		5800	\|\| i.types[0].bitfield.sreg3)
		5801	{
		5802	if (i.tm.base_opcode == POP_SEG_SHORT
		5803	&& i.op[0].regs->reg_num == 1)
		5804	{
		5805	as_bad (_("you can't `pop %scs'"), register_prefix);
		5806	return 0;
		5807	}
		5808	i.tm.base_opcode \|= (i.op[0].regs->reg_num << 3);
		5809	if ((i.op[0].regs->reg_flags & RegRex) != 0)
		5810	i.rex \|= REX_B;
		5811	}
		5812	else
		5813	{
		5814	/* The register or float register operand is in operand
		5815
		5816	unsigned int op;
		5817
		5818	if (i.types[0].bitfield.floatreg
		5819	\|\| operand_type_check (i.types[0], reg))
		5820	op = 0;
		5821	else
		5822	op = 1;
		5823	/* Register goes in low 3 bits of opcode. */
		5824	i.tm.base_opcode \|= i.op[op].regs->reg_num;
		5825	if ((i.op[op].regs->reg_flags & RegRex) != 0)
		5826	i.rex \|= REX_B;
		5827	if (!quiet_warnings && i.tm.opcode_modifier.ugh)
		5828	{
		5829	/* Warn about some common errors, but press on regardless.
		5830	The first case can be generated by gcc (<= 2.8.1). */
		5831	if (i.operands == 2)
		5832	{
		5833	/* Reversed arguments on faddp, fsubp, etc. */
		5834	as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
		5835	register_prefix, i.op[!intel_syntax].regs->reg_name,
		5836	register_prefix, i.op[intel_syntax].regs->reg_name);
		5837	}
		5838	else
		5839	{
		5840	/* Extraneous `l' suffix on fp insn. */
		5841	as_warn (_("translating to `%s %s%s'"), i.tm.name,
		5842	register_prefix, i.op[0].regs->reg_name);
		5843	}
		5844	}
		5845	}
		5846	}
		5847	else if (i.tm.opcode_modifier.modrm)
		5848	{
		5849	/* The opcode is completed (modulo i.tm.extension_opcode which
		5850	must be put into the modrm byte). Now, we make the modrm and
		5851	index base bytes based on all the info we've collected. */
		5852
		5853	default_seg = build_modrm_byte ();
		5854	}
		5855	else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
		5856	{
		5857	default_seg = &ds;
		5858	}
		5859	else if (i.tm.opcode_modifier.isstring)
		5860	{
		5861	/* For the string instructions that allow a segment override
		5862	on one of their operands, the default segment is ds. */
		5863	default_seg = &ds;
		5864	}
		5865
		5866	if (i.tm.base_opcode == 0x8d /* lea */
		5867	&& i.seg[0]
		5868	&& !quiet_warnings)
		5869	as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
		5870
		5871	/* If a segment was explicitly specified, and the specified segment
		5872	is not the default, use an opcode prefix to select it. If we
		5873	never figured out what the default segment is, then default_seg
		5874	will be zero at this point, and the specified segment prefix will
		5875	always be used. */
		5876	if ((i.seg[0]) && (i.seg[0] != default_seg))
		5877	{
		5878	if (!add_prefix (i.seg[0]->seg_prefix))
		5879	return 0;
		5880	}
		5881	return 1;
		5882	}
		5883
		5884	static const seg_entry *
		5885	build_modrm_byte (void)
		5886	{
		5887	const seg_entry *default_seg = 0;
		5888	unsigned int source, dest;
		5889	int vex_3_sources;
		5890
		5891	/* The first operand of instructions with VEX prefix and 3 sources
		5892	must be VEX_Imm4. */
		5893	vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
		5894	if (vex_3_sources)
		5895	{
		5896	unsigned int nds, reg_slot;
		5897	expressionS *exp;
		5898
		5899	if (i.tm.opcode_modifier.veximmext
		5900	&& i.tm.opcode_modifier.immext)
		5901	{
		5902	dest = i.operands - 2;
		5903	gas_assert (dest == 3);
		5904	}
		5905	else
		5906	dest = i.operands - 1;
		5907	nds = dest - 1;
		5908
		5909	/* There are 2 kinds of instructions:
		5910	1. 5 operands: 4 register operands or 3 register operands
		5911	plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
		5912	VexW0 or VexW1. The destination must be either XMM, YMM or
		5913	ZMM register.
		5914	2. 4 operands: 4 register operands or 3 register operands
		5915	plus 1 memory operand, VexXDS, and VexImmExt */
		5916	gas_assert ((i.reg_operands == 4
		5917	\|\| (i.reg_operands == 3 && i.mem_operands == 1))
		5918	&& i.tm.opcode_modifier.vexvvvv == VEXXDS
		5919	&& (i.tm.opcode_modifier.veximmext
		5920	\|\| (i.imm_operands == 1
		5921	&& i.types[0].bitfield.vec_imm4
		5922	&& (i.tm.opcode_modifier.vexw == VEXW0
		5923	\|\| i.tm.opcode_modifier.vexw == VEXW1)
		5924	&& (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
		5925	\|\| operand_type_equal (&i.tm.operand_types[dest], ®ymm)
		5926	\|\| operand_type_equal (&i.tm.operand_types[dest], ®zmm)))));
		5927
		5928	if (i.imm_operands == 0)
		5929	{
		5930	/* When there is no immediate operand, generate an 8bit
		5931	immediate operand to encode the first operand. */
		5932	exp = &im_expressions[i.imm_operands++];
		5933	i.op[i.operands].imms = exp;
		5934	i.types[i.operands] = imm8;
		5935	i.operands++;
		5936	/* If VexW1 is set, the first operand is the source and
		5937	the second operand is encoded in the immediate operand. */
		5938	if (i.tm.opcode_modifier.vexw == VEXW1)
		5939	{
		5940	source = 0;
		5941	reg_slot = 1;
		5942	}
		5943	else
		5944	{
		5945	source = 1;
		5946	reg_slot = 0;
		5947	}
		5948
		5949	/* FMA swaps REG and NDS. */
		5950	if (i.tm.cpu_flags.bitfield.cpufma)
		5951	{
		5952	unsigned int tmp;
		5953	tmp = reg_slot;
		5954	reg_slot = nds;
		5955	nds = tmp;
		5956	}
		5957
		5958	gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
		5959	®xmm)
		5960	\|\| operand_type_equal (&i.tm.operand_types[reg_slot],
		5961	®ymm)
		5962	\|\| operand_type_equal (&i.tm.operand_types[reg_slot],
		5963	®zmm));
		5964	exp->X_op = O_constant;
		5965	exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
		5966	gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
		5967	}
		5968	else
		5969	{
		5970	unsigned int imm_slot;
		5971
		5972	if (i.tm.opcode_modifier.vexw == VEXW0)
		5973	{
		5974	/* If VexW0 is set, the third operand is the source and
		5975	the second operand is encoded in the immediate
		5976	operand. */
		5977	source = 2;
		5978	reg_slot = 1;
		5979	}
		5980	else
		5981	{
		5982	/* VexW1 is set, the second operand is the source and
		5983	the third operand is encoded in the immediate
		5984	operand. */
		5985	source = 1;
		5986	reg_slot = 2;
		5987	}
		5988
		5989	if (i.tm.opcode_modifier.immext)
		5990	{
		5991	/* When ImmExt is set, the immdiate byte is the last
		5992	operand. */
		5993	imm_slot = i.operands - 1;
		5994	source--;
		5995	reg_slot--;
		5996	}
		5997	else
		5998	{
		5999	imm_slot = 0;
		6000
		6001	/* Turn on Imm8 so that output_imm will generate it. */
		6002	i.types[imm_slot].bitfield.imm8 = 1;
		6003	}
		6004
		6005	gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
		6006	®xmm)
		6007	\|\| operand_type_equal (&i.tm.operand_types[reg_slot],
		6008	®ymm)
		6009	\|\| operand_type_equal (&i.tm.operand_types[reg_slot],
		6010	®zmm));
		6011	i.op[imm_slot].imms->X_add_number
		6012	\|= register_number (i.op[reg_slot].regs) << 4;
		6013	gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
		6014	}
		6015
		6016	gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
		6017	\|\| operand_type_equal (&i.tm.operand_types[nds],
		6018	®ymm)
		6019	\|\| operand_type_equal (&i.tm.operand_types[nds],
		6020	®zmm));
		6021	i.vex.register_specifier = i.op[nds].regs;
		6022	}
		6023	else
		6024	source = dest = 0;
		6025
		6026	/* i.reg_operands MUST be the number of real register operands;
		6027	implicit registers do not count. If there are 3 register
		6028	operands, it must be a instruction with VexNDS. For a
		6029	instruction with VexNDD, the destination register is encoded
		6030	in VEX prefix. If there are 4 register operands, it must be
		6031	a instruction with VEX prefix and 3 sources. */
		6032	if (i.mem_operands == 0
		6033	&& ((i.reg_operands == 2
		6034	&& i.tm.opcode_modifier.vexvvvv <= VEXXDS)
		6035	\|\| (i.reg_operands == 3
		6036	&& i.tm.opcode_modifier.vexvvvv == VEXXDS)
		6037	\|\| (i.reg_operands == 4 && vex_3_sources)))
		6038	{
		6039	switch (i.operands)
		6040	{
		6041	case 2:
		6042	source = 0;
		6043	break;
		6044	case 3:
		6045	/* When there are 3 operands, one of them may be immediate,
		6046	which may be the first or the last operand. Otherwise,
		6047	the first operand must be shift count register (cl) or it
		6048	is an instruction with VexNDS. */
		6049	gas_assert (i.imm_operands == 1
		6050	\|\| (i.imm_operands == 0
		6051	&& (i.tm.opcode_modifier.vexvvvv == VEXXDS
		6052	\|\| i.types[0].bitfield.shiftcount)));
		6053	if (operand_type_check (i.types[0], imm)
		6054	\|\| i.types[0].bitfield.shiftcount)
		6055	source = 1;
		6056	else
		6057	source = 0;
		6058	break;
		6059	case 4:
		6060	/* When there are 4 operands, the first two must be 8bit
		6061	immediate operands. The source operand will be the 3rd
		6062	one.
		6063
		6064	For instructions with VexNDS, if the first operand
		6065	an imm8, the source operand is the 2nd one. If the last
		6066	operand is imm8, the source operand is the first one. */
		6067	gas_assert ((i.imm_operands == 2
		6068	&& i.types[0].bitfield.imm8
		6069	&& i.types[1].bitfield.imm8)
		6070	\|\| (i.tm.opcode_modifier.vexvvvv == VEXXDS
		6071	&& i.imm_operands == 1
		6072	&& (i.types[0].bitfield.imm8
		6073	\|\| i.types[i.operands - 1].bitfield.imm8
		6074	\|\| i.rounding)));
		6075	if (i.imm_operands == 2)
		6076	source = 2;
		6077	else
		6078	{
		6079	if (i.types[0].bitfield.imm8)
		6080	source = 1;
		6081	else
		6082	source = 0;
		6083	}
		6084	break;
		6085	case 5:
		6086	if (i.tm.opcode_modifier.evex)
		6087	{
		6088	/* For EVEX instructions, when there are 5 operands, the
		6089	first one must be immediate operand. If the second one
		6090	is immediate operand, the source operand is the 3th
		6091	one. If the last one is immediate operand, the source
		6092	operand is the 2nd one. */
		6093	gas_assert (i.imm_operands == 2
		6094	&& i.tm.opcode_modifier.sae
		6095	&& operand_type_check (i.types[0], imm));
		6096	if (operand_type_check (i.types[1], imm))
		6097	source = 2;
		6098	else if (operand_type_check (i.types[4], imm))
		6099	source = 1;
		6100	else
		6101	abort ();
		6102	}
		6103	break;
		6104	default:
		6105	abort ();
		6106	}
		6107
		6108	if (!vex_3_sources)
		6109	{
		6110	dest = source + 1;
		6111
		6112	/* RC/SAE operand could be between DEST and SRC. That happens
		6113	when one operand is GPR and the other one is XMM/YMM/ZMM
		6114	register. */
		6115	if (i.rounding && i.rounding->operand == (int) dest)
		6116	dest++;
		6117
		6118	if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
		6119	{
		6120	/* For instructions with VexNDS, the register-only source
		6121	operand must be 32/64bit integer, XMM, YMM or ZMM
		6122	register. It is encoded in VEX prefix. We need to
		6123	clear RegMem bit before calling operand_type_equal. */
		6124
		6125	i386_operand_type op;
		6126	unsigned int vvvv;
		6127
		6128	/* Check register-only source operand when two source
		6129	operands are swapped. */
		6130	if (!i.tm.operand_types[source].bitfield.baseindex
		6131	&& i.tm.operand_types[dest].bitfield.baseindex)
		6132	{
		6133	vvvv = source;
		6134	source = dest;
		6135	}
		6136	else
		6137	vvvv = dest;
		6138
		6139	op = i.tm.operand_types[vvvv];
		6140	op.bitfield.regmem = 0;
		6141	if ((dest + 1) >= i.operands
		6142	\|\| (op.bitfield.reg32 != 1
		6143	&& !op.bitfield.reg64 != 1
		6144	&& !operand_type_equal (&op, ®xmm)
		6145	&& !operand_type_equal (&op, ®ymm)
		6146	&& !operand_type_equal (&op, ®zmm)
		6147	&& !operand_type_equal (&op, ®mask)))
		6148	abort ();
		6149	i.vex.register_specifier = i.op[vvvv].regs;
		6150	dest++;
		6151	}
		6152	}
		6153
		6154	i.rm.mode = 3;
		6155	/* One of the register operands will be encoded in the i.tm.reg
		6156	field, the other in the combined i.tm.mode and i.tm.regmem
		6157	fields. If no form of this instruction supports a memory
		6158	destination operand, then we assume the source operand may
		6159	sometimes be a memory operand and so we need to store the
		6160	destination in the i.rm.reg field. */
		6161	if (!i.tm.operand_types[dest].bitfield.regmem
		6162	&& operand_type_check (i.tm.operand_types[dest], anymem) == 0)
		6163	{
		6164	i.rm.reg = i.op[dest].regs->reg_num;
		6165	i.rm.regmem = i.op[source].regs->reg_num;
		6166	if ((i.op[dest].regs->reg_flags & RegRex) != 0)
		6167	i.rex \|= REX_R;
		6168	if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
		6169	i.vrex \|= REX_R;
		6170	if ((i.op[source].regs->reg_flags & RegRex) != 0)
		6171	i.rex \|= REX_B;
		6172	if ((i.op[source].regs->reg_flags & RegVRex) != 0)
		6173	i.vrex \|= REX_B;
		6174	}
		6175	else
		6176	{
		6177	i.rm.reg = i.op[source].regs->reg_num;
		6178	i.rm.regmem = i.op[dest].regs->reg_num;
		6179	if ((i.op[dest].regs->reg_flags & RegRex) != 0)
		6180	i.rex \|= REX_B;
		6181	if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
		6182	i.vrex \|= REX_B;
		6183	if ((i.op[source].regs->reg_flags & RegRex) != 0)
		6184	i.rex \|= REX_R;
		6185	if ((i.op[source].regs->reg_flags & RegVRex) != 0)
		6186	i.vrex \|= REX_R;
		6187	}
		6188	if (flag_code != CODE_64BIT && (i.rex & (REX_R \| REX_B)))
		6189	{
		6190	if (!i.types[0].bitfield.control
		6191	&& !i.types[1].bitfield.control)
		6192	abort ();
		6193	i.rex &= ~(REX_R \| REX_B);
		6194	add_prefix (LOCK_PREFIX_OPCODE);
		6195	}
		6196	}
		6197	else
		6198	{ /* If it's not 2 reg operands... */
		6199	unsigned int mem;
		6200
		6201	if (i.mem_operands)
		6202	{
		6203	unsigned int fake_zero_displacement = 0;
		6204	unsigned int op;
		6205
		6206	for (op = 0; op < i.operands; op++)
		6207	if (operand_type_check (i.types[op], anymem))
		6208	break;
		6209	gas_assert (op < i.operands);
		6210
		6211	if (i.tm.opcode_modifier.vecsib)
		6212	{
		6213	if (i.index_reg->reg_num == RegEiz
		6214	\|\| i.index_reg->reg_num == RegRiz)
		6215	abort ();
		6216
		6217	i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
		6218	if (!i.base_reg)
		6219	{
		6220	i.sib.base = NO_BASE_REGISTER;
		6221	i.sib.scale = i.log2_scale_factor;
		6222	/* No Vec_Disp8 if there is no base. */
		6223	i.types[op].bitfield.vec_disp8 = 0;
		6224	i.types[op].bitfield.disp8 = 0;
		6225	i.types[op].bitfield.disp16 = 0;
		6226	i.types[op].bitfield.disp64 = 0;
		6227	if (flag_code != CODE_64BIT)
		6228	{
		6229	/* Must be 32 bit */
		6230	i.types[op].bitfield.disp32 = 1;
		6231	i.types[op].bitfield.disp32s = 0;
		6232	}
		6233	else
		6234	{
		6235	i.types[op].bitfield.disp32 = 0;
		6236	i.types[op].bitfield.disp32s = 1;
		6237	}
		6238	}
		6239	i.sib.index = i.index_reg->reg_num;
		6240	if ((i.index_reg->reg_flags & RegRex) != 0)
		6241	i.rex \|= REX_X;
		6242	if ((i.index_reg->reg_flags & RegVRex) != 0)
		6243	i.vrex \|= REX_X;
		6244	}
		6245
		6246	default_seg = &ds;
		6247
		6248	if (i.base_reg == 0)
		6249	{
		6250	i.rm.mode = 0;
		6251	if (!i.disp_operands)
		6252	{
		6253	fake_zero_displacement = 1;
		6254	/* Instructions with VSIB byte need 32bit displacement
		6255	if there is no base register. */
		6256	if (i.tm.opcode_modifier.vecsib)
		6257	i.types[op].bitfield.disp32 = 1;
		6258	}
		6259	if (i.index_reg == 0)
		6260	{
		6261	gas_assert (!i.tm.opcode_modifier.vecsib);
		6262	/* Operand is just */
		6263	if (flag_code == CODE_64BIT)
		6264	{
		6265	/* 64bit mode overwrites the 32bit absolute
		6266	addressing by RIP relative addressing and
		6267	absolute addressing is encoded by one of the
		6268	redundant SIB forms. */
		6269	i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
		6270	i.sib.base = NO_BASE_REGISTER;
		6271	i.sib.index = NO_INDEX_REGISTER;
		6272	i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
		6273	? disp32s : disp32);
		6274	}
		6275	else if ((flag_code == CODE_16BIT)
		6276	^ (i.prefix[ADDR_PREFIX] != 0))
		6277	{
		6278	i.rm.regmem = NO_BASE_REGISTER_16;
		6279	i.types[op] = disp16;
		6280	}
		6281	else
		6282	{
		6283	i.rm.regmem = NO_BASE_REGISTER;
		6284	i.types[op] = disp32;
		6285	}
		6286	}
		6287	else if (!i.tm.opcode_modifier.vecsib)
		6288	{
		6289	/* !i.base_reg && i.index_reg */
		6290	if (i.index_reg->reg_num == RegEiz
		6291	\|\| i.index_reg->reg_num == RegRiz)
		6292	i.sib.index = NO_INDEX_REGISTER;
		6293	else
		6294	i.sib.index = i.index_reg->reg_num;
		6295	i.sib.base = NO_BASE_REGISTER;
		6296	i.sib.scale = i.log2_scale_factor;
		6297	i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
		6298	/* No Vec_Disp8 if there is no base. */
		6299	i.types[op].bitfield.vec_disp8 = 0;
		6300	i.types[op].bitfield.disp8 = 0;
		6301	i.types[op].bitfield.disp16 = 0;
		6302	i.types[op].bitfield.disp64 = 0;
		6303	if (flag_code != CODE_64BIT)
		6304	{
		6305	/* Must be 32 bit */
		6306	i.types[op].bitfield.disp32 = 1;
		6307	i.types[op].bitfield.disp32s = 0;
		6308	}
		6309	else
		6310	{
		6311	i.types[op].bitfield.disp32 = 0;
		6312	i.types[op].bitfield.disp32s = 1;
		6313	}
		6314	if ((i.index_reg->reg_flags & RegRex) != 0)
		6315	i.rex \|= REX_X;
		6316	}
		6317	}
		6318	/* RIP addressing for 64bit mode. */
		6319	else if (i.base_reg->reg_num == RegRip \|\|
		6320	i.base_reg->reg_num == RegEip)
		6321	{
		6322	gas_assert (!i.tm.opcode_modifier.vecsib);
		6323	i.rm.regmem = NO_BASE_REGISTER;
		6324	i.types[op].bitfield.disp8 = 0;
		6325	i.types[op].bitfield.disp16 = 0;
		6326	i.types[op].bitfield.disp32 = 0;
		6327	i.types[op].bitfield.disp32s = 1;
		6328	i.types[op].bitfield.disp64 = 0;
		6329	i.types[op].bitfield.vec_disp8 = 0;
		6330	i.flags[op] \|= Operand_PCrel;
		6331	if (! i.disp_operands)
		6332	fake_zero_displacement = 1;
		6333	}
		6334	else if (i.base_reg->reg_type.bitfield.reg16)
		6335	{
		6336	gas_assert (!i.tm.opcode_modifier.vecsib);
		6337	switch (i.base_reg->reg_num)
		6338	{
		6339	case 3: /* (%bx) */
		6340	if (i.index_reg == 0)
		6341	i.rm.regmem = 7;
		6342	else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
		6343	i.rm.regmem = i.index_reg->reg_num - 6;
		6344	break;
		6345	case 5: /* (%bp) */
		6346	default_seg = &ss;
		6347	if (i.index_reg == 0)
		6348	{
		6349	i.rm.regmem = 6;
		6350	if (operand_type_check (i.types[op], disp) == 0)
		6351	{
		6352	/* fake (%bp) into 0(%bp) */
		6353	if (i.tm.operand_types[op].bitfield.vec_disp8)
		6354	i.types[op].bitfield.vec_disp8 = 1;
		6355	else
		6356	i.types[op].bitfield.disp8 = 1;
		6357	fake_zero_displacement = 1;
		6358	}
		6359	}
		6360	else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
		6361	i.rm.regmem = i.index_reg->reg_num - 6 + 2;
		6362	break;
		6363	default: /* (%si) -> 4 or (%di) -> 5 */
		6364	i.rm.regmem = i.base_reg->reg_num - 6 + 4;
		6365	}
		6366	i.rm.mode = mode_from_disp_size (i.types[op]);
		6367	}
		6368	else /* i.base_reg and 32/64 bit mode */
		6369	{
		6370	if (flag_code == CODE_64BIT
		6371	&& operand_type_check (i.types[op], disp))
		6372	{
		6373	i386_operand_type temp;
		6374	operand_type_set (&temp, 0);
		6375	temp.bitfield.disp8 = i.types[op].bitfield.disp8;
		6376	temp.bitfield.vec_disp8
		6377	= i.types[op].bitfield.vec_disp8;
		6378	i.types[op] = temp;
		6379	if (i.prefix[ADDR_PREFIX] == 0)
		6380	i.types[op].bitfield.disp32s = 1;
		6381	else
		6382	i.types[op].bitfield.disp32 = 1;
		6383	}
		6384
		6385	if (!i.tm.opcode_modifier.vecsib)
		6386	i.rm.regmem = i.base_reg->reg_num;
		6387	if ((i.base_reg->reg_flags & RegRex) != 0)
		6388	i.rex \|= REX_B;
		6389	i.sib.base = i.base_reg->reg_num;
		6390	/* x86-64 ignores REX prefix bit here to avoid decoder
		6391	complications. */
		6392	if (!(i.base_reg->reg_flags & RegRex)
		6393	&& (i.base_reg->reg_num == EBP_REG_NUM
		6394	\|\| i.base_reg->reg_num == ESP_REG_NUM))
		6395	default_seg = &ss;
		6396	if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
		6397	{
		6398	fake_zero_displacement = 1;
		6399	if (i.tm.operand_types [op].bitfield.vec_disp8)
		6400	i.types[op].bitfield.vec_disp8 = 1;
		6401	else
		6402	i.types[op].bitfield.disp8 = 1;
		6403	}
		6404	i.sib.scale = i.log2_scale_factor;
		6405	if (i.index_reg == 0)
		6406	{
		6407	gas_assert (!i.tm.opcode_modifier.vecsib);
		6408	/* (%esp) becomes two byte modrm with no index
		6409	register. We've already stored the code for esp
		6410	in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
		6411	Any base register besides %esp will not use the
		6412	extra modrm byte. */
		6413	i.sib.index = NO_INDEX_REGISTER;
		6414	}
		6415	else if (!i.tm.opcode_modifier.vecsib)
		6416	{
		6417	if (i.index_reg->reg_num == RegEiz
		6418	\|\| i.index_reg->reg_num == RegRiz)
		6419	i.sib.index = NO_INDEX_REGISTER;
		6420	else
		6421	i.sib.index = i.index_reg->reg_num;
		6422	i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
		6423	if ((i.index_reg->reg_flags & RegRex) != 0)
		6424	i.rex \|= REX_X;
		6425	}
		6426
		6427	if (i.disp_operands
		6428	&& (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
		6429	\|\| i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
		6430	i.rm.mode = 0;
		6431	else
		6432	{
		6433	if (!fake_zero_displacement
		6434	&& !i.disp_operands
		6435	&& i.disp_encoding)
		6436	{
		6437	fake_zero_displacement = 1;
		6438	if (i.disp_encoding == disp_encoding_8bit)
		6439	i.types[op].bitfield.disp8 = 1;
		6440	else
		6441	i.types[op].bitfield.disp32 = 1;
		6442	}
		6443	i.rm.mode = mode_from_disp_size (i.types[op]);
		6444	}
		6445	}
		6446
		6447	if (fake_zero_displacement)
		6448	{
		6449	/* Fakes a zero displacement assuming that i.types[op]
		6450	holds the correct displacement size. */
		6451	expressionS *exp;
		6452
		6453	gas_assert (i.op[op].disps == 0);
		6454	exp = &disp_expressions[i.disp_operands++];
		6455	i.op[op].disps = exp;
		6456	exp->X_op = O_constant;
		6457	exp->X_add_number = 0;
		6458	exp->X_add_symbol = (symbolS *) 0;
		6459	exp->X_op_symbol = (symbolS *) 0;
		6460	}
		6461
		6462	mem = op;
		6463	}
		6464	else
		6465	mem = ~0;
		6466
		6467	if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
		6468	{
		6469	if (operand_type_check (i.types[0], imm))
		6470	i.vex.register_specifier = NULL;
		6471	else
		6472	{
		6473	/* VEX.vvvv encodes one of the sources when the first
		6474	operand is not an immediate. */
		6475	if (i.tm.opcode_modifier.vexw == VEXW0)
		6476	i.vex.register_specifier = i.op[0].regs;
		6477	else
		6478	i.vex.register_specifier = i.op[1].regs;
		6479	}
		6480
		6481	/* Destination is a XMM register encoded in the ModRM.reg
		6482	and VEX.R bit. */
		6483	i.rm.reg = i.op[2].regs->reg_num;
		6484	if ((i.op[2].regs->reg_flags & RegRex) != 0)
		6485	i.rex \|= REX_R;
		6486
		6487	/* ModRM.rm and VEX.B encodes the other source. */
		6488	if (!i.mem_operands)
		6489	{
		6490	i.rm.mode = 3;
		6491
		6492	if (i.tm.opcode_modifier.vexw == VEXW0)
		6493	i.rm.regmem = i.op[1].regs->reg_num;
		6494	else
		6495	i.rm.regmem = i.op[0].regs->reg_num;
		6496
		6497	if ((i.op[1].regs->reg_flags & RegRex) != 0)
		6498	i.rex \|= REX_B;
		6499	}
		6500	}
		6501	else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
		6502	{
		6503	i.vex.register_specifier = i.op[2].regs;
		6504	if (!i.mem_operands)
		6505	{
		6506	i.rm.mode = 3;
		6507	i.rm.regmem = i.op[1].regs->reg_num;
		6508	if ((i.op[1].regs->reg_flags & RegRex) != 0)
		6509	i.rex \|= REX_B;
		6510	}
		6511	}
		6512	/* Fill in i.rm.reg or i.rm.regmem field with register operand
		6513	(if any) based on i.tm.extension_opcode. Again, we must be
		6514	careful to make sure that segment/control/debug/test/MMX
		6515	registers are coded into the i.rm.reg field. */
		6516	else if (i.reg_operands)
		6517	{
		6518	unsigned int op;
		6519	unsigned int vex_reg = ~0;
		6520
		6521	for (op = 0; op < i.operands; op++)
		6522	if (i.types[op].bitfield.reg8
		6523	\|\| i.types[op].bitfield.reg16
		6524	\|\| i.types[op].bitfield.reg32
		6525	\|\| i.types[op].bitfield.reg64
		6526	\|\| i.types[op].bitfield.regmmx
		6527	\|\| i.types[op].bitfield.regxmm
		6528	\|\| i.types[op].bitfield.regymm
		6529	\|\| i.types[op].bitfield.regbnd
		6530	\|\| i.types[op].bitfield.regzmm
		6531	\|\| i.types[op].bitfield.regmask
		6532	\|\| i.types[op].bitfield.sreg2
		6533	\|\| i.types[op].bitfield.sreg3
		6534	\|\| i.types[op].bitfield.control
		6535	\|\| i.types[op].bitfield.debug
		6536	\|\| i.types[op].bitfield.test)
		6537	break;
		6538
		6539	if (vex_3_sources)
		6540	op = dest;
		6541	else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
		6542	{
		6543	/* For instructions with VexNDS, the register-only
		6544	source operand is encoded in VEX prefix. */
		6545	gas_assert (mem != (unsigned int) ~0);
		6546
		6547	if (op > mem)
		6548	{
		6549	vex_reg = op++;
		6550	gas_assert (op < i.operands);
		6551	}
		6552	else
		6553	{
		6554	/* Check register-only source operand when two source
		6555	operands are swapped. */
		6556	if (!i.tm.operand_types[op].bitfield.baseindex
		6557	&& i.tm.operand_types[op + 1].bitfield.baseindex)
		6558	{
		6559	vex_reg = op;
		6560	op += 2;
		6561	gas_assert (mem == (vex_reg + 1)
		6562	&& op < i.operands);
		6563	}
		6564	else
		6565	{
		6566	vex_reg = op + 1;
		6567	gas_assert (vex_reg < i.operands);
		6568	}
		6569	}
		6570	}
		6571	else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
		6572	{
		6573	/* For instructions with VexNDD, the register destination
		6574	is encoded in VEX prefix. */
		6575	if (i.mem_operands == 0)
		6576	{
		6577	/* There is no memory operand. */
		6578	gas_assert ((op + 2) == i.operands);
		6579	vex_reg = op + 1;
		6580	}
		6581	else
		6582	{
		6583	/* There are only 2 operands. */
		6584	gas_assert (op < 2 && i.operands == 2);
		6585	vex_reg = 1;
		6586	}
		6587	}
		6588	else
		6589	gas_assert (op < i.operands);
		6590
		6591	if (vex_reg != (unsigned int) ~0)
		6592	{
		6593	i386_operand_type *type = &i.tm.operand_types[vex_reg];
		6594
		6595	if (type->bitfield.reg32 != 1
		6596	&& type->bitfield.reg64 != 1
		6597	&& !operand_type_equal (type, ®xmm)
		6598	&& !operand_type_equal (type, ®ymm)
		6599	&& !operand_type_equal (type, ®zmm)
		6600	&& !operand_type_equal (type, ®mask))
		6601	abort ();
		6602
		6603	i.vex.register_specifier = i.op[vex_reg].regs;
		6604	}
		6605
		6606	/* Don't set OP operand twice. */
		6607	if (vex_reg != op)
		6608	{
		6609	/* If there is an extension opcode to put here, the
		6610	register number must be put into the regmem field. */
		6611	if (i.tm.extension_opcode != None)
		6612	{
		6613	i.rm.regmem = i.op[op].regs->reg_num;
		6614	if ((i.op[op].regs->reg_flags & RegRex) != 0)
		6615	i.rex \|= REX_B;
		6616	if ((i.op[op].regs->reg_flags & RegVRex) != 0)
		6617	i.vrex \|= REX_B;
		6618	}
		6619	else
		6620	{
		6621	i.rm.reg = i.op[op].regs->reg_num;
		6622	if ((i.op[op].regs->reg_flags & RegRex) != 0)
		6623	i.rex \|= REX_R;
		6624	if ((i.op[op].regs->reg_flags & RegVRex) != 0)
		6625	i.vrex \|= REX_R;
		6626	}
		6627	}
		6628
		6629	/* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
		6630	must set it to 3 to indicate this is a register operand
		6631	in the regmem field. */
		6632	if (!i.mem_operands)
		6633	i.rm.mode = 3;
		6634	}
		6635
		6636	/* Fill in i.rm.reg field with extension opcode (if any). */
		6637	if (i.tm.extension_opcode != None)
		6638	i.rm.reg = i.tm.extension_opcode;
		6639	}
		6640	return default_seg;
		6641	}
		6642
		6643	static void
		6644	output_branch (void)
		6645	{
		6646	char *p;
		6647	int size;
		6648	int code16;
		6649	int prefix;
		6650	relax_substateT subtype;
		6651	symbolS *sym;
		6652	offsetT off;
		6653
		6654	code16 = flag_code == CODE_16BIT ? CODE16 : 0;
		6655	size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
		6656
		6657	prefix = 0;
		6658	if (i.prefix[DATA_PREFIX] != 0)
		6659	{
		6660	prefix = 1;
		6661	i.prefixes -= 1;
		6662	code16 ^= CODE16;
		6663	}
		6664	/* Pentium4 branch hints. */
		6665	if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
		6666	\|\| i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
		6667	{
		6668	prefix++;
		6669	i.prefixes--;
		6670	}
		6671	if (i.prefix[REX_PREFIX] != 0)
		6672	{
		6673	prefix++;
		6674	i.prefixes--;
		6675	}
		6676
		6677	/* BND prefixed jump. */
		6678	if (i.prefix[BND_PREFIX] != 0)
		6679	{
		6680	FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
		6681	i.prefixes -= 1;
		6682	}
		6683
		6684	if (i.prefixes != 0 && !intel_syntax)
		6685	as_warn (_("skipping prefixes on this instruction"));
		6686
		6687	/* It's always a symbol; End frag & setup for relax.
		6688	Make sure there is enough room in this frag for the largest
		6689	instruction we may generate in md_convert_frag. This is 2
		6690	bytes for the opcode and room for the prefix and largest
		6691	displacement. */
		6692	frag_grow (prefix + 2 + 4);
		6693	/* Prefix and 1 opcode byte go in fr_fix. */
		6694	p = frag_more (prefix + 1);
		6695	if (i.prefix[DATA_PREFIX] != 0)
		6696	*p++ = DATA_PREFIX_OPCODE;
		6697	if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
		6698	\|\| i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
		6699	*p++ = i.prefix[SEG_PREFIX];
		6700	if (i.prefix[REX_PREFIX] != 0)
		6701	*p++ = i.prefix[REX_PREFIX];
		6702	*p = i.tm.base_opcode;
		6703
		6704	if ((unsigned char) *p == JUMP_PC_RELATIVE)
		6705	subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
		6706	else if (cpu_arch_flags.bitfield.cpui386)
		6707	subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
		6708	else
		6709	subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
		6710	subtype \|= code16;
		6711
		6712	sym = i.op[0].disps->X_add_symbol;
		6713	off = i.op[0].disps->X_add_number;
		6714
		6715	if (i.op[0].disps->X_op != O_constant
		6716	&& i.op[0].disps->X_op != O_symbol)
		6717	{
		6718	/* Handle complex expressions. */
		6719	sym = make_expr_symbol (i.op[0].disps);
		6720	off = 0;
		6721	}
		6722
		6723	/* 1 possible extra opcode + 4 byte displacement go in var part.
		6724	Pass reloc in fr_var. */
		6725	frag_var (rs_machine_dependent, 5,
		6726	((!object_64bit
		6727	\|\| i.reloc[0] != NO_RELOC
		6728	\|\| (i.bnd_prefix == NULL && !add_bnd_prefix))
		6729	? i.reloc[0]
		6730	: BFD_RELOC_X86_64_PC32_BND),
		6731	subtype, sym, off, p);
		6732	}
		6733
		6734	static void
		6735	output_jump (void)
		6736	{
		6737	char *p;
		6738	int size;
		6739	fixS *fixP;
		6740
		6741	if (i.tm.opcode_modifier.jumpbyte)
		6742	{
		6743	/* This is a loop or jecxz type instruction. */
		6744	size = 1;
		6745	if (i.prefix[ADDR_PREFIX] != 0)
		6746	{
		6747	FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
		6748	i.prefixes -= 1;
		6749	}
		6750	/* Pentium4 branch hints. */
		6751	if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
		6752	\|\| i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
		6753	{
		6754	FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
		6755	i.prefixes--;
		6756	}
		6757	}
		6758	else
		6759	{
		6760	int code16;
		6761
		6762	code16 = 0;
		6763	if (flag_code == CODE_16BIT)
		6764	code16 = CODE16;
		6765
		6766	if (i.prefix[DATA_PREFIX] != 0)
		6767	{
		6768	FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
		6769	i.prefixes -= 1;
		6770	code16 ^= CODE16;
		6771	}
		6772
		6773	size = 4;
		6774	if (code16)
		6775	size = 2;
		6776	}
		6777
		6778	if (i.prefix[REX_PREFIX] != 0)
		6779	{
		6780	FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
		6781	i.prefixes -= 1;
		6782	}
		6783
		6784	/* BND prefixed jump. */
		6785	if (i.prefix[BND_PREFIX] != 0)
		6786	{
		6787	FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
		6788	i.prefixes -= 1;
		6789	}
		6790
		6791	if (i.prefixes != 0 && !intel_syntax)
		6792	as_warn (_("skipping prefixes on this instruction"));
		6793
		6794	p = frag_more (i.tm.opcode_length + size);
		6795	switch (i.tm.opcode_length)
		6796	{
		6797	case 2:
		6798	*p++ = i.tm.base_opcode >> 8;
		6799	case 1:
		6800	*p++ = i.tm.base_opcode;
		6801	break;
		6802	default:
		6803	abort ();
		6804	}
		6805
		6806	fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
		6807	i.op[0].disps, 1, reloc (size, 1, 1,
		6808	(i.bnd_prefix != NULL
		6809	\|\| add_bnd_prefix),
		6810	i.reloc[0]));
		6811
		6812	/* All jumps handled here are signed, but don't use a signed limit
		6813	check for 32 and 16 bit jumps as we want to allow wrap around at
		6814	4G and 64k respectively. */
		6815	if (size == 1)
		6816	fixP->fx_signed = 1;
		6817	}
		6818
		6819	static void
		6820	output_interseg_jump (void)
		6821	{
		6822	char *p;
		6823	int size;
		6824	int prefix;
		6825	int code16;
		6826
		6827	code16 = 0;
		6828	if (flag_code == CODE_16BIT)
		6829	code16 = CODE16;
		6830
		6831	prefix = 0;
		6832	if (i.prefix[DATA_PREFIX] != 0)
		6833	{
		6834	prefix = 1;
		6835	i.prefixes -= 1;
		6836	code16 ^= CODE16;
		6837	}
		6838	if (i.prefix[REX_PREFIX] != 0)
		6839	{
		6840	prefix++;
		6841	i.prefixes -= 1;
		6842	}
		6843
		6844	size = 4;
		6845	if (code16)
		6846	size = 2;
		6847
		6848	if (i.prefixes != 0 && !intel_syntax)
		6849	as_warn (_("skipping prefixes on this instruction"));
		6850
		6851	/* 1 opcode; 2 segment; offset */
		6852	p = frag_more (prefix + 1 + 2 + size);
		6853
		6854	if (i.prefix[DATA_PREFIX] != 0)
		6855	*p++ = DATA_PREFIX_OPCODE;
		6856
		6857	if (i.prefix[REX_PREFIX] != 0)
		6858	*p++ = i.prefix[REX_PREFIX];
		6859
		6860	*p++ = i.tm.base_opcode;
		6861	if (i.op[1].imms->X_op == O_constant)
		6862	{
		6863	offsetT n = i.op[1].imms->X_add_number;
		6864
		6865	if (size == 2
		6866	&& !fits_in_unsigned_word (n)
		6867	&& !fits_in_signed_word (n))
		6868	{
		6869	as_bad (_("16-bit jump out of range"));
		6870	return;
		6871	}
		6872	md_number_to_chars (p, n, size);
		6873	}
		6874	else
		6875	fix_new_exp (frag_now, p - frag_now->fr_literal, size,
		6876	i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
		6877	if (i.op[0].imms->X_op != O_constant)
		6878	as_bad (_("can't handle non absolute segment in `%s'"),
		6879	i.tm.name);
		6880	md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
		6881	}
		6882
		6883	static void
		6884	output_insn (void)
		6885	{
		6886	fragS *insn_start_frag;
		6887	offsetT insn_start_off;
		6888
		6889	/* Tie dwarf2 debug info to the address at the start of the insn.
		6890	We can't do this after the insn has been output as the current
		6891	frag may have been closed off. eg. by frag_var. */
		6892	dwarf2_emit_insn (0);
		6893
		6894	insn_start_frag = frag_now;
		6895	insn_start_off = frag_now_fix ();
		6896
		6897	/* Output jumps. */
		6898	if (i.tm.opcode_modifier.jump)
		6899	output_branch ();
		6900	else if (i.tm.opcode_modifier.jumpbyte
		6901	\|\| i.tm.opcode_modifier.jumpdword)
		6902	output_jump ();
		6903	else if (i.tm.opcode_modifier.jumpintersegment)
		6904	output_interseg_jump ();
		6905	else
		6906	{
		6907	/* Output normal instructions here. */
		6908	char *p;
		6909	unsigned char *q;
		6910	unsigned int j;
		6911	unsigned int prefix;
		6912
		6913	/* Since the VEX/EVEX prefix contains the implicit prefix, we
		6914	don't need the explicit prefix. */
		6915	if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
		6916	{
		6917	switch (i.tm.opcode_length)
		6918	{
		6919	case 3:
		6920	if (i.tm.base_opcode & 0xff000000)
		6921	{
		6922	prefix = (i.tm.base_opcode >> 24) & 0xff;
		6923	goto check_prefix;
		6924	}
		6925	break;
		6926	case 2:
		6927	if ((i.tm.base_opcode & 0xff0000) != 0)
		6928	{
		6929	prefix = (i.tm.base_opcode >> 16) & 0xff;
		6930	if (i.tm.cpu_flags.bitfield.cpupadlock)
		6931	{
		6932	check_prefix:
		6933	if (prefix != REPE_PREFIX_OPCODE
		6934	\|\| (i.prefix[REP_PREFIX]
		6935	!= REPE_PREFIX_OPCODE))
		6936	add_prefix (prefix);
		6937	}
		6938	else
		6939	add_prefix (prefix);
		6940	}
		6941	break;
		6942	case 1:
		6943	break;
		6944	default:
		6945	abort ();
		6946	}
		6947
		6948	/* The prefix bytes. */
		6949	for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
		6950	if (*q)
		6951	FRAG_APPEND_1_CHAR (*q);
		6952	}
		6953	else
		6954	{
		6955	for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
		6956	if (*q)
		6957	switch (j)
		6958	{
		6959	case REX_PREFIX:
		6960	/* REX byte is encoded in VEX prefix. */
		6961	break;
		6962	case SEG_PREFIX:
		6963	case ADDR_PREFIX:
		6964	FRAG_APPEND_1_CHAR (*q);
		6965	break;
		6966	default:
		6967	/* There should be no other prefixes for instructions
		6968	with VEX prefix. */
		6969	abort ();
		6970	}
		6971
		6972	/* For EVEX instructions i.vrex should become 0 after
		6973	build_evex_prefix. For VEX instructions upper 16 registers
		6974	aren't available, so VREX should be 0. */
		6975	if (i.vrex)
		6976	abort ();
		6977	/* Now the VEX prefix. */
		6978	p = frag_more (i.vex.length);
		6979	for (j = 0; j < i.vex.length; j++)
		6980	p[j] = i.vex.bytes[j];
		6981	}
		6982
		6983	/* Now the opcode; be careful about word order here! */
		6984	if (i.tm.opcode_length == 1)
		6985	{
		6986	FRAG_APPEND_1_CHAR (i.tm.base_opcode);
		6987	}
		6988	else
		6989	{
		6990	switch (i.tm.opcode_length)
		6991	{
		6992	case 4:
		6993	p = frag_more (4);
		6994	*p++ = (i.tm.base_opcode >> 24) & 0xff;
		6995	*p++ = (i.tm.base_opcode >> 16) & 0xff;
		6996	break;
		6997	case 3:
		6998	p = frag_more (3);
		6999	*p++ = (i.tm.base_opcode >> 16) & 0xff;
		7000	break;
		7001	case 2:
		7002	p = frag_more (2);
		7003	break;
		7004	default:
		7005	abort ();
		7006	break;
		7007	}
		7008
		7009	/* Put out high byte first: can't use md_number_to_chars! */
		7010	*p++ = (i.tm.base_opcode >> 8) & 0xff;
		7011	*p = i.tm.base_opcode & 0xff;
		7012	}
		7013
		7014	/* Now the modrm byte and sib byte (if present). */
		7015	if (i.tm.opcode_modifier.modrm)
		7016	{
		7017	FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
		7018	\| i.rm.reg << 3
		7019	\| i.rm.mode << 6));
		7020	/* If i.rm.regmem == ESP (4)
		7021	&& i.rm.mode != (Register mode)
		7022	&& not 16 bit
		7023	==> need second modrm byte. */
		7024	if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
		7025	&& i.rm.mode != 3
		7026	&& !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
		7027	FRAG_APPEND_1_CHAR ((i.sib.base << 0
		7028	\| i.sib.index << 3
		7029	\| i.sib.scale << 6));
		7030	}
		7031
		7032	if (i.disp_operands)
		7033	output_disp (insn_start_frag, insn_start_off);
		7034
		7035	if (i.imm_operands)
		7036	output_imm (insn_start_frag, insn_start_off);
		7037	}
		7038
		7039	#ifdef DEBUG386
		7040	if (flag_debug)
		7041	{
		7042	pi ("" /line/, &i);
		7043	}
		7044	#endif /* DEBUG386 */
		7045	}
		7046
		7047	/* Return the size of the displacement operand N. */
		7048
		7049	static int
		7050	disp_size (unsigned int n)
		7051	{
		7052	int size = 4;
		7053
		7054	/* Vec_Disp8 has to be 8bit. */
		7055	if (i.types[n].bitfield.vec_disp8)
		7056	size = 1;
		7057	else if (i.types[n].bitfield.disp64)
		7058	size = 8;
		7059	else if (i.types[n].bitfield.disp8)
		7060	size = 1;
		7061	else if (i.types[n].bitfield.disp16)
		7062	size = 2;
		7063	return size;
		7064	}
		7065
		7066	/* Return the size of the immediate operand N. */
		7067
		7068	static int
		7069	imm_size (unsigned int n)
		7070	{
		7071	int size = 4;
		7072	if (i.types[n].bitfield.imm64)
		7073	size = 8;
		7074	else if (i.types[n].bitfield.imm8 \|\| i.types[n].bitfield.imm8s)
		7075	size = 1;
		7076	else if (i.types[n].bitfield.imm16)
		7077	size = 2;
		7078	return size;
		7079	}
		7080
		7081	static void
		7082	output_disp (fragS *insn_start_frag, offsetT insn_start_off)
		7083	{
		7084	char *p;
		7085	unsigned int n;
		7086
		7087	for (n = 0; n < i.operands; n++)
		7088	{
		7089	if (i.types[n].bitfield.vec_disp8
		7090	\|\| operand_type_check (i.types[n], disp))
		7091	{
		7092	if (i.op[n].disps->X_op == O_constant)
		7093	{
		7094	int size = disp_size (n);
		7095	offsetT val = i.op[n].disps->X_add_number;
		7096
		7097	if (i.types[n].bitfield.vec_disp8)
		7098	val >>= i.memshift;
		7099	val = offset_in_range (val, size);
		7100	p = frag_more (size);
		7101	md_number_to_chars (p, val, size);
		7102	}
		7103	else
		7104	{
		7105	enum bfd_reloc_code_real reloc_type;
		7106	int size = disp_size (n);
		7107	int sign = i.types[n].bitfield.disp32s;
		7108	int pcrel = (i.flags[n] & Operand_PCrel) != 0;
		7109
		7110	/* We can't have 8 bit displacement here. */
		7111	gas_assert (!i.types[n].bitfield.disp8);
		7112
		7113	/* The PC relative address is computed relative
		7114	to the instruction boundary, so in case immediate
		7115	fields follows, we need to adjust the value. */
		7116	if (pcrel && i.imm_operands)
		7117	{
		7118	unsigned int n1;
		7119	int sz = 0;
		7120
		7121	for (n1 = 0; n1 < i.operands; n1++)
		7122	if (operand_type_check (i.types[n1], imm))
		7123	{
		7124	/* Only one immediate is allowed for PC
		7125	relative address. */
		7126	gas_assert (sz == 0);
		7127	sz = imm_size (n1);
		7128	i.op[n].disps->X_add_number -= sz;
		7129	}
		7130	/* We should find the immediate. */
		7131	gas_assert (sz != 0);
		7132	}
		7133
		7134	p = frag_more (size);
		7135	reloc_type = reloc (size, pcrel, sign,
		7136	(i.bnd_prefix != NULL
		7137	\|\| add_bnd_prefix),
		7138	i.reloc[n]);
		7139	if (GOT_symbol
		7140	&& GOT_symbol == i.op[n].disps->X_add_symbol
		7141	&& (((reloc_type == BFD_RELOC_32
		7142	\|\| reloc_type == BFD_RELOC_X86_64_32S
		7143	\|\| (reloc_type == BFD_RELOC_64
		7144	&& object_64bit))
		7145	&& (i.op[n].disps->X_op == O_symbol
		7146	\|\| (i.op[n].disps->X_op == O_add
		7147	&& ((symbol_get_value_expression
		7148	(i.op[n].disps->X_op_symbol)->X_op)
		7149	== O_subtract))))
		7150	\|\| reloc_type == BFD_RELOC_32_PCREL))
		7151	{
		7152	offsetT add;
		7153
		7154	if (insn_start_frag == frag_now)
		7155	add = (p - frag_now->fr_literal) - insn_start_off;
		7156	else
		7157	{
		7158	fragS *fr;
		7159
		7160	add = insn_start_frag->fr_fix - insn_start_off;
		7161	for (fr = insn_start_frag->fr_next;
		7162	fr && fr != frag_now; fr = fr->fr_next)
		7163	add += fr->fr_fix;
		7164	add += p - frag_now->fr_literal;
		7165	}
		7166
		7167	if (!object_64bit)
		7168	{
		7169	reloc_type = BFD_RELOC_386_GOTPC;
		7170	i.op[n].imms->X_add_number += add;
		7171	}
		7172	else if (reloc_type == BFD_RELOC_64)
		7173	reloc_type = BFD_RELOC_X86_64_GOTPC64;
		7174	else
		7175	/* Don't do the adjustment for x86-64, as there
		7176	the pcrel addressing is relative to the _next_
		7177	insn, and that is taken care of in other code. */
		7178	reloc_type = BFD_RELOC_X86_64_GOTPC32;
		7179	}
		7180	fix_new_exp (frag_now, p - frag_now->fr_literal, size,
		7181	i.op[n].disps, pcrel, reloc_type);
		7182	}
		7183	}
		7184	}
		7185	}
		7186
		7187	static void
		7188	output_imm (fragS *insn_start_frag, offsetT insn_start_off)
		7189	{
		7190	char *p;
		7191	unsigned int n;
		7192
		7193	for (n = 0; n < i.operands; n++)
		7194	{
		7195	/* Skip SAE/RC Imm operand in EVEX. They are already handled. */
		7196	if (i.rounding && (int) n == i.rounding->operand)
		7197	continue;
		7198
		7199	if (operand_type_check (i.types[n], imm))
		7200	{
		7201	if (i.op[n].imms->X_op == O_constant)
		7202	{
		7203	int size = imm_size (n);
		7204	offsetT val;
		7205
		7206	val = offset_in_range (i.op[n].imms->X_add_number,
		7207	size);
		7208	p = frag_more (size);
		7209	md_number_to_chars (p, val, size);
		7210	}
		7211	else
		7212	{
		7213	/* Not absolute_section.
		7214	Need a 32-bit fixup (don't support 8bit
		7215	non-absolute imms). Try to support other
		7216	sizes ... */
		7217	enum bfd_reloc_code_real reloc_type;
		7218	int size = imm_size (n);
		7219	int sign;
		7220
		7221	if (i.types[n].bitfield.imm32s
		7222	&& (i.suffix == QWORD_MNEM_SUFFIX
		7223	\|\| (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
		7224	sign = 1;
		7225	else
		7226	sign = 0;
		7227
		7228	p = frag_more (size);
		7229	reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
		7230
		7231	/* This is tough to explain. We end up with this one if we
		7232	* have operands that look like
		7233	* "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
		7234	* obtain the absolute address of the GOT, and it is strongly
		7235	* preferable from a performance point of view to avoid using
		7236	* a runtime relocation for this. The actual sequence of
		7237	* instructions often look something like:
		7238	*
		7239	* call .L66
		7240	* .L66:
		7241	* popl %ebx
		7242	* addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
		7243	*
		7244	* The call and pop essentially return the absolute address
		7245	* of the label .L66 and store it in %ebx. The linker itself
		7246	* will ultimately change the first operand of the addl so
		7247	* that %ebx points to the GOT, but to keep things simple, the
		7248	* .o file must have this operand set so that it generates not
		7249	* the absolute address of .L66, but the absolute address of
		7250	* itself. This allows the linker itself simply treat a GOTPC
		7251	* relocation as asking for a pcrel offset to the GOT to be
		7252	* added in, and the addend of the relocation is stored in the
		7253	* operand field for the instruction itself.
		7254	*
		7255	* Our job here is to fix the operand so that it would add
		7256	* the correct offset so that %ebx would point to itself. The
		7257	* thing that is tricky is that .-.L66 will point to the
		7258	* beginning of the instruction, so we need to further modify
		7259	* the operand so that it will point to itself. There are
		7260	* other cases where you have something like:
		7261	*
		7262	* .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
		7263	*
		7264	* and here no correction would be required. Internally in
		7265	* the assembler we treat operands of this form as not being
		7266	* pcrel since the '.' is explicitly mentioned, and I wonder
		7267	* whether it would simplify matters to do it this way. Who
		7268	* knows. In earlier versions of the PIC patches, the
		7269	* pcrel_adjust field was used to store the correction, but
		7270	* since the expression is not pcrel, I felt it would be
		7271	* confusing to do it this way. */
		7272
		7273	if ((reloc_type == BFD_RELOC_32
		7274	\|\| reloc_type == BFD_RELOC_X86_64_32S
		7275	\|\| reloc_type == BFD_RELOC_64)
		7276	&& GOT_symbol
		7277	&& GOT_symbol == i.op[n].imms->X_add_symbol
		7278	&& (i.op[n].imms->X_op == O_symbol
		7279	\|\| (i.op[n].imms->X_op == O_add
		7280	&& ((symbol_get_value_expression
		7281	(i.op[n].imms->X_op_symbol)->X_op)
		7282	== O_subtract))))
		7283	{
		7284	offsetT add;
		7285
		7286	if (insn_start_frag == frag_now)
		7287	add = (p - frag_now->fr_literal) - insn_start_off;
		7288	else
		7289	{
		7290	fragS *fr;
		7291
		7292	add = insn_start_frag->fr_fix - insn_start_off;
		7293	for (fr = insn_start_frag->fr_next;
		7294	fr && fr != frag_now; fr = fr->fr_next)
		7295	add += fr->fr_fix;
		7296	add += p - frag_now->fr_literal;
		7297	}
		7298
		7299	if (!object_64bit)
		7300	reloc_type = BFD_RELOC_386_GOTPC;
		7301	else if (size == 4)
		7302	reloc_type = BFD_RELOC_X86_64_GOTPC32;
		7303	else if (size == 8)
		7304	reloc_type = BFD_RELOC_X86_64_GOTPC64;
		7305	i.op[n].imms->X_add_number += add;
		7306	}
		7307	fix_new_exp (frag_now, p - frag_now->fr_literal, size,
		7308	i.op[n].imms, 0, reloc_type);
		7309	}
		7310	}
		7311	}
		7312	}
		7313
		7314	/* x86_cons_fix_new is called via the expression parsing code when a
		7315	reloc is needed. We use this hook to get the correct .got reloc. */
		7316	static enum bfd_reloc_code_real got_reloc = NO_RELOC;
		7317	static int cons_sign = -1;
		7318
		7319	void
		7320	x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
		7321	expressionS *exp)
		7322	{
		7323	enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
		7324
		7325	got_reloc = NO_RELOC;
		7326
		7327	#ifdef TE_PE
		7328	if (exp->X_op == O_secrel)
		7329	{
		7330	exp->X_op = O_symbol;
		7331	r = BFD_RELOC_32_SECREL;
		7332	}
		7333	#endif
		7334
		7335	fix_new_exp (frag, off, len, exp, 0, r);
		7336	}
		7337
		7338	/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
		7339	purpose of the `.dc.a' internal pseudo-op. */
		7340
		7341	int
		7342	x86_address_bytes (void)
		7343	{
		7344	if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
		7345	return 4;
		7346	return stdoutput->arch_info->bits_per_address / 8;
		7347	}
		7348
		7349	#if !(defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) \|\| defined (OBJ_MACH_O)) \
		7350	\|\| defined (LEX_AT)
		7351	# define lex_got(reloc, adjust, types, bnd_prefix) NULL
		7352	#else
		7353	/* Parse operands of the form
		7354	@GOTOFF+
		7355	and similar .plt or .got references.
		7356
		7357	If we find one, set up the correct relocation in RELOC and copy the
		7358	input string, minus the `@GOTOFF' into a malloc'd buffer for
		7359	parsing by the calling routine. Return this buffer, and if ADJUST
		7360	is non-null set it to the length of the string we removed from the
		7361	input line. Otherwise return NULL. */
		7362	static char *
		7363	lex_got (enum bfd_reloc_code_real *rel,
		7364	int *adjust,
		7365	i386_operand_type *types,
		7366	int bnd_prefix)
		7367	{
		7368	/* Some of the relocations depend on the size of what field is to
		7369	be relocated. But in our callers i386_immediate and i386_displacement
		7370	we don't yet know the operand size (this will be set by insn
		7371	matching). Hence we record the word32 relocation here,
		7372	and adjust the reloc according to the real size in reloc(). */
		7373	static const struct {
		7374	const char *str;
		7375	int len;
		7376	const enum bfd_reloc_code_real rel[2];
		7377	const i386_operand_type types64;
		7378	} gotrel[] = {
		7379	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		7380	{ STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
		7381	BFD_RELOC_SIZE32 },
		7382	OPERAND_TYPE_IMM32_64 },
		7383	#endif
		7384	{ STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
		7385	BFD_RELOC_X86_64_PLTOFF64 },
		7386	OPERAND_TYPE_IMM64 },
		7387	{ STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
		7388	BFD_RELOC_X86_64_PLT32 },
		7389	OPERAND_TYPE_IMM32_32S_DISP32 },
		7390	{ STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
		7391	BFD_RELOC_X86_64_GOTPLT64 },
		7392	OPERAND_TYPE_IMM64_DISP64 },
		7393	{ STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
		7394	BFD_RELOC_X86_64_GOTOFF64 },
		7395	OPERAND_TYPE_IMM64_DISP64 },
		7396	{ STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
		7397	BFD_RELOC_X86_64_GOTPCREL },
		7398	OPERAND_TYPE_IMM32_32S_DISP32 },
		7399	{ STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
		7400	BFD_RELOC_X86_64_TLSGD },
		7401	OPERAND_TYPE_IMM32_32S_DISP32 },
		7402	{ STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
		7403	_dummy_first_bfd_reloc_code_real },
		7404	OPERAND_TYPE_NONE },
		7405	{ STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
		7406	BFD_RELOC_X86_64_TLSLD },
		7407	OPERAND_TYPE_IMM32_32S_DISP32 },
		7408	{ STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
		7409	BFD_RELOC_X86_64_GOTTPOFF },
		7410	OPERAND_TYPE_IMM32_32S_DISP32 },
		7411	{ STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
		7412	BFD_RELOC_X86_64_TPOFF32 },
		7413	OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
		7414	{ STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
		7415	_dummy_first_bfd_reloc_code_real },
		7416	OPERAND_TYPE_NONE },
		7417	{ STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
		7418	BFD_RELOC_X86_64_DTPOFF32 },
		7419	OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
		7420	{ STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
		7421	_dummy_first_bfd_reloc_code_real },
		7422	OPERAND_TYPE_NONE },
		7423	{ STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
		7424	_dummy_first_bfd_reloc_code_real },
		7425	OPERAND_TYPE_NONE },
		7426	{ STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
		7427	BFD_RELOC_X86_64_GOT32 },
		7428	OPERAND_TYPE_IMM32_32S_64_DISP32 },
		7429	{ STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
		7430	BFD_RELOC_X86_64_GOTPC32_TLSDESC },
		7431	OPERAND_TYPE_IMM32_32S_DISP32 },
		7432	{ STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
		7433	BFD_RELOC_X86_64_TLSDESC_CALL },
		7434	OPERAND_TYPE_IMM32_32S_DISP32 },
		7435	};
		7436	char *cp;
		7437	unsigned int j;
		7438
		7439	#if defined (OBJ_MAYBE_ELF)
		7440	if (!IS_ELF)
		7441	return NULL;
		7442	#endif
		7443
		7444	for (cp = input_line_pointer; *cp != '@'; cp++)
		7445	if (is_end_of_line[(unsigned char) cp] \|\| cp == ',')
		7446	return NULL;
		7447
		7448	for (j = 0; j < ARRAY_SIZE (gotrel); j++)
		7449	{
		7450	int len = gotrel[j].len;
		7451	if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
		7452	{
		7453	if (gotrel[j].rel[object_64bit] != 0)
		7454	{
		7455	int first, second;
		7456	char tmpbuf, past_reloc;
		7457
		7458	*rel = gotrel[j].rel[object_64bit];
		7459
		7460	if (types)
		7461	{
		7462	if (flag_code != CODE_64BIT)
		7463	{
		7464	types->bitfield.imm32 = 1;
		7465	types->bitfield.disp32 = 1;
		7466	}
		7467	else
		7468	*types = gotrel[j].types64;
		7469	}
		7470
		7471	if (j != 0 && GOT_symbol == NULL)
		7472	GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
		7473
		7474	/* The length of the first part of our input line. */
		7475	first = cp - input_line_pointer;
		7476
		7477	/* The second part goes from after the reloc token until
		7478	(and including) an end_of_line char or comma. */
		7479	past_reloc = cp + 1 + len;
		7480	cp = past_reloc;
		7481	while (!is_end_of_line[(unsigned char) cp] && cp != ',')
		7482	++cp;
		7483	second = cp + 1 - past_reloc;
		7484
		7485	/* Allocate and copy string. The trailing NUL shouldn't
		7486	be necessary, but be safe. */
		7487	tmpbuf = (char *) xmalloc (first + second + 2);
		7488	memcpy (tmpbuf, input_line_pointer, first);
		7489	if (second != 0 && *past_reloc != ' ')
		7490	/* Replace the relocation token with ' ', so that
		7491	errors like foo@GOTOFF1 will be detected. */
		7492	tmpbuf[first++] = ' ';
		7493	else
		7494	/* Increment length by 1 if the relocation token is
		7495	removed. */
		7496	len++;
		7497	if (adjust)
		7498	*adjust = len;
		7499	memcpy (tmpbuf + first, past_reloc, second);
		7500	tmpbuf[first + second] = '\0';
		7501	if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
		7502	*rel = BFD_RELOC_X86_64_PLT32_BND;
		7503	return tmpbuf;
		7504	}
		7505
		7506	as_bad (_("@%s reloc is not supported with %d-bit output format"),
		7507	gotrel[j].str, 1 << (5 + object_64bit));
		7508	return NULL;
		7509	}
		7510	}
		7511
		7512	/* Might be a symbol version string. Don't as_bad here. */
		7513	return NULL;
		7514	}
		7515	#endif
		7516
		7517	#ifdef TE_PE
		7518	#ifdef lex_got
		7519	#undef lex_got
		7520	#endif
		7521	/* Parse operands of the form
		7522	@SECREL32+
		7523
		7524	If we find one, set up the correct relocation in RELOC and copy the
		7525	input string, minus the `@SECREL32' into a malloc'd buffer for
		7526	parsing by the calling routine. Return this buffer, and if ADJUST
		7527	is non-null set it to the length of the string we removed from the
		7528	input line. Otherwise return NULL.
		7529
		7530	This function is copied from the ELF version above adjusted for PE targets. */
		7531
		7532	static char *
		7533	lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
		7534	int *adjust ATTRIBUTE_UNUSED,
		7535	i386_operand_type *types,
		7536	int bnd_prefix ATTRIBUTE_UNUSED)
		7537	{
		7538	static const struct
		7539	{
		7540	const char *str;
		7541	int len;
		7542	const enum bfd_reloc_code_real rel[2];
		7543	const i386_operand_type types64;
		7544	}
		7545	gotrel[] =
		7546	{
		7547	{ STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
		7548	BFD_RELOC_32_SECREL },
		7549	OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
		7550	};
		7551
		7552	char *cp;
		7553	unsigned j;
		7554
		7555	for (cp = input_line_pointer; *cp != '@'; cp++)
		7556	if (is_end_of_line[(unsigned char) cp] \|\| cp == ',')
		7557	return NULL;
		7558
		7559	for (j = 0; j < ARRAY_SIZE (gotrel); j++)
		7560	{
		7561	int len = gotrel[j].len;
		7562
		7563	if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
		7564	{
		7565	if (gotrel[j].rel[object_64bit] != 0)
		7566	{
		7567	int first, second;
		7568	char tmpbuf, past_reloc;
		7569
		7570	*rel = gotrel[j].rel[object_64bit];
		7571	if (adjust)
		7572	*adjust = len;
		7573
		7574	if (types)
		7575	{
		7576	if (flag_code != CODE_64BIT)
		7577	{
		7578	types->bitfield.imm32 = 1;
		7579	types->bitfield.disp32 = 1;
		7580	}
		7581	else
		7582	*types = gotrel[j].types64;
		7583	}
		7584
		7585	/* The length of the first part of our input line. */
		7586	first = cp - input_line_pointer;
		7587
		7588	/* The second part goes from after the reloc token until
		7589	(and including) an end_of_line char or comma. */
		7590	past_reloc = cp + 1 + len;
		7591	cp = past_reloc;
		7592	while (!is_end_of_line[(unsigned char) cp] && cp != ',')
		7593	++cp;
		7594	second = cp + 1 - past_reloc;
		7595
		7596	/* Allocate and copy string. The trailing NUL shouldn't
		7597	be necessary, but be safe. */
		7598	tmpbuf = (char *) xmalloc (first + second + 2);
		7599	memcpy (tmpbuf, input_line_pointer, first);
		7600	if (second != 0 && *past_reloc != ' ')
		7601	/* Replace the relocation token with ' ', so that
		7602	errors like foo@SECLREL321 will be detected. */
		7603	tmpbuf[first++] = ' ';
		7604	memcpy (tmpbuf + first, past_reloc, second);
		7605	tmpbuf[first + second] = '\0';
		7606	return tmpbuf;
		7607	}
		7608
		7609	as_bad (_("@%s reloc is not supported with %d-bit output format"),
		7610	gotrel[j].str, 1 << (5 + object_64bit));
		7611	return NULL;
		7612	}
		7613	}
		7614
		7615	/* Might be a symbol version string. Don't as_bad here. */
		7616	return NULL;
		7617	}
		7618
		7619	#endif /* TE_PE */
		7620
		7621	void
		7622	x86_cons (expressionS *exp, int size)
		7623	{
		7624	intel_syntax = -intel_syntax;
		7625
		7626	exp->X_md = 0;
		7627	if (size == 4 \|\| (object_64bit && size == 8))
		7628	{
		7629	/* Handle @GOTOFF and the like in an expression. */
		7630	char *save;
		7631	char *gotfree_input_line;
		7632	int adjust = 0;
		7633
		7634	save = input_line_pointer;
		7635	gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
		7636	if (gotfree_input_line)
		7637	input_line_pointer = gotfree_input_line;
		7638
		7639	expression (exp);
		7640
		7641	if (gotfree_input_line)
		7642	{
		7643	/* expression () has merrily parsed up to the end of line,
		7644	or a comma - in the wrong buffer. Transfer how far
		7645	input_line_pointer has moved to the right buffer. */
		7646	input_line_pointer = (save
		7647	+ (input_line_pointer - gotfree_input_line)
		7648	+ adjust);
		7649	free (gotfree_input_line);
		7650	if (exp->X_op == O_constant
		7651	\|\| exp->X_op == O_absent
		7652	\|\| exp->X_op == O_illegal
		7653	\|\| exp->X_op == O_register
		7654	\|\| exp->X_op == O_big)
		7655	{
		7656	char c = *input_line_pointer;
		7657	*input_line_pointer = 0;
		7658	as_bad (_("missing or invalid expression `%s'"), save);
		7659	*input_line_pointer = c;
		7660	}
		7661	}
		7662	}
		7663	else
		7664	expression (exp);
		7665
		7666	intel_syntax = -intel_syntax;
		7667
		7668	if (intel_syntax)
		7669	i386_intel_simplify (exp);
		7670	}
		7671
		7672	static void
		7673	signed_cons (int size)
		7674	{
		7675	if (flag_code == CODE_64BIT)
		7676	cons_sign = 1;
		7677	cons (size);
		7678	cons_sign = -1;
		7679	}
		7680
		7681	#ifdef TE_PE
		7682	static void
		7683	pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
		7684	{
		7685	expressionS exp;
		7686
		7687	do
		7688	{
		7689	expression (&exp);
		7690	if (exp.X_op == O_symbol)
		7691	exp.X_op = O_secrel;
		7692
		7693	emit_expr (&exp, 4);
		7694	}
		7695	while (*input_line_pointer++ == ',');
		7696
		7697	input_line_pointer--;
		7698	demand_empty_rest_of_line ();
		7699	}
		7700	#endif
		7701
		7702	/* Handle Vector operations. */
		7703
		7704	static char *
		7705	check_VecOperations (char op_string, char op_end)
		7706	{
		7707	const reg_entry *mask;
		7708	const char *saved;
		7709	char *end_op;
		7710
		7711	while (*op_string
		7712	&& (op_end == NULL \|\| op_string < op_end))
		7713	{
		7714	saved = op_string;
		7715	if (*op_string == '{')
		7716	{
		7717	op_string++;
		7718
		7719	/* Check broadcasts. */
		7720	if (strncmp (op_string, "1to", 3) == 0)
		7721	{
		7722	int bcst_type;
		7723
		7724	if (i.broadcast)
		7725	goto duplicated_vec_op;
		7726
		7727	op_string += 3;
		7728	if (*op_string == '8')
		7729	bcst_type = BROADCAST_1TO8;
		7730	else if (*op_string == '1'
		7731	&& *(op_string+1) == '6')
		7732	{
		7733	bcst_type = BROADCAST_1TO16;
		7734	op_string++;
		7735	}
		7736	else
		7737	{
		7738	as_bad (_("Unsupported broadcast: `%s'"), saved);
		7739	return NULL;
		7740	}
		7741	op_string++;
		7742
		7743	broadcast_op.type = bcst_type;
		7744	broadcast_op.operand = this_operand;
		7745	i.broadcast = &broadcast_op;
		7746	}
		7747	/* Check masking operation. */
		7748	else if ((mask = parse_register (op_string, &end_op)) != NULL)
		7749	{
		7750	/* k0 can't be used for write mask. */
		7751	if (mask->reg_num == 0)
		7752	{
		7753	as_bad (_("`%s' can't be used for write mask"),
		7754	op_string);
		7755	return NULL;
		7756	}
		7757
		7758	if (!i.mask)
		7759	{
		7760	mask_op.mask = mask;
		7761	mask_op.zeroing = 0;
		7762	mask_op.operand = this_operand;
		7763	i.mask = &mask_op;
		7764	}
		7765	else
		7766	{
		7767	if (i.mask->mask)
		7768	goto duplicated_vec_op;
		7769
		7770	i.mask->mask = mask;
		7771
		7772	/* Only "{z}" is allowed here. No need to check
		7773	zeroing mask explicitly. */
		7774	if (i.mask->operand != this_operand)
		7775	{
		7776	as_bad (_("invalid write mask `%s'"), saved);
		7777	return NULL;
		7778	}
		7779	}
		7780
		7781	op_string = end_op;
		7782	}
		7783	/* Check zeroing-flag for masking operation. */
		7784	else if (*op_string == 'z')
		7785	{
		7786	if (!i.mask)
		7787	{
		7788	mask_op.mask = NULL;
		7789	mask_op.zeroing = 1;
		7790	mask_op.operand = this_operand;
		7791	i.mask = &mask_op;
		7792	}
		7793	else
		7794	{
		7795	if (i.mask->zeroing)
		7796	{
		7797	duplicated_vec_op:
		7798	as_bad (_("duplicated `%s'"), saved);
		7799	return NULL;
		7800	}
		7801
		7802	i.mask->zeroing = 1;
		7803
		7804	/* Only "{%k}" is allowed here. No need to check mask
		7805	register explicitly. */
		7806	if (i.mask->operand != this_operand)
		7807	{
		7808	as_bad (_("invalid zeroing-masking `%s'"),
		7809	saved);
		7810	return NULL;
		7811	}
		7812	}
		7813
		7814	op_string++;
		7815	}
		7816	else
		7817	goto unknown_vec_op;
		7818
		7819	if (*op_string != '}')
		7820	{
		7821	as_bad (_("missing `}' in `%s'"), saved);
		7822	return NULL;
		7823	}
		7824	op_string++;
		7825	continue;
		7826	}
		7827	unknown_vec_op:
		7828	/* We don't know this one. */
		7829	as_bad (_("unknown vector operation: `%s'"), saved);
		7830	return NULL;
		7831	}
		7832
		7833	return op_string;
		7834	}
		7835
		7836	static int
		7837	i386_immediate (char *imm_start)
		7838	{
		7839	char *save_input_line_pointer;
		7840	char *gotfree_input_line;
		7841	segT exp_seg = 0;
		7842	expressionS *exp;
		7843	i386_operand_type types;
		7844
		7845	operand_type_set (&types, ~0);
		7846
		7847	if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
		7848	{
		7849	as_bad (_("at most %d immediate operands are allowed"),
		7850	MAX_IMMEDIATE_OPERANDS);
		7851	return 0;
		7852	}
		7853
		7854	exp = &im_expressions[i.imm_operands++];
		7855	i.op[this_operand].imms = exp;
		7856
		7857	if (is_space_char (*imm_start))
		7858	++imm_start;
		7859
		7860	save_input_line_pointer = input_line_pointer;
		7861	input_line_pointer = imm_start;
		7862
		7863	gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
		7864	(i.bnd_prefix != NULL
		7865	\|\| add_bnd_prefix));
		7866	if (gotfree_input_line)
		7867	input_line_pointer = gotfree_input_line;
		7868
		7869	exp_seg = expression (exp);
		7870
		7871	SKIP_WHITESPACE ();
		7872
		7873	/* Handle vector operations. */
		7874	if (*input_line_pointer == '{')
		7875	{
		7876	input_line_pointer = check_VecOperations (input_line_pointer,
		7877	NULL);
		7878	if (input_line_pointer == NULL)
		7879	return 0;
		7880	}
		7881
		7882	if (*input_line_pointer)
		7883	as_bad (_("junk `%s' after expression"), input_line_pointer);
		7884
		7885	input_line_pointer = save_input_line_pointer;
		7886	if (gotfree_input_line)
		7887	{
		7888	free (gotfree_input_line);
		7889
		7890	if (exp->X_op == O_constant \|\| exp->X_op == O_register)
		7891	exp->X_op = O_illegal;
		7892	}
		7893
		7894	return i386_finalize_immediate (exp_seg, exp, types, imm_start);
		7895	}
		7896
		7897	static int
		7898	i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
		7899	i386_operand_type types, const char *imm_start)
		7900	{
		7901	if (exp->X_op == O_absent \|\| exp->X_op == O_illegal \|\| exp->X_op == O_big)
		7902	{
		7903	if (imm_start)
		7904	as_bad (_("missing or invalid immediate expression `%s'"),
		7905	imm_start);
		7906	return 0;
		7907	}
		7908	else if (exp->X_op == O_constant)
		7909	{
		7910	/* Size it properly later. */
		7911	i.types[this_operand].bitfield.imm64 = 1;
		7912	/* If not 64bit, sign extend val. */
		7913	if (flag_code != CODE_64BIT
		7914	&& (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
		7915	exp->X_add_number
		7916	= (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
		7917	}
		7918	#if (defined (OBJ_AOUT) \|\| defined (OBJ_MAYBE_AOUT))
		7919	else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
		7920	&& exp_seg != absolute_section
		7921	&& exp_seg != text_section
		7922	&& exp_seg != data_section
		7923	&& exp_seg != bss_section
		7924	&& exp_seg != undefined_section
		7925	&& !bfd_is_com_section (exp_seg))
		7926	{
		7927	as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
		7928	return 0;
		7929	}
		7930	#endif
		7931	else if (!intel_syntax && exp->X_op == O_register)
		7932	{
		7933	if (imm_start)
		7934	as_bad (_("illegal immediate register operand %s"), imm_start);
		7935	return 0;
		7936	}
		7937	else
		7938	{
		7939	/* This is an address. The size of the address will be
		7940	determined later, depending on destination register,
		7941	suffix, or the default for the section. */
		7942	i.types[this_operand].bitfield.imm8 = 1;
		7943	i.types[this_operand].bitfield.imm16 = 1;
		7944	i.types[this_operand].bitfield.imm32 = 1;
		7945	i.types[this_operand].bitfield.imm32s = 1;
		7946	i.types[this_operand].bitfield.imm64 = 1;
		7947	i.types[this_operand] = operand_type_and (i.types[this_operand],
		7948	types);
		7949	}
		7950
		7951	return 1;
		7952	}
		7953
		7954	static char *
		7955	i386_scale (char *scale)
		7956	{
		7957	offsetT val;
		7958	char *save = input_line_pointer;
		7959
		7960	input_line_pointer = scale;
		7961	val = get_absolute_expression ();
		7962
		7963	switch (val)
		7964	{
		7965	case 1:
		7966	i.log2_scale_factor = 0;
		7967	break;
		7968	case 2:
		7969	i.log2_scale_factor = 1;
		7970	break;
		7971	case 4:
		7972	i.log2_scale_factor = 2;
		7973	break;
		7974	case 8:
		7975	i.log2_scale_factor = 3;
		7976	break;
		7977	default:
		7978	{
		7979	char sep = *input_line_pointer;
		7980
		7981	*input_line_pointer = '\0';
		7982	as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
		7983	scale);
		7984	*input_line_pointer = sep;
		7985	input_line_pointer = save;
		7986	return NULL;
		7987	}
		7988	}
		7989	if (i.log2_scale_factor != 0 && i.index_reg == 0)
		7990	{
		7991	as_warn (_("scale factor of %d without an index register"),
		7992	1 << i.log2_scale_factor);
		7993	i.log2_scale_factor = 0;
		7994	}
		7995	scale = input_line_pointer;
		7996	input_line_pointer = save;
		7997	return scale;
		7998	}
		7999
		8000	static int
		8001	i386_displacement (char disp_start, char disp_end)
		8002	{
		8003	expressionS *exp;
		8004	segT exp_seg = 0;
		8005	char *save_input_line_pointer;
		8006	char *gotfree_input_line;
		8007	int override;
		8008	i386_operand_type bigdisp, types = anydisp;
		8009	int ret;
		8010
		8011	if (i.disp_operands == MAX_MEMORY_OPERANDS)
		8012	{
		8013	as_bad (_("at most %d displacement operands are allowed"),
		8014	MAX_MEMORY_OPERANDS);
		8015	return 0;
		8016	}
		8017
		8018	operand_type_set (&bigdisp, 0);
		8019	if ((i.types[this_operand].bitfield.jumpabsolute)
		8020	\|\| (!current_templates->start->opcode_modifier.jump
		8021	&& !current_templates->start->opcode_modifier.jumpdword))
		8022	{
		8023	bigdisp.bitfield.disp32 = 1;
		8024	override = (i.prefix[ADDR_PREFIX] != 0);
		8025	if (flag_code == CODE_64BIT)
		8026	{
		8027	if (!override)
		8028	{
		8029	bigdisp.bitfield.disp32s = 1;
		8030	bigdisp.bitfield.disp64 = 1;
		8031	}
		8032	}
		8033	else if ((flag_code == CODE_16BIT) ^ override)
		8034	{
		8035	bigdisp.bitfield.disp32 = 0;
		8036	bigdisp.bitfield.disp16 = 1;
		8037	}
		8038	}
		8039	else
		8040	{
		8041	/* For PC-relative branches, the width of the displacement
		8042	is dependent upon data size, not address size. */
		8043	override = (i.prefix[DATA_PREFIX] != 0);
		8044	if (flag_code == CODE_64BIT)
		8045	{
		8046	if (override \|\| i.suffix == WORD_MNEM_SUFFIX)
		8047	bigdisp.bitfield.disp16 = 1;
		8048	else
		8049	{
		8050	bigdisp.bitfield.disp32 = 1;
		8051	bigdisp.bitfield.disp32s = 1;
		8052	}
		8053	}
		8054	else
		8055	{
		8056	if (!override)
		8057	override = (i.suffix == (flag_code != CODE_16BIT
		8058	? WORD_MNEM_SUFFIX
		8059	: LONG_MNEM_SUFFIX));
		8060	bigdisp.bitfield.disp32 = 1;
		8061	if ((flag_code == CODE_16BIT) ^ override)
		8062	{
		8063	bigdisp.bitfield.disp32 = 0;
		8064	bigdisp.bitfield.disp16 = 1;
		8065	}
		8066	}
		8067	}
		8068	i.types[this_operand] = operand_type_or (i.types[this_operand],
		8069	bigdisp);
		8070
		8071	exp = &disp_expressions[i.disp_operands];
		8072	i.op[this_operand].disps = exp;
		8073	i.disp_operands++;
		8074	save_input_line_pointer = input_line_pointer;
		8075	input_line_pointer = disp_start;
		8076	END_STRING_AND_SAVE (disp_end);
		8077
		8078	#ifndef GCC_ASM_O_HACK
		8079	#define GCC_ASM_O_HACK 0
		8080	#endif
		8081	#if GCC_ASM_O_HACK
		8082	END_STRING_AND_SAVE (disp_end + 1);
		8083	if (i.types[this_operand].bitfield.baseIndex
		8084	&& displacement_string_end[-1] == '+')
		8085	{
		8086	/* This hack is to avoid a warning when using the "o"
		8087	constraint within gcc asm statements.
		8088	For instance:
		8089
		8090	#define _set_tssldt_desc(n,addr,limit,type) \
		8091	__asm__ __volatile__ ( \
		8092	"movw %w2,%0\n\t" \
		8093	"movw %w1,2+%0\n\t" \
		8094	"rorl $16,%1\n\t" \
		8095	"movb %b1,4+%0\n\t" \
		8096	"movb %4,5+%0\n\t" \
		8097	"movb $0,6+%0\n\t" \
		8098	"movb %h1,7+%0\n\t" \
		8099	"rorl $16,%1" \
		8100	: "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
		8101
		8102	This works great except that the output assembler ends
		8103	up looking a bit weird if it turns out that there is
		8104	no offset. You end up producing code that looks like:
		8105
		8106	#APP
		8107	movw $235,(%eax)
		8108	movw %dx,2+(%eax)
		8109	rorl $16,%edx
		8110	movb %dl,4+(%eax)
		8111	movb $137,5+(%eax)
		8112	movb $0,6+(%eax)
		8113	movb %dh,7+(%eax)
		8114	rorl $16,%edx
		8115	#NO_APP
		8116
		8117	So here we provide the missing zero. */
		8118
		8119	*displacement_string_end = '0';
		8120	}
		8121	#endif
		8122	gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
		8123	(i.bnd_prefix != NULL
		8124	\|\| add_bnd_prefix));
		8125	if (gotfree_input_line)
		8126	input_line_pointer = gotfree_input_line;
		8127
		8128	exp_seg = expression (exp);
		8129
		8130	SKIP_WHITESPACE ();
		8131	if (*input_line_pointer)
		8132	as_bad (_("junk `%s' after expression"), input_line_pointer);
		8133	#if GCC_ASM_O_HACK
		8134	RESTORE_END_STRING (disp_end + 1);
		8135	#endif
		8136	input_line_pointer = save_input_line_pointer;
		8137	if (gotfree_input_line)
		8138	{
		8139	free (gotfree_input_line);
		8140
		8141	if (exp->X_op == O_constant \|\| exp->X_op == O_register)
		8142	exp->X_op = O_illegal;
		8143	}
		8144
		8145	ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
		8146
		8147	RESTORE_END_STRING (disp_end);
		8148
		8149	return ret;
		8150	}
		8151
		8152	static int
		8153	i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
		8154	i386_operand_type types, const char *disp_start)
		8155	{
		8156	i386_operand_type bigdisp;
		8157	int ret = 1;
		8158
		8159	/* We do this to make sure that the section symbol is in
		8160	the symbol table. We will ultimately change the relocation
		8161	to be relative to the beginning of the section. */
		8162	if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
		8163	\|\| i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
		8164	\|\| i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
		8165	{
		8166	if (exp->X_op != O_symbol)
		8167	goto inv_disp;
		8168
		8169	if (S_IS_LOCAL (exp->X_add_symbol)
		8170	&& S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
		8171	&& S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
		8172	section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
		8173	exp->X_op = O_subtract;
		8174	exp->X_op_symbol = GOT_symbol;
		8175	if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
		8176	i.reloc[this_operand] = BFD_RELOC_32_PCREL;
		8177	else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
		8178	i.reloc[this_operand] = BFD_RELOC_64;
		8179	else
		8180	i.reloc[this_operand] = BFD_RELOC_32;
		8181	}
		8182
		8183	else if (exp->X_op == O_absent
		8184	\|\| exp->X_op == O_illegal
		8185	\|\| exp->X_op == O_big)
		8186	{
		8187	inv_disp:
		8188	as_bad (_("missing or invalid displacement expression `%s'"),
		8189	disp_start);
		8190	ret = 0;
		8191	}
		8192
		8193	else if (flag_code == CODE_64BIT
		8194	&& !i.prefix[ADDR_PREFIX]
		8195	&& exp->X_op == O_constant)
		8196	{
		8197	/* Since displacement is signed extended to 64bit, don't allow
		8198	disp32 and turn off disp32s if they are out of range. */
		8199	i.types[this_operand].bitfield.disp32 = 0;
		8200	if (!fits_in_signed_long (exp->X_add_number))
		8201	{
		8202	i.types[this_operand].bitfield.disp32s = 0;
		8203	if (i.types[this_operand].bitfield.baseindex)
		8204	{
		8205	as_bad (_("0x%lx out range of signed 32bit displacement"),
		8206	(long) exp->X_add_number);
		8207	ret = 0;
		8208	}
		8209	}
		8210	}
		8211
		8212	#if (defined (OBJ_AOUT) \|\| defined (OBJ_MAYBE_AOUT))
		8213	else if (exp->X_op != O_constant
		8214	&& OUTPUT_FLAVOR == bfd_target_aout_flavour
		8215	&& exp_seg != absolute_section
		8216	&& exp_seg != text_section
		8217	&& exp_seg != data_section
		8218	&& exp_seg != bss_section
		8219	&& exp_seg != undefined_section
		8220	&& !bfd_is_com_section (exp_seg))
		8221	{
		8222	as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
		8223	ret = 0;
		8224	}
		8225	#endif
		8226
		8227	/* Check if this is a displacement only operand. */
		8228	bigdisp = i.types[this_operand];
		8229	bigdisp.bitfield.disp8 = 0;
		8230	bigdisp.bitfield.disp16 = 0;
		8231	bigdisp.bitfield.disp32 = 0;
		8232	bigdisp.bitfield.disp32s = 0;
		8233	bigdisp.bitfield.disp64 = 0;
		8234	if (operand_type_all_zero (&bigdisp))
		8235	i.types[this_operand] = operand_type_and (i.types[this_operand],
		8236	types);
		8237
		8238	return ret;
		8239	}
		8240
		8241	/* Make sure the memory operand we've been dealt is valid.
		8242	Return 1 on success, 0 on a failure. */
		8243
		8244	static int
		8245	i386_index_check (const char *operand_string)
		8246	{
		8247	const char *kind = "base/index";
		8248	enum flag_code addr_mode;
		8249
		8250	if (i.prefix[ADDR_PREFIX])
		8251	addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
		8252	else
		8253	{
		8254	addr_mode = flag_code;
		8255
		8256	#if INFER_ADDR_PREFIX
		8257	if (i.mem_operands == 0)
		8258	{
		8259	/* Infer address prefix from the first memory operand. */
		8260	const reg_entry *addr_reg = i.base_reg;
		8261
		8262	if (addr_reg == NULL)
		8263	addr_reg = i.index_reg;
		8264
		8265	if (addr_reg)
		8266	{
		8267	if (addr_reg->reg_num == RegEip
		8268	\|\| addr_reg->reg_num == RegEiz
		8269	\|\| addr_reg->reg_type.bitfield.reg32)
		8270	addr_mode = CODE_32BIT;
		8271	else if (flag_code != CODE_64BIT
		8272	&& addr_reg->reg_type.bitfield.reg16)
		8273	addr_mode = CODE_16BIT;
		8274
		8275	if (addr_mode != flag_code)
		8276	{
		8277	i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
		8278	i.prefixes += 1;
		8279	/* Change the size of any displacement too. At most one
		8280	of Disp16 or Disp32 is set.
		8281	FIXME. There doesn't seem to be any real need for
		8282	separate Disp16 and Disp32 flags. The same goes for
		8283	Imm16 and Imm32. Removing them would probably clean
		8284	up the code quite a lot. */
		8285	if (flag_code != CODE_64BIT
		8286	&& (i.types[this_operand].bitfield.disp16
		8287	\|\| i.types[this_operand].bitfield.disp32))
		8288	i.types[this_operand]
		8289	= operand_type_xor (i.types[this_operand], disp16_32);
		8290	}
		8291	}
		8292	}
		8293	#endif
		8294	}
		8295
		8296	if (current_templates->start->opcode_modifier.isstring
		8297	&& !current_templates->start->opcode_modifier.immext
		8298	&& (current_templates->end[-1].opcode_modifier.isstring
		8299	\|\| i.mem_operands))
		8300	{
		8301	/* Memory operands of string insns are special in that they only allow
		8302	a single register (rDI, rSI, or rBX) as their memory address. */
		8303	const reg_entry *expected_reg;
		8304	static const char *di_si[][2] =
		8305	{
		8306	{ "esi", "edi" },
		8307	{ "si", "di" },
		8308	{ "rsi", "rdi" }
		8309	};
		8310	static const char *bx[] = { "ebx", "bx", "rbx" };
		8311
		8312	kind = "string address";
		8313
		8314	if (current_templates->start->opcode_modifier.w)
		8315	{
		8316	i386_operand_type type = current_templates->end[-1].operand_types[0];
		8317
		8318	if (!type.bitfield.baseindex
		8319	\|\| ((!i.mem_operands != !intel_syntax)
		8320	&& current_templates->end[-1].operand_types[1]
		8321	.bitfield.baseindex))
		8322	type = current_templates->end[-1].operand_types[1];
		8323	expected_reg = hash_find (reg_hash,
		8324	di_si[addr_mode][type.bitfield.esseg]);
		8325
		8326	}
		8327	else
		8328	expected_reg = hash_find (reg_hash, bx[addr_mode]);
		8329
		8330	if (i.base_reg != expected_reg
		8331	\|\| i.index_reg
		8332	\|\| operand_type_check (i.types[this_operand], disp))
		8333	{
		8334	/* The second memory operand must have the same size as
		8335	the first one. */
		8336	if (i.mem_operands
		8337	&& i.base_reg
		8338	&& !((addr_mode == CODE_64BIT
		8339	&& i.base_reg->reg_type.bitfield.reg64)
		8340	\|\| (addr_mode == CODE_32BIT
		8341	? i.base_reg->reg_type.bitfield.reg32
		8342	: i.base_reg->reg_type.bitfield.reg16)))
		8343	goto bad_address;
		8344
		8345	as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
		8346	operand_string,
		8347	intel_syntax ? '[' : '(',
		8348	register_prefix,
		8349	expected_reg->reg_name,
		8350	intel_syntax ? ']' : ')');
		8351	return 1;
		8352	}
		8353	else
		8354	return 1;
		8355
		8356	bad_address:
		8357	as_bad (_("`%s' is not a valid %s expression"),
		8358	operand_string, kind);
		8359	return 0;
		8360	}
		8361	else
		8362	{
		8363	if (addr_mode != CODE_16BIT)
		8364	{
		8365	/* 32-bit/64-bit checks. */
		8366	if ((i.base_reg
		8367	&& (addr_mode == CODE_64BIT
		8368	? !i.base_reg->reg_type.bitfield.reg64
		8369	: !i.base_reg->reg_type.bitfield.reg32)
		8370	&& (i.index_reg
		8371	\|\| (i.base_reg->reg_num
		8372	!= (addr_mode == CODE_64BIT ? RegRip : RegEip))))
		8373	\|\| (i.index_reg
		8374	&& !i.index_reg->reg_type.bitfield.regxmm
		8375	&& !i.index_reg->reg_type.bitfield.regymm
		8376	&& !i.index_reg->reg_type.bitfield.regzmm
		8377	&& ((addr_mode == CODE_64BIT
		8378	? !(i.index_reg->reg_type.bitfield.reg64
		8379	\|\| i.index_reg->reg_num == RegRiz)
		8380	: !(i.index_reg->reg_type.bitfield.reg32
		8381	\|\| i.index_reg->reg_num == RegEiz))
		8382	\|\| !i.index_reg->reg_type.bitfield.baseindex)))
		8383	goto bad_address;
		8384	}
		8385	else
		8386	{
		8387	/* 16-bit checks. */
		8388	if ((i.base_reg
		8389	&& (!i.base_reg->reg_type.bitfield.reg16
		8390	\|\| !i.base_reg->reg_type.bitfield.baseindex))
		8391	\|\| (i.index_reg
		8392	&& (!i.index_reg->reg_type.bitfield.reg16
		8393	\|\| !i.index_reg->reg_type.bitfield.baseindex
		8394	\|\| !(i.base_reg
		8395	&& i.base_reg->reg_num < 6
		8396	&& i.index_reg->reg_num >= 6
		8397	&& i.log2_scale_factor == 0))))
		8398	goto bad_address;
		8399	}
		8400	}
		8401	return 1;
		8402	}
		8403
		8404	/* Handle vector immediates. */
		8405
		8406	static int
		8407	RC_SAE_immediate (const char *imm_start)
		8408	{
		8409	unsigned int match_found, j;
		8410	const char *pstr = imm_start;
		8411	expressionS *exp;
		8412
		8413	if (*pstr != '{')
		8414	return 0;
		8415
		8416	pstr++;
		8417	match_found = 0;
		8418	for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
		8419	{
		8420	if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
		8421	{
		8422	if (!i.rounding)
		8423	{
		8424	rc_op.type = RC_NamesTable[j].type;
		8425	rc_op.operand = this_operand;
		8426	i.rounding = &rc_op;
		8427	}
		8428	else
		8429	{
		8430	as_bad (_("duplicated `%s'"), imm_start);
		8431	return 0;
		8432	}
		8433	pstr += RC_NamesTable[j].len;
		8434	match_found = 1;
		8435	break;
		8436	}
		8437	}
		8438	if (!match_found)
		8439	return 0;
		8440
		8441	if (*pstr++ != '}')
		8442	{
		8443	as_bad (_("Missing '}': '%s'"), imm_start);
		8444	return 0;
		8445	}
		8446	/* RC/SAE immediate string should contain nothing more. */;
		8447	if (*pstr != 0)
		8448	{
		8449	as_bad (_("Junk after '}': '%s'"), imm_start);
		8450	return 0;
		8451	}
		8452
		8453	exp = &im_expressions[i.imm_operands++];
		8454	i.op[this_operand].imms = exp;
		8455
		8456	exp->X_op = O_constant;
		8457	exp->X_add_number = 0;
		8458	exp->X_add_symbol = (symbolS *) 0;
		8459	exp->X_op_symbol = (symbolS *) 0;
		8460
		8461	i.types[this_operand].bitfield.imm8 = 1;
		8462	return 1;
		8463	}
		8464
		8465	/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
		8466	on error. */
		8467
		8468	static int
		8469	i386_att_operand (char *operand_string)
		8470	{
		8471	const reg_entry *r;
		8472	char *end_op;
		8473	char *op_string = operand_string;
		8474
		8475	if (is_space_char (*op_string))
		8476	++op_string;
		8477
		8478	/* We check for an absolute prefix (differentiating,
		8479	for example, 'jmp pc_relative_label' from 'jmp absolute_label'. /
		8480	if (*op_string == ABSOLUTE_PREFIX)
		8481	{
		8482	++op_string;
		8483	if (is_space_char (*op_string))
		8484	++op_string;
		8485	i.types[this_operand].bitfield.jumpabsolute = 1;
		8486	}
		8487
		8488	/* Check if operand is a register. */
		8489	if ((r = parse_register (op_string, &end_op)) != NULL)
		8490	{
		8491	i386_operand_type temp;
		8492
		8493	/* Check for a segment override by searching for ':' after a
		8494	segment register. */
		8495	op_string = end_op;
		8496	if (is_space_char (*op_string))
		8497	++op_string;
		8498	if (*op_string == ':'
		8499	&& (r->reg_type.bitfield.sreg2
		8500	\|\| r->reg_type.bitfield.sreg3))
		8501	{
		8502	switch (r->reg_num)
		8503	{
		8504	case 0:
		8505	i.seg[i.mem_operands] = &es;
		8506	break;
		8507	case 1:
		8508	i.seg[i.mem_operands] = &cs;
		8509	break;
		8510	case 2:
		8511	i.seg[i.mem_operands] = &ss;
		8512	break;
		8513	case 3:
		8514	i.seg[i.mem_operands] = &ds;
		8515	break;
		8516	case 4:
		8517	i.seg[i.mem_operands] = &fs;
		8518	break;
		8519	case 5:
		8520	i.seg[i.mem_operands] = &gs;
		8521	break;
		8522	}
		8523
		8524	/* Skip the ':' and whitespace. */
		8525	++op_string;
		8526	if (is_space_char (*op_string))
		8527	++op_string;
		8528
		8529	if (!is_digit_char (*op_string)
		8530	&& !is_identifier_char (*op_string)
		8531	&& *op_string != '('
		8532	&& *op_string != ABSOLUTE_PREFIX)
		8533	{
		8534	as_bad (_("bad memory operand `%s'"), op_string);
		8535	return 0;
		8536	}
		8537	/* Handle case of %es:foo. /
		8538	if (*op_string == ABSOLUTE_PREFIX)
		8539	{
		8540	++op_string;
		8541	if (is_space_char (*op_string))
		8542	++op_string;
		8543	i.types[this_operand].bitfield.jumpabsolute = 1;
		8544	}
		8545	goto do_memory_reference;
		8546	}
		8547
		8548	/* Handle vector operations. */
		8549	if (*op_string == '{')
		8550	{
		8551	op_string = check_VecOperations (op_string, NULL);
		8552	if (op_string == NULL)
		8553	return 0;
		8554	}
		8555
		8556	if (*op_string)
		8557	{
		8558	as_bad (_("junk `%s' after register"), op_string);
		8559	return 0;
		8560	}
		8561	temp = r->reg_type;
		8562	temp.bitfield.baseindex = 0;
		8563	i.types[this_operand] = operand_type_or (i.types[this_operand],
		8564	temp);
		8565	i.types[this_operand].bitfield.unspecified = 0;
		8566	i.op[this_operand].regs = r;
		8567	i.reg_operands++;
		8568	}
		8569	else if (*op_string == REGISTER_PREFIX)
		8570	{
		8571	as_bad (_("bad register name `%s'"), op_string);
		8572	return 0;
		8573	}
		8574	else if (*op_string == IMMEDIATE_PREFIX)
		8575	{
		8576	++op_string;
		8577	if (i.types[this_operand].bitfield.jumpabsolute)
		8578	{
		8579	as_bad (_("immediate operand illegal with absolute jump"));
		8580	return 0;
		8581	}
		8582	if (!i386_immediate (op_string))
		8583	return 0;
		8584	}
		8585	else if (RC_SAE_immediate (operand_string))
		8586	{
		8587	/* If it is a RC or SAE immediate, do nothing. */
		8588	;
		8589	}
		8590	else if (is_digit_char (*op_string)
		8591	\|\| is_identifier_char (*op_string)
		8592	\|\| *op_string == '(')
		8593	{
		8594	/* This is a memory reference of some sort. */
		8595	char *base_string;
		8596
		8597	/* Start and end of displacement string expression (if found). */
		8598	char *displacement_string_start;
		8599	char *displacement_string_end;
		8600	char *vop_start;
		8601
		8602	do_memory_reference:
		8603	if ((i.mem_operands == 1
		8604	&& !current_templates->start->opcode_modifier.isstring)
		8605	\|\| i.mem_operands == 2)
		8606	{
		8607	as_bad (_("too many memory references for `%s'"),
		8608	current_templates->start->name);
		8609	return 0;
		8610	}
		8611
		8612	/* Check for base index form. We detect the base index form by
		8613	looking for an ')' at the end of the operand, searching
		8614	for the '(' matching it, and finding a REGISTER_PREFIX or ','
		8615	after the '('. */
		8616	base_string = op_string + strlen (op_string);
		8617
		8618	/* Handle vector operations. */
		8619	vop_start = strchr (op_string, '{');
		8620	if (vop_start && vop_start < base_string)
		8621	{
		8622	if (check_VecOperations (vop_start, base_string) == NULL)
		8623	return 0;
		8624	base_string = vop_start;
		8625	}
		8626
		8627	--base_string;
		8628	if (is_space_char (*base_string))
		8629	--base_string;
		8630
		8631	/* If we only have a displacement, set-up for it to be parsed later. */
		8632	displacement_string_start = op_string;
		8633	displacement_string_end = base_string + 1;
		8634
		8635	if (*base_string == ')')
		8636	{
		8637	char *temp_string;
		8638	unsigned int parens_balanced = 1;
		8639	/* We've already checked that the number of left & right ()'s are
		8640	equal, so this loop will not be infinite. */
		8641	do
		8642	{
		8643	base_string--;
		8644	if (*base_string == ')')
		8645	parens_balanced++;
		8646	if (*base_string == '(')
		8647	parens_balanced--;
		8648	}
		8649	while (parens_balanced);
		8650
		8651	temp_string = base_string;
		8652
		8653	/* Skip past '(' and whitespace. */
		8654	++base_string;
		8655	if (is_space_char (*base_string))
		8656	++base_string;
		8657
		8658	if (*base_string == ','
		8659	\|\| ((i.base_reg = parse_register (base_string, &end_op))
		8660	!= NULL))
		8661	{
		8662	displacement_string_end = temp_string;
		8663
		8664	i.types[this_operand].bitfield.baseindex = 1;
		8665
		8666	if (i.base_reg)
		8667	{
		8668	base_string = end_op;
		8669	if (is_space_char (*base_string))
		8670	++base_string;
		8671	}
		8672
		8673	/* There may be an index reg or scale factor here. */
		8674	if (*base_string == ',')
		8675	{
		8676	++base_string;
		8677	if (is_space_char (*base_string))
		8678	++base_string;
		8679
		8680	if ((i.index_reg = parse_register (base_string, &end_op))
		8681	!= NULL)
		8682	{
		8683	base_string = end_op;
		8684	if (is_space_char (*base_string))
		8685	++base_string;
		8686	if (*base_string == ',')
		8687	{
		8688	++base_string;
		8689	if (is_space_char (*base_string))
		8690	++base_string;
		8691	}
		8692	else if (*base_string != ')')
		8693	{
		8694	as_bad (_("expecting `,' or `)' "
		8695	"after index register in `%s'"),
		8696	operand_string);
		8697	return 0;
		8698	}
		8699	}
		8700	else if (*base_string == REGISTER_PREFIX)
		8701	{
		8702	end_op = strchr (base_string, ',');
		8703	if (end_op)
		8704	*end_op = '\0';
		8705	as_bad (_("bad register name `%s'"), base_string);
		8706	return 0;
		8707	}
		8708
		8709	/* Check for scale factor. */
		8710	if (*base_string != ')')
		8711	{
		8712	char *end_scale = i386_scale (base_string);
		8713
		8714	if (!end_scale)
		8715	return 0;
		8716
		8717	base_string = end_scale;
		8718	if (is_space_char (*base_string))
		8719	++base_string;
		8720	if (*base_string != ')')
		8721	{
		8722	as_bad (_("expecting `)' "
		8723	"after scale factor in `%s'"),
		8724	operand_string);
		8725	return 0;
		8726	}
		8727	}
		8728	else if (!i.index_reg)
		8729	{
		8730	as_bad (_("expecting index register or scale factor "
		8731	"after `,'; got '%c'"),
		8732	*base_string);
		8733	return 0;
		8734	}
		8735	}
		8736	else if (*base_string != ')')
		8737	{
		8738	as_bad (_("expecting `,' or `)' "
		8739	"after base register in `%s'"),
		8740	operand_string);
		8741	return 0;
		8742	}
		8743	}
		8744	else if (*base_string == REGISTER_PREFIX)
		8745	{
		8746	end_op = strchr (base_string, ',');
		8747	if (end_op)
		8748	*end_op = '\0';
		8749	as_bad (_("bad register name `%s'"), base_string);
		8750	return 0;
		8751	}
		8752	}
		8753
		8754	/* If there's an expression beginning the operand, parse it,
		8755	assuming displacement_string_start and
		8756	displacement_string_end are meaningful. */
		8757	if (displacement_string_start != displacement_string_end)
		8758	{
		8759	if (!i386_displacement (displacement_string_start,
		8760	displacement_string_end))
		8761	return 0;
		8762	}
		8763
		8764	/* Special case for (%dx) while doing input/output op. */
		8765	if (i.base_reg
		8766	&& operand_type_equal (&i.base_reg->reg_type,
		8767	®16_inoutportreg)
		8768	&& i.index_reg == 0
		8769	&& i.log2_scale_factor == 0
		8770	&& i.seg[i.mem_operands] == 0
		8771	&& !operand_type_check (i.types[this_operand], disp))
		8772	{
		8773	i.types[this_operand] = inoutportreg;
		8774	return 1;
		8775	}
		8776
		8777	if (i386_index_check (operand_string) == 0)
		8778	return 0;
		8779	i.types[this_operand].bitfield.mem = 1;
		8780	i.mem_operands++;
		8781	}
		8782	else
		8783	{
		8784	/* It's not a memory operand; argh! */
		8785	as_bad (_("invalid char %s beginning operand %d `%s'"),
		8786	output_invalid (*op_string),
		8787	this_operand + 1,
		8788	op_string);
		8789	return 0;
		8790	}
		8791	return 1; /* Normal return. */
		8792	}
		8793
		8794	/* Calculate the maximum variable size (i.e., excluding fr_fix)
		8795	that an rs_machine_dependent frag may reach. */
		8796
		8797	unsigned int
		8798	i386_frag_max_var (fragS *frag)
		8799	{
		8800	/* The only relaxable frags are for jumps.
		8801	Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
		8802	gas_assert (frag->fr_type == rs_machine_dependent);
		8803	return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
		8804	}
		8805
		8806	/* md_estimate_size_before_relax()
		8807
		8808	Called just before relax() for rs_machine_dependent frags. The x86
		8809	assembler uses these frags to handle variable size jump
		8810	instructions.
		8811
		8812	Any symbol that is now undefined will not become defined.
		8813	Return the correct fr_subtype in the frag.
		8814	Return the initial "guess for variable size of frag" to caller.
		8815	The guess is actually the growth beyond the fixed part. Whatever
		8816	we do to grow the fixed or variable part contributes to our
		8817	returned value. */
		8818
		8819	int
		8820	md_estimate_size_before_relax (fragS *fragP, segT segment)
		8821	{
		8822	/* We've already got fragP->fr_subtype right; all we have to do is
		8823	check for un-relaxable symbols. On an ELF system, we can't relax
		8824	an externally visible symbol, because it may be overridden by a
		8825	shared library. */
		8826	if (S_GET_SEGMENT (fragP->fr_symbol) != segment
		8827	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		8828	\|\| (IS_ELF
		8829	&& (S_IS_EXTERNAL (fragP->fr_symbol)
		8830	\|\| S_IS_WEAK (fragP->fr_symbol)
		8831	\|\| ((symbol_get_bfdsym (fragP->fr_symbol)->flags
		8832	& BSF_GNU_INDIRECT_FUNCTION))))
		8833	#endif
		8834	#if defined (OBJ_COFF) && defined (TE_PE)
		8835	\|\| (OUTPUT_FLAVOR == bfd_target_coff_flavour
		8836	&& S_IS_WEAK (fragP->fr_symbol))
		8837	#endif
		8838	)
		8839	{
		8840	/* Symbol is undefined in this segment, or we need to keep a
		8841	reloc so that weak symbols can be overridden. */
		8842	int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
		8843	enum bfd_reloc_code_real reloc_type;
		8844	unsigned char *opcode;
		8845	int old_fr_fix;
		8846
		8847	if (fragP->fr_var != NO_RELOC)
		8848	reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
		8849	else if (size == 2)
		8850	reloc_type = BFD_RELOC_16_PCREL;
		8851	else
		8852	reloc_type = BFD_RELOC_32_PCREL;
		8853
		8854	old_fr_fix = fragP->fr_fix;
		8855	opcode = (unsigned char *) fragP->fr_opcode;
		8856
		8857	switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
		8858	{
		8859	case UNCOND_JUMP:
		8860	/* Make jmp (0xeb) a (d)word displacement jump. */
		8861	opcode[0] = 0xe9;
		8862	fragP->fr_fix += size;
		8863	fix_new (fragP, old_fr_fix, size,
		8864	fragP->fr_symbol,
		8865	fragP->fr_offset, 1,
		8866	reloc_type);
		8867	break;
		8868
		8869	case COND_JUMP86:
		8870	if (size == 2
		8871	&& (!no_cond_jump_promotion \|\| fragP->fr_var != NO_RELOC))
		8872	{
		8873	/* Negate the condition, and branch past an
		8874	unconditional jump. */
		8875	opcode[0] ^= 1;
		8876	opcode[1] = 3;
		8877	/* Insert an unconditional jump. */
		8878	opcode[2] = 0xe9;
		8879	/* We added two extra opcode bytes, and have a two byte
		8880	offset. */
		8881	fragP->fr_fix += 2 + 2;
		8882	fix_new (fragP, old_fr_fix + 2, 2,
		8883	fragP->fr_symbol,
		8884	fragP->fr_offset, 1,
		8885	reloc_type);
		8886	break;
		8887	}
		8888	/* Fall through. */
		8889
		8890	case COND_JUMP:
		8891	if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
		8892	{
		8893	fixS *fixP;
		8894
		8895	fragP->fr_fix += 1;
		8896	fixP = fix_new (fragP, old_fr_fix, 1,
		8897	fragP->fr_symbol,
		8898	fragP->fr_offset, 1,
		8899	BFD_RELOC_8_PCREL);
		8900	fixP->fx_signed = 1;
		8901	break;
		8902	}
		8903
		8904	/* This changes the byte-displacement jump 0x7N
		8905	to the (d)word-displacement jump 0x0f,0x8N. */
		8906	opcode[1] = opcode[0] + 0x10;
		8907	opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
		8908	/* We've added an opcode byte. */
		8909	fragP->fr_fix += 1 + size;
		8910	fix_new (fragP, old_fr_fix + 1, size,
		8911	fragP->fr_symbol,
		8912	fragP->fr_offset, 1,
		8913	reloc_type);
		8914	break;
		8915
		8916	default:
		8917	BAD_CASE (fragP->fr_subtype);
		8918	break;
		8919	}
		8920	frag_wane (fragP);
		8921	return fragP->fr_fix - old_fr_fix;
		8922	}
		8923
		8924	/* Guess size depending on current relax state. Initially the relax
		8925	state will correspond to a short jump and we return 1, because
		8926	the variable part of the frag (the branch offset) is one byte
		8927	long. However, we can relax a section more than once and in that
		8928	case we must either set fr_subtype back to the unrelaxed state,
		8929	or return the value for the appropriate branch. */
		8930	return md_relax_table[fragP->fr_subtype].rlx_length;
		8931	}
		8932
		8933	/* Called after relax() is finished.
		8934
		8935	In: Address of frag.
		8936	fr_type == rs_machine_dependent.
		8937	fr_subtype is what the address relaxed to.
		8938
		8939	Out: Any fixSs and constants are set up.
		8940	Caller will turn frag into a ".space 0". */
		8941
		8942	void
		8943	md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
		8944	fragS *fragP)
		8945	{
		8946	unsigned char *opcode;
		8947	unsigned char *where_to_put_displacement = NULL;
		8948	offsetT target_address;
		8949	offsetT opcode_address;
		8950	unsigned int extension = 0;
		8951	offsetT displacement_from_opcode_start;
		8952
		8953	opcode = (unsigned char *) fragP->fr_opcode;
		8954
		8955	/* Address we want to reach in file space. */
		8956	target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
		8957
		8958	/* Address opcode resides at in file space. */
		8959	opcode_address = fragP->fr_address + fragP->fr_fix;
		8960
		8961	/* Displacement from opcode start to fill into instruction. */
		8962	displacement_from_opcode_start = target_address - opcode_address;
		8963
		8964	if ((fragP->fr_subtype & BIG) == 0)
		8965	{
		8966	/* Don't have to change opcode. */
		8967	extension = 1; /* 1 opcode + 1 displacement */
		8968	where_to_put_displacement = &opcode[1];
		8969	}
		8970	else
		8971	{
		8972	if (no_cond_jump_promotion
		8973	&& TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
		8974	as_warn_where (fragP->fr_file, fragP->fr_line,
		8975	_("long jump required"));
		8976
		8977	switch (fragP->fr_subtype)
		8978	{
		8979	case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
		8980	extension = 4; /* 1 opcode + 4 displacement */
		8981	opcode[0] = 0xe9;
		8982	where_to_put_displacement = &opcode[1];
		8983	break;
		8984
		8985	case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
		8986	extension = 2; /* 1 opcode + 2 displacement */
		8987	opcode[0] = 0xe9;
		8988	where_to_put_displacement = &opcode[1];
		8989	break;
		8990
		8991	case ENCODE_RELAX_STATE (COND_JUMP, BIG):
		8992	case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
		8993	extension = 5; /* 2 opcode + 4 displacement */
		8994	opcode[1] = opcode[0] + 0x10;
		8995	opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
		8996	where_to_put_displacement = &opcode[2];
		8997	break;
		8998
		8999	case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
		9000	extension = 3; /* 2 opcode + 2 displacement */
		9001	opcode[1] = opcode[0] + 0x10;
		9002	opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
		9003	where_to_put_displacement = &opcode[2];
		9004	break;
		9005
		9006	case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
		9007	extension = 4;
		9008	opcode[0] ^= 1;
		9009	opcode[1] = 3;
		9010	opcode[2] = 0xe9;
		9011	where_to_put_displacement = &opcode[3];
		9012	break;
		9013
		9014	default:
		9015	BAD_CASE (fragP->fr_subtype);
		9016	break;
		9017	}
		9018	}
		9019
		9020	/* If size if less then four we are sure that the operand fits,
		9021	but if it's 4, then it could be that the displacement is larger
		9022	then -/+ 2GB. */
		9023	if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
		9024	&& object_64bit
		9025	&& ((addressT) (displacement_from_opcode_start - extension
		9026	+ ((addressT) 1 << 31))
		9027	> (((addressT) 2 << 31) - 1)))
		9028	{
		9029	as_bad_where (fragP->fr_file, fragP->fr_line,
		9030	_("jump target out of range"));
		9031	/* Make us emit 0. */
		9032	displacement_from_opcode_start = extension;
		9033	}
		9034	/* Now put displacement after opcode. */
		9035	md_number_to_chars ((char *) where_to_put_displacement,
		9036	(valueT) (displacement_from_opcode_start - extension),
		9037	DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
		9038	fragP->fr_fix += extension;
		9039	}
		9040
		9041	/* Apply a fixup (fixP) to segment data, once it has been determined
		9042	by our caller that we have all the info we need to fix it up.
		9043
		9044	Parameter valP is the pointer to the value of the bits.
		9045
		9046	On the 386, immediates, displacements, and data pointers are all in
		9047	the same (little-endian) format, so we don't need to care about which
		9048	we are handling. */
		9049
		9050	void
		9051	md_apply_fix (fixS fixP, valueT valP, segT seg ATTRIBUTE_UNUSED)
		9052	{
		9053	char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
		9054	valueT value = *valP;
		9055
		9056	#if !defined (TE_Mach)
		9057	if (fixP->fx_pcrel)
		9058	{
		9059	switch (fixP->fx_r_type)
		9060	{
		9061	default:
		9062	break;
		9063
		9064	case BFD_RELOC_64:
		9065	fixP->fx_r_type = BFD_RELOC_64_PCREL;
		9066	break;
		9067	case BFD_RELOC_32:
		9068	case BFD_RELOC_X86_64_32S:
		9069	fixP->fx_r_type = BFD_RELOC_32_PCREL;
		9070	break;
		9071	case BFD_RELOC_16:
		9072	fixP->fx_r_type = BFD_RELOC_16_PCREL;
		9073	break;
		9074	case BFD_RELOC_8:
		9075	fixP->fx_r_type = BFD_RELOC_8_PCREL;
		9076	break;
		9077	}
		9078	}
		9079
		9080	if (fixP->fx_addsy != NULL
		9081	&& (fixP->fx_r_type == BFD_RELOC_32_PCREL
		9082	\|\| fixP->fx_r_type == BFD_RELOC_64_PCREL
		9083	\|\| fixP->fx_r_type == BFD_RELOC_16_PCREL
		9084	\|\| fixP->fx_r_type == BFD_RELOC_8_PCREL
		9085	\|\| fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
		9086	&& !use_rela_relocations)
		9087	{
		9088	/* This is a hack. There should be a better way to handle this.
		9089	This covers for the fact that bfd_install_relocation will
		9090	subtract the current location (for partial_inplace, PC relative
		9091	relocations); see more below. */
		9092	#ifndef OBJ_AOUT
		9093	if (IS_ELF
		9094	#ifdef TE_PE
		9095	\|\| OUTPUT_FLAVOR == bfd_target_coff_flavour
		9096	#endif
		9097	)
		9098	value += fixP->fx_where + fixP->fx_frag->fr_address;
		9099	#endif
		9100	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9101	if (IS_ELF)
		9102	{
		9103	segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
		9104
		9105	if ((sym_seg == seg
		9106	\|\| (symbol_section_p (fixP->fx_addsy)
		9107	&& sym_seg != absolute_section))
		9108	&& !generic_force_reloc (fixP))
		9109	{
		9110	/* Yes, we add the values in twice. This is because
		9111	bfd_install_relocation subtracts them out again. I think
		9112	bfd_install_relocation is broken, but I don't dare change
		9113	it. FIXME. */
		9114	value += fixP->fx_where + fixP->fx_frag->fr_address;
		9115	}
		9116	}
		9117	#endif
		9118	#if defined (OBJ_COFF) && defined (TE_PE)
		9119	/* For some reason, the PE format does not store a
		9120	section address offset for a PC relative symbol. */
		9121	if (S_GET_SEGMENT (fixP->fx_addsy) != seg
		9122	\|\| S_IS_WEAK (fixP->fx_addsy))
		9123	value += md_pcrel_from (fixP);
		9124	#endif
		9125	}
		9126	#if defined (OBJ_COFF) && defined (TE_PE)
		9127	if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
		9128	{
		9129	value -= S_GET_VALUE (fixP->fx_addsy);
		9130	}
		9131	#endif
		9132
		9133	/* Fix a few things - the dynamic linker expects certain values here,
		9134	and we must not disappoint it. */
		9135	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9136	if (IS_ELF && fixP->fx_addsy)
		9137	switch (fixP->fx_r_type)
		9138	{
		9139	case BFD_RELOC_386_PLT32:
		9140	case BFD_RELOC_X86_64_PLT32:
		9141	case BFD_RELOC_X86_64_PLT32_BND:
		9142	/* Make the jump instruction point to the address of the operand. At
		9143	runtime we merely add the offset to the actual PLT entry. */
		9144	value = -4;
		9145	break;
		9146
		9147	case BFD_RELOC_386_TLS_GD:
		9148	case BFD_RELOC_386_TLS_LDM:
		9149	case BFD_RELOC_386_TLS_IE_32:
		9150	case BFD_RELOC_386_TLS_IE:
		9151	case BFD_RELOC_386_TLS_GOTIE:
		9152	case BFD_RELOC_386_TLS_GOTDESC:
		9153	case BFD_RELOC_X86_64_TLSGD:
		9154	case BFD_RELOC_X86_64_TLSLD:
		9155	case BFD_RELOC_X86_64_GOTTPOFF:
		9156	case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
		9157	value = 0; /* Fully resolved at runtime. No addend. */
		9158	/* Fallthrough */
		9159	case BFD_RELOC_386_TLS_LE:
		9160	case BFD_RELOC_386_TLS_LDO_32:
		9161	case BFD_RELOC_386_TLS_LE_32:
		9162	case BFD_RELOC_X86_64_DTPOFF32:
		9163	case BFD_RELOC_X86_64_DTPOFF64:
		9164	case BFD_RELOC_X86_64_TPOFF32:
		9165	case BFD_RELOC_X86_64_TPOFF64:
		9166	S_SET_THREAD_LOCAL (fixP->fx_addsy);
		9167	break;
		9168
		9169	case BFD_RELOC_386_TLS_DESC_CALL:
		9170	case BFD_RELOC_X86_64_TLSDESC_CALL:
		9171	value = 0; /* Fully resolved at runtime. No addend. */
		9172	S_SET_THREAD_LOCAL (fixP->fx_addsy);
		9173	fixP->fx_done = 0;
		9174	return;
		9175
		9176	case BFD_RELOC_386_GOT32:
		9177	case BFD_RELOC_X86_64_GOT32:
		9178	value = 0; /* Fully resolved at runtime. No addend. */
		9179	break;
		9180
		9181	case BFD_RELOC_VTABLE_INHERIT:
		9182	case BFD_RELOC_VTABLE_ENTRY:
		9183	fixP->fx_done = 0;
		9184	return;
		9185
		9186	default:
		9187	break;
		9188	}
		9189	#endif /* defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) */
		9190	*valP = value;
		9191	#endif /* !defined (TE_Mach) */
		9192
		9193	/* Are we finished with this relocation now? */
		9194	if (fixP->fx_addsy == NULL)
		9195	fixP->fx_done = 1;
		9196	#if defined (OBJ_COFF) && defined (TE_PE)
		9197	else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
		9198	{
		9199	fixP->fx_done = 0;
		9200	/* Remember value for tc_gen_reloc. */
		9201	fixP->fx_addnumber = value;
		9202	/* Clear out the frag for now. */
		9203	value = 0;
		9204	}
		9205	#endif
		9206	else if (use_rela_relocations)
		9207	{
		9208	fixP->fx_no_overflow = 1;
		9209	/* Remember value for tc_gen_reloc. */
		9210	fixP->fx_addnumber = value;
		9211	value = 0;
		9212	}
		9213
		9214	md_number_to_chars (p, value, fixP->fx_size);
		9215	}
		9216
		9217	char *
		9218	md_atof (int type, char litP, int sizeP)
		9219	{
		9220	/* This outputs the LITTLENUMs in REVERSE order;
		9221	in accord with the bigendian 386. */
		9222	return ieee_md_atof (type, litP, sizeP, FALSE);
		9223	}
		9224
		9225	static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
		9226
		9227	static char *
		9228	output_invalid (int c)
		9229	{
		9230	if (ISPRINT (c))
		9231	snprintf (output_invalid_buf, sizeof (output_invalid_buf),
		9232	"'%c'", c);
		9233	else
		9234	snprintf (output_invalid_buf, sizeof (output_invalid_buf),
		9235	"(0x%x)", (unsigned char) c);
		9236	return output_invalid_buf;
		9237	}
		9238
		9239	/* REG_STRING starts before REGISTER_PREFIX. */
		9240
		9241	static const reg_entry *
		9242	parse_real_register (char reg_string, char *end_op)
		9243	{
		9244	char *s = reg_string;
		9245	char *p;
		9246	char reg_name_given[MAX_REG_NAME_SIZE + 1];
		9247	const reg_entry *r;
		9248
		9249	/* Skip possible REGISTER_PREFIX and possible whitespace. */
		9250	if (*s == REGISTER_PREFIX)
		9251	++s;
		9252
		9253	if (is_space_char (*s))
		9254	++s;
		9255
		9256	p = reg_name_given;
		9257	while ((p++ = register_chars[(unsigned char) s]) != '\0')
		9258	{
		9259	if (p >= reg_name_given + MAX_REG_NAME_SIZE)
		9260	return (const reg_entry *) NULL;
		9261	s++;
		9262	}
		9263
		9264	/* For naked regs, make sure that we are not dealing with an identifier.
		9265	This prevents confusing an identifier like `eax_var' with register
		9266	`eax'. */
		9267	if (allow_naked_reg && identifier_chars[(unsigned char) *s])
		9268	return (const reg_entry *) NULL;
		9269
		9270	*end_op = s;
		9271
		9272	r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
		9273
		9274	/* Handle floating point regs, allowing spaces in the (i) part. */
		9275	if (r == i386_regtab /* %st is first entry of table */)
		9276	{
		9277	if (is_space_char (*s))
		9278	++s;
		9279	if (*s == '(')
		9280	{
		9281	++s;
		9282	if (is_space_char (*s))
		9283	++s;
		9284	if (s >= '0' && s <= '7')
		9285	{
		9286	int fpr = *s - '0';
		9287	++s;
		9288	if (is_space_char (*s))
		9289	++s;
		9290	if (*s == ')')
		9291	{
		9292	*end_op = s + 1;
		9293	r = (const reg_entry *) hash_find (reg_hash, "st(0)");
		9294	know (r);
		9295	return r + fpr;
		9296	}
		9297	}
		9298	/* We have "%st(" then garbage. */
		9299	return (const reg_entry *) NULL;
		9300	}
		9301	}
		9302
		9303	if (r == NULL \|\| allow_pseudo_reg)
		9304	return r;
		9305
		9306	if (operand_type_all_zero (&r->reg_type))
		9307	return (const reg_entry *) NULL;
		9308
		9309	if ((r->reg_type.bitfield.reg32
		9310	\|\| r->reg_type.bitfield.sreg3
		9311	\|\| r->reg_type.bitfield.control
		9312	\|\| r->reg_type.bitfield.debug
		9313	\|\| r->reg_type.bitfield.test)
		9314	&& !cpu_arch_flags.bitfield.cpui386)
		9315	return (const reg_entry *) NULL;
		9316
		9317	if (r->reg_type.bitfield.floatreg
		9318	&& !cpu_arch_flags.bitfield.cpu8087
		9319	&& !cpu_arch_flags.bitfield.cpu287
		9320	&& !cpu_arch_flags.bitfield.cpu387)
		9321	return (const reg_entry *) NULL;
		9322
		9323	if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
		9324	return (const reg_entry *) NULL;
		9325
		9326	if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
		9327	return (const reg_entry *) NULL;
		9328
		9329	if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
		9330	return (const reg_entry *) NULL;
		9331
		9332	if ((r->reg_type.bitfield.regzmm \|\| r->reg_type.bitfield.regmask)
		9333	&& !cpu_arch_flags.bitfield.cpuavx512f)
		9334	return (const reg_entry *) NULL;
		9335
		9336	/* Don't allow fake index register unless allow_index_reg isn't 0. */
		9337	if (!allow_index_reg
		9338	&& (r->reg_num == RegEiz \|\| r->reg_num == RegRiz))
		9339	return (const reg_entry *) NULL;
		9340
		9341	/* Upper 16 vector register is only available with VREX in 64bit
		9342	mode. */
		9343	if ((r->reg_flags & RegVRex))
		9344	{
		9345	if (!cpu_arch_flags.bitfield.cpuvrex
		9346	\|\| flag_code != CODE_64BIT)
		9347	return (const reg_entry *) NULL;
		9348
		9349	i.need_vrex = 1;
		9350	}
		9351
		9352	if (((r->reg_flags & (RegRex64 \| RegRex))
		9353	\|\| r->reg_type.bitfield.reg64)
		9354	&& (!cpu_arch_flags.bitfield.cpulm
		9355	\|\| !operand_type_equal (&r->reg_type, &control))
		9356	&& flag_code != CODE_64BIT)
		9357	return (const reg_entry *) NULL;
		9358
		9359	if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
		9360	return (const reg_entry *) NULL;
		9361
		9362	return r;
		9363	}
		9364
		9365	/* REG_STRING starts before REGISTER_PREFIX. */
		9366
		9367	static const reg_entry *
		9368	parse_register (char reg_string, char *end_op)
		9369	{
		9370	const reg_entry *r;
		9371
		9372	if (*reg_string == REGISTER_PREFIX \|\| allow_naked_reg)
		9373	r = parse_real_register (reg_string, end_op);
		9374	else
		9375	r = NULL;
		9376	if (!r)
		9377	{
		9378	char *save = input_line_pointer;
		9379	char c;
		9380	symbolS *symbolP;
		9381
		9382	input_line_pointer = reg_string;
		9383	c = get_symbol_end ();
		9384	symbolP = symbol_find (reg_string);
		9385	if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
		9386	{
		9387	const expressionS *e = symbol_get_value_expression (symbolP);
		9388
		9389	know (e->X_op == O_register);
		9390	know (e->X_add_number >= 0
		9391	&& (valueT) e->X_add_number < i386_regtab_size);
		9392	r = i386_regtab + e->X_add_number;
		9393	*end_op = input_line_pointer;
		9394	}
		9395	*input_line_pointer = c;
		9396	input_line_pointer = save;
		9397	}
		9398	return r;
		9399	}
		9400
		9401	int
		9402	i386_parse_name (char name, expressionS e, char *nextcharP)
		9403	{
		9404	const reg_entry *r;
		9405	char *end = input_line_pointer;
		9406
		9407	end = nextcharP;
		9408	r = parse_register (name, &input_line_pointer);
		9409	if (r && end <= input_line_pointer)
		9410	{
		9411	nextcharP = input_line_pointer;
		9412	*input_line_pointer = 0;
		9413	e->X_op = O_register;
		9414	e->X_add_number = r - i386_regtab;
		9415	return 1;
		9416	}
		9417	input_line_pointer = end;
		9418	*end = 0;
		9419	return intel_syntax ? i386_intel_parse_name (name, e) : 0;
		9420	}
		9421
		9422	void
		9423	md_operand (expressionS *e)
		9424	{
		9425	char *end;
		9426	const reg_entry *r;
		9427
		9428	switch (*input_line_pointer)
		9429	{
		9430	case REGISTER_PREFIX:
		9431	r = parse_real_register (input_line_pointer, &end);
		9432	if (r)
		9433	{
		9434	e->X_op = O_register;
		9435	e->X_add_number = r - i386_regtab;
		9436	input_line_pointer = end;
		9437	}
		9438	break;
		9439
		9440	case '[':
		9441	gas_assert (intel_syntax);
		9442	end = input_line_pointer++;
		9443	expression (e);
		9444	if (*input_line_pointer == ']')
		9445	{
		9446	++input_line_pointer;
		9447	e->X_op_symbol = make_expr_symbol (e);
		9448	e->X_add_symbol = NULL;
		9449	e->X_add_number = 0;
		9450	e->X_op = O_index;
		9451	}
		9452	else
		9453	{
		9454	e->X_op = O_absent;
		9455	input_line_pointer = end;
		9456	}
		9457	break;
		9458	}
		9459	}
		9460
		9461
		9462	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9463	const char *md_shortopts = "kVQ:sqn";
		9464	#else
		9465	const char *md_shortopts = "qn";
		9466	#endif
		9467
		9468	#define OPTION_32 (OPTION_MD_BASE + 0)
		9469	#define OPTION_64 (OPTION_MD_BASE + 1)
		9470	#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
		9471	#define OPTION_MARCH (OPTION_MD_BASE + 3)
		9472	#define OPTION_MTUNE (OPTION_MD_BASE + 4)
		9473	#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
		9474	#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
		9475	#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
		9476	#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
		9477	#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
		9478	#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
		9479	#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
		9480	#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
		9481	#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
		9482	#define OPTION_X32 (OPTION_MD_BASE + 14)
		9483	#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
		9484	#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
		9485	#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
		9486
		9487	struct option md_longopts[] =
		9488	{
		9489	{"32", no_argument, NULL, OPTION_32},
		9490	#if (defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) \
		9491	\|\| defined (TE_PE) \|\| defined (TE_PEP) \|\| defined (OBJ_MACH_O))
		9492	{"64", no_argument, NULL, OPTION_64},
		9493	#endif
		9494	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9495	{"x32", no_argument, NULL, OPTION_X32},
		9496	#endif
		9497	{"divide", no_argument, NULL, OPTION_DIVIDE},
		9498	{"march", required_argument, NULL, OPTION_MARCH},
		9499	{"mtune", required_argument, NULL, OPTION_MTUNE},
		9500	{"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
		9501	{"msyntax", required_argument, NULL, OPTION_MSYNTAX},
		9502	{"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
		9503	{"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
		9504	{"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
		9505	{"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
		9506	{"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
		9507	{"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
		9508	{"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
		9509	{"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
		9510	{"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
		9511	{"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
		9512	{NULL, no_argument, NULL, 0}
		9513	};
		9514	size_t md_longopts_size = sizeof (md_longopts);
		9515
		9516	int
		9517	md_parse_option (int c, char *arg)
		9518	{
		9519	unsigned int j;
		9520	char arch, next;
		9521
		9522	switch (c)
		9523	{
		9524	case 'n':
		9525	optimize_align_code = 0;
		9526	break;
		9527
		9528	case 'q':
		9529	quiet_warnings = 1;
		9530	break;
		9531
		9532	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9533	/* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
		9534	should be emitted or not. FIXME: Not implemented. */
		9535	case 'Q':
		9536	break;
		9537
		9538	/* -V: SVR4 argument to print version ID. */
		9539	case 'V':
		9540	print_version_id ();
		9541	break;
		9542
		9543	/* -k: Ignore for FreeBSD compatibility. */
		9544	case 'k':
		9545	break;
		9546
		9547	case 's':
		9548	/* -s: On i386 Solaris, this tells the native assembler to use
		9549	.stab instead of .stab.excl. We always use .stab anyhow. */
		9550	break;
		9551	#endif
		9552	#if (defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) \
		9553	\|\| defined (TE_PE) \|\| defined (TE_PEP) \|\| defined (OBJ_MACH_O))
		9554	case OPTION_64:
		9555	{
		9556	const char list, l;
		9557
		9558	list = bfd_target_list ();
		9559	for (l = list; *l != NULL; l++)
		9560	if (CONST_STRNEQ (*l, "elf64-x86-64")
		9561	\|\| strcmp (*l, "coff-x86-64") == 0
		9562	\|\| strcmp (*l, "pe-x86-64") == 0
		9563	\|\| strcmp (*l, "pei-x86-64") == 0
		9564	\|\| strcmp (*l, "mach-o-x86-64") == 0)
		9565	{
		9566	default_arch = "x86_64";
		9567	break;
		9568	}
		9569	if (*l == NULL)
		9570	as_fatal (_("no compiled in support for x86_64"));
		9571	free (list);
		9572	}
		9573	break;
		9574	#endif
		9575
		9576	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9577	case OPTION_X32:
		9578	if (IS_ELF)
		9579	{
		9580	const char list, l;
		9581
		9582	list = bfd_target_list ();
		9583	for (l = list; *l != NULL; l++)
		9584	if (CONST_STRNEQ (*l, "elf32-x86-64"))
		9585	{
		9586	default_arch = "x86_64:32";
		9587	break;
		9588	}
		9589	if (*l == NULL)
		9590	as_fatal (_("no compiled in support for 32bit x86_64"));
		9591	free (list);
		9592	}
		9593	else
		9594	as_fatal (_("32bit x86_64 is only supported for ELF"));
		9595	break;
		9596	#endif
		9597
		9598	case OPTION_32:
		9599	default_arch = "i386";
		9600	break;
		9601
		9602	case OPTION_DIVIDE:
		9603	#ifdef SVR4_COMMENT_CHARS
		9604	{
		9605	char n, t;
		9606	const char *s;
		9607
		9608	n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
		9609	t = n;
		9610	for (s = i386_comment_chars; *s != '\0'; s++)
		9611	if (*s != '/')
		9612	t++ = s;
		9613	*t = '\0';
		9614	i386_comment_chars = n;
		9615	}
		9616	#endif
		9617	break;
		9618
		9619	case OPTION_MARCH:
		9620	arch = xstrdup (arg);
		9621	do
		9622	{
		9623	if (*arch == '.')
		9624	as_fatal (_("invalid -march= option: `%s'"), arg);
		9625	next = strchr (arch, '+');
		9626	if (next)
		9627	*next++ = '\0';
		9628	for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
		9629	{
		9630	if (strcmp (arch, cpu_arch [j].name) == 0)
		9631	{
		9632	/* Processor. */
		9633	if (! cpu_arch[j].flags.bitfield.cpui386)
		9634	continue;
		9635
		9636	cpu_arch_name = cpu_arch[j].name;
		9637	cpu_sub_arch_name = NULL;
		9638	cpu_arch_flags = cpu_arch[j].flags;
		9639	cpu_arch_isa = cpu_arch[j].type;
		9640	cpu_arch_isa_flags = cpu_arch[j].flags;
		9641	if (!cpu_arch_tune_set)
		9642	{
		9643	cpu_arch_tune = cpu_arch_isa;
		9644	cpu_arch_tune_flags = cpu_arch_isa_flags;
		9645	}
		9646	break;
		9647	}
		9648	else if (*cpu_arch [j].name == '.'
		9649	&& strcmp (arch, cpu_arch [j].name + 1) == 0)
		9650	{
		9651	/* ISA entension. */
		9652	i386_cpu_flags flags;
		9653
		9654	if (!cpu_arch[j].negated)
		9655	flags = cpu_flags_or (cpu_arch_flags,
		9656	cpu_arch[j].flags);
		9657	else
		9658	flags = cpu_flags_and_not (cpu_arch_flags,
		9659	cpu_arch[j].flags);
		9660	if (!cpu_flags_equal (&flags, &cpu_arch_flags))
		9661	{
		9662	if (cpu_sub_arch_name)
		9663	{
		9664	char *name = cpu_sub_arch_name;
		9665	cpu_sub_arch_name = concat (name,
		9666	cpu_arch[j].name,
		9667	(const char *) NULL);
		9668	free (name);
		9669	}
		9670	else
		9671	cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
		9672	cpu_arch_flags = flags;
		9673	cpu_arch_isa_flags = flags;
		9674	}
		9675	break;
		9676	}
		9677	}
		9678
		9679	if (j >= ARRAY_SIZE (cpu_arch))
		9680	as_fatal (_("invalid -march= option: `%s'"), arg);
		9681
		9682	arch = next;
		9683	}
		9684	while (next != NULL );
		9685	break;
		9686
		9687	case OPTION_MTUNE:
		9688	if (*arg == '.')
		9689	as_fatal (_("invalid -mtune= option: `%s'"), arg);
		9690	for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
		9691	{
		9692	if (strcmp (arg, cpu_arch [j].name) == 0)
		9693	{
		9694	cpu_arch_tune_set = 1;
		9695	cpu_arch_tune = cpu_arch [j].type;
		9696	cpu_arch_tune_flags = cpu_arch[j].flags;
		9697	break;
		9698	}
		9699	}
		9700	if (j >= ARRAY_SIZE (cpu_arch))
		9701	as_fatal (_("invalid -mtune= option: `%s'"), arg);
		9702	break;
		9703
		9704	case OPTION_MMNEMONIC:
		9705	if (strcasecmp (arg, "att") == 0)
		9706	intel_mnemonic = 0;
		9707	else if (strcasecmp (arg, "intel") == 0)
		9708	intel_mnemonic = 1;
		9709	else
		9710	as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
		9711	break;
		9712
		9713	case OPTION_MSYNTAX:
		9714	if (strcasecmp (arg, "att") == 0)
		9715	intel_syntax = 0;
		9716	else if (strcasecmp (arg, "intel") == 0)
		9717	intel_syntax = 1;
		9718	else
		9719	as_fatal (_("invalid -msyntax= option: `%s'"), arg);
		9720	break;
		9721
		9722	case OPTION_MINDEX_REG:
		9723	allow_index_reg = 1;
		9724	break;
		9725
		9726	case OPTION_MNAKED_REG:
		9727	allow_naked_reg = 1;
		9728	break;
		9729
		9730	case OPTION_MOLD_GCC:
		9731	old_gcc = 1;
		9732	break;
		9733
		9734	case OPTION_MSSE2AVX:
		9735	sse2avx = 1;
		9736	break;
		9737
		9738	case OPTION_MSSE_CHECK:
		9739	if (strcasecmp (arg, "error") == 0)
		9740	sse_check = check_error;
		9741	else if (strcasecmp (arg, "warning") == 0)
		9742	sse_check = check_warning;
		9743	else if (strcasecmp (arg, "none") == 0)
		9744	sse_check = check_none;
		9745	else
		9746	as_fatal (_("invalid -msse-check= option: `%s'"), arg);
		9747	break;
		9748
		9749	case OPTION_MOPERAND_CHECK:
		9750	if (strcasecmp (arg, "error") == 0)
		9751	operand_check = check_error;
		9752	else if (strcasecmp (arg, "warning") == 0)
		9753	operand_check = check_warning;
		9754	else if (strcasecmp (arg, "none") == 0)
		9755	operand_check = check_none;
		9756	else
		9757	as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
		9758	break;
		9759
		9760	case OPTION_MAVXSCALAR:
		9761	if (strcasecmp (arg, "128") == 0)
		9762	avxscalar = vex128;
		9763	else if (strcasecmp (arg, "256") == 0)
		9764	avxscalar = vex256;
		9765	else
		9766	as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
		9767	break;
		9768
		9769	case OPTION_MADD_BND_PREFIX:
		9770	add_bnd_prefix = 1;
		9771	break;
		9772
		9773	case OPTION_MEVEXLIG:
		9774	if (strcmp (arg, "128") == 0)
		9775	evexlig = evexl128;
		9776	else if (strcmp (arg, "256") == 0)
		9777	evexlig = evexl256;
		9778	else if (strcmp (arg, "512") == 0)
		9779	evexlig = evexl512;
		9780	else
		9781	as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
		9782	break;
		9783
		9784	case OPTION_MEVEXWIG:
		9785	if (strcmp (arg, "0") == 0)
		9786	evexwig = evexw0;
		9787	else if (strcmp (arg, "1") == 0)
		9788	evexwig = evexw1;
		9789	else
		9790	as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
		9791	break;
		9792
		9793	default:
		9794	return 0;
		9795	}
		9796	return 1;
		9797	}
		9798
		9799	#define MESSAGE_TEMPLATE \
		9800	" "
		9801
		9802	static void
		9803	show_arch (FILE *stream, int ext, int check)
		9804	{
		9805	static char message[] = MESSAGE_TEMPLATE;
		9806	char *start = message + 27;
		9807	char *p;
		9808	int size = sizeof (MESSAGE_TEMPLATE);
		9809	int left;
		9810	const char *name;
		9811	int len;
		9812	unsigned int j;
		9813
		9814	p = start;
		9815	left = size - (start - message);
		9816	for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
		9817	{
		9818	/* Should it be skipped? */
		9819	if (cpu_arch [j].skip)
		9820	continue;
		9821
		9822	name = cpu_arch [j].name;
		9823	len = cpu_arch [j].len;
		9824	if (*name == '.')
		9825	{
		9826	/* It is an extension. Skip if we aren't asked to show it. */
		9827	if (ext)
		9828	{
		9829	name++;
		9830	len--;
		9831	}
		9832	else
		9833	continue;
		9834	}
		9835	else if (ext)
		9836	{
		9837	/* It is an processor. Skip if we show only extension. */
		9838	continue;
		9839	}
		9840	else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
		9841	{
		9842	/* It is an impossible processor - skip. */
		9843	continue;
		9844	}
		9845
		9846	/* Reserve 2 spaces for ", " or ",\0" */
		9847	left -= len + 2;
		9848
		9849	/* Check if there is any room. */
		9850	if (left >= 0)
		9851	{
		9852	if (p != start)
		9853	{
		9854	*p++ = ',';
		9855	*p++ = ' ';
		9856	}
		9857	p = mempcpy (p, name, len);
		9858	}
		9859	else
		9860	{
		9861	/* Output the current message now and start a new one. */
		9862	*p++ = ',';
		9863	*p = '\0';
		9864	fprintf (stream, "%s\n", message);
		9865	p = start;
		9866	left = size - (start - message) - len - 2;
		9867
		9868	gas_assert (left >= 0);
		9869
		9870	p = mempcpy (p, name, len);
		9871	}
		9872	}
		9873
		9874	*p = '\0';
		9875	fprintf (stream, "%s\n", message);
		9876	}
		9877
		9878	void
		9879	md_show_usage (FILE *stream)
		9880	{
		9881	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9882	fprintf (stream, _("\
		9883	-Q ignored\n\
		9884	-V print assembler version number\n\
		9885	-k ignored\n"));
		9886	#endif
		9887	fprintf (stream, _("\
		9888	-n Do not optimize code alignment\n\
		9889	-q quieten some warnings\n"));
		9890	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		9891	fprintf (stream, _("\
		9892	-s ignored\n"));
		9893	#endif
		9894	#if (defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) \
		9895	\|\| defined (TE_PE) \|\| defined (TE_PEP))
		9896	fprintf (stream, _("\
		9897	--32/--64/--x32 generate 32bit/64bit/x32 code\n"));
		9898	#endif
		9899	#ifdef SVR4_COMMENT_CHARS
		9900	fprintf (stream, _("\
		9901	--divide do not treat `/' as a comment character\n"));
		9902	#else
		9903	fprintf (stream, _("\
		9904	--divide ignored\n"));
		9905	#endif
		9906	fprintf (stream, _("\
		9907	-march=CPU[,+EXTENSION...]\n\
		9908	generate code for CPU and EXTENSION, CPU is one of:\n"));
		9909	show_arch (stream, 0, 1);
		9910	fprintf (stream, _("\
		9911	EXTENSION is combination of:\n"));
		9912	show_arch (stream, 1, 0);
		9913	fprintf (stream, _("\
		9914	-mtune=CPU optimize for CPU, CPU is one of:\n"));
		9915	show_arch (stream, 0, 0);
		9916	fprintf (stream, _("\
		9917	-msse2avx encode SSE instructions with VEX prefix\n"));
		9918	fprintf (stream, _("\
		9919	-msse-check=[none\|error\|warning]\n\
		9920	check SSE instructions\n"));
		9921	fprintf (stream, _("\
		9922	-moperand-check=[none\|error\|warning]\n\
		9923	check operand combinations for validity\n"));
		9924	fprintf (stream, _("\
		9925	-mavxscalar=[128\|256] encode scalar AVX instructions with specific vector\n\
		9926	length\n"));
		9927	fprintf (stream, _("\
		9928	-mevexlig=[128\|256\|512] encode scalar EVEX instructions with specific vector\n\
		9929	length\n"));
		9930	fprintf (stream, _("\
		9931	-mevexwig=[0\|1] encode EVEX instructions with specific EVEX.W value\n\
		9932	for EVEX.W bit ignored instructions\n"));
		9933	fprintf (stream, _("\
		9934	-mmnemonic=[att\|intel] use AT&T/Intel mnemonic\n"));
		9935	fprintf (stream, _("\
		9936	-msyntax=[att\|intel] use AT&T/Intel syntax\n"));
		9937	fprintf (stream, _("\
		9938	-mindex-reg support pseudo index registers\n"));
		9939	fprintf (stream, _("\
		9940	-mnaked-reg don't require `%%' prefix for registers\n"));
		9941	fprintf (stream, _("\
		9942	-mold-gcc support old (<= 2.8.1) versions of gcc\n"));
		9943	fprintf (stream, _("\
		9944	-madd-bnd-prefix add BND prefix for all valid branches\n"));
		9945	}
		9946
		9947	#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
		9948	\|\| defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF) \
		9949	\|\| defined (TE_PE) \|\| defined (TE_PEP) \|\| defined (OBJ_MACH_O))
		9950
		9951	/* Pick the target format to use. */
		9952
		9953	const char *
		9954	i386_target_format (void)
		9955	{
		9956	if (!strncmp (default_arch, "x86_64", 6))
		9957	{
		9958	update_code_flag (CODE_64BIT, 1);
		9959	if (default_arch[6] == '\0')
		9960	x86_elf_abi = X86_64_ABI;
		9961	else
		9962	x86_elf_abi = X86_64_X32_ABI;
		9963	}
		9964	else if (!strcmp (default_arch, "i386"))
		9965	update_code_flag (CODE_32BIT, 1);
		9966	else
		9967	as_fatal (_("unknown architecture"));
		9968
		9969	if (cpu_flags_all_zero (&cpu_arch_isa_flags))
		9970	cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
		9971	if (cpu_flags_all_zero (&cpu_arch_tune_flags))
		9972	cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
		9973
		9974	switch (OUTPUT_FLAVOR)
		9975	{
		9976	#if defined (OBJ_MAYBE_AOUT) \|\| defined (OBJ_AOUT)
		9977	case bfd_target_aout_flavour:
		9978	return AOUT_TARGET_FORMAT;
		9979	#endif
		9980	#if defined (OBJ_MAYBE_COFF) \|\| defined (OBJ_COFF)
		9981	# if defined (TE_PE) \|\| defined (TE_PEP)
		9982	case bfd_target_coff_flavour:
		9983	return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
		9984	# elif defined (TE_GO32)
		9985	case bfd_target_coff_flavour:
		9986	return "coff-go32";
		9987	# else
		9988	case bfd_target_coff_flavour:
		9989	return "coff-i386";
		9990	# endif
		9991	#endif
		9992	#if defined (OBJ_MAYBE_ELF) \|\| defined (OBJ_ELF)
		9993	case bfd_target_elf_flavour:
		9994	{
		9995	const char *format;
		9996
		9997	switch (x86_elf_abi)
		9998	{
		9999	default:
		10000	format = ELF_TARGET_FORMAT;
		10001	break;
		10002	case X86_64_ABI:
		10003	use_rela_relocations = 1;
		10004	object_64bit = 1;
		10005	format = ELF_TARGET_FORMAT64;
		10006	break;
		10007	case X86_64_X32_ABI:
		10008	use_rela_relocations = 1;
		10009	object_64bit = 1;
		10010	disallow_64bit_reloc = 1;
		10011	format = ELF_TARGET_FORMAT32;
		10012	break;
		10013	}
		10014	if (cpu_arch_isa == PROCESSOR_L1OM)
		10015	{
		10016	if (x86_elf_abi != X86_64_ABI)
		10017	as_fatal (_("Intel L1OM is 64bit only"));
		10018	return ELF_TARGET_L1OM_FORMAT;
		10019	}
		10020	if (cpu_arch_isa == PROCESSOR_K1OM)
		10021	{
		10022	if (x86_elf_abi != X86_64_ABI)
		10023	as_fatal (_("Intel K1OM is 64bit only"));
		10024	return ELF_TARGET_K1OM_FORMAT;
		10025	}
		10026	else
		10027	return format;
		10028	}
		10029	#endif
		10030	#if defined (OBJ_MACH_O)
		10031	case bfd_target_mach_o_flavour:
		10032	if (flag_code == CODE_64BIT)
		10033	{
		10034	use_rela_relocations = 1;
		10035	object_64bit = 1;
		10036	return "mach-o-x86-64";
		10037	}
		10038	else
		10039	return "mach-o-i386";
		10040	#endif
		10041	default:
		10042	abort ();
		10043	return NULL;
		10044	}
		10045	}
		10046
		10047	#endif /* OBJ_MAYBE_ more than one */
		10048
		10049	#if (defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF))
		10050	void
		10051	i386_elf_emit_arch_note (void)
		10052	{
		10053	if (IS_ELF && cpu_arch_name != NULL)
		10054	{
		10055	char *p;
		10056	asection *seg = now_seg;
		10057	subsegT subseg = now_subseg;
		10058	Elf_Internal_Note i_note;
		10059	Elf_External_Note e_note;
		10060	asection *note_secp;
		10061	int len;
		10062
		10063	/* Create the .note section. */
		10064	note_secp = subseg_new (".note", 0);
		10065	bfd_set_section_flags (stdoutput,
		10066	note_secp,
		10067	SEC_HAS_CONTENTS \| SEC_READONLY);
		10068
		10069	/* Process the arch string. */
		10070	len = strlen (cpu_arch_name);
		10071
		10072	i_note.namesz = len + 1;
		10073	i_note.descsz = 0;
		10074	i_note.type = NT_ARCH;
		10075	p = frag_more (sizeof (e_note.namesz));
		10076	md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
		10077	p = frag_more (sizeof (e_note.descsz));
		10078	md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
		10079	p = frag_more (sizeof (e_note.type));
		10080	md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
		10081	p = frag_more (len + 1);
		10082	strcpy (p, cpu_arch_name);
		10083
		10084	frag_align (2, 0, 0);
		10085
		10086	subseg_set (seg, subseg);
		10087	}
		10088	}
		10089	#endif
		10090
		10091	symbolS *
		10092	md_undefined_symbol (char *name)
		10093	{
		10094	if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
		10095	&& name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
		10096	&& name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
		10097	&& strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
		10098	{
		10099	if (!GOT_symbol)
		10100	{
		10101	if (symbol_find (name))
		10102	as_bad (_("GOT already in symbol table"));
		10103	GOT_symbol = symbol_new (name, undefined_section,
		10104	(valueT) 0, &zero_address_frag);
		10105	};
		10106	return GOT_symbol;
		10107	}
		10108	return 0;
		10109	}
		10110
		10111	/* Round up a section size to the appropriate boundary. */
		10112
		10113	valueT
		10114	md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
		10115	{
		10116	#if (defined (OBJ_AOUT) \|\| defined (OBJ_MAYBE_AOUT))
		10117	if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
		10118	{
		10119	/* For a.out, force the section size to be aligned. If we don't do
		10120	this, BFD will align it for us, but it will not write out the
		10121	final bytes of the section. This may be a bug in BFD, but it is
		10122	easier to fix it here since that is how the other a.out targets
		10123	work. */
		10124	int align;
		10125
		10126	align = bfd_get_section_alignment (stdoutput, segment);
		10127	size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
		10128	}
		10129	#endif
		10130
		10131	return size;
		10132	}
		10133
		10134	/* On the i386, PC-relative offsets are relative to the start of the
		10135	next instruction. That is, the address of the offset, plus its
		10136	size, since the offset is always the last part of the insn. */
		10137
		10138	long
		10139	md_pcrel_from (fixS *fixP)
		10140	{
		10141	return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
		10142	}
		10143
		10144	#ifndef I386COFF
		10145
		10146	static void
		10147	s_bss (int ignore ATTRIBUTE_UNUSED)
		10148	{
		10149	int temp;
		10150
		10151	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		10152	if (IS_ELF)
		10153	obj_elf_section_change_hook ();
		10154	#endif
		10155	temp = get_absolute_expression ();
		10156	subseg_set (bss_section, (subsegT) temp);
		10157	demand_empty_rest_of_line ();
		10158	}
		10159
		10160	#endif
		10161
		10162	void
		10163	i386_validate_fix (fixS *fixp)
		10164	{
		10165	if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
		10166	{
		10167	if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
		10168	{
		10169	if (!object_64bit)
		10170	abort ();
		10171	fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
		10172	}
		10173	else
		10174	{
		10175	if (!object_64bit)
		10176	fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
		10177	else
		10178	fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
		10179	}
		10180	fixp->fx_subsy = 0;
		10181	}
		10182	}
		10183
		10184	arelent *
		10185	tc_gen_reloc (asection section ATTRIBUTE_UNUSED, fixS fixp)
		10186	{
		10187	arelent *rel;
		10188	bfd_reloc_code_real_type code;
		10189
		10190	switch (fixp->fx_r_type)
		10191	{
		10192	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		10193	case BFD_RELOC_SIZE32:
		10194	case BFD_RELOC_SIZE64:
		10195	if (S_IS_DEFINED (fixp->fx_addsy)
		10196	&& !S_IS_EXTERNAL (fixp->fx_addsy))
		10197	{
		10198	/* Resolve size relocation against local symbol to size of
		10199	the symbol plus addend. */
		10200	valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
		10201	if (fixp->fx_r_type == BFD_RELOC_SIZE32
		10202	&& !fits_in_unsigned_long (value))
		10203	as_bad_where (fixp->fx_file, fixp->fx_line,
		10204	_("symbol size computation overflow"));
		10205	fixp->fx_addsy = NULL;
		10206	fixp->fx_subsy = NULL;
		10207	md_apply_fix (fixp, (valueT *) &value, NULL);
		10208	return NULL;
		10209	}
		10210	#endif
		10211
		10212	case BFD_RELOC_X86_64_PLT32:
		10213	case BFD_RELOC_X86_64_PLT32_BND:
		10214	case BFD_RELOC_X86_64_GOT32:
		10215	case BFD_RELOC_X86_64_GOTPCREL:
		10216	case BFD_RELOC_386_PLT32:
		10217	case BFD_RELOC_386_GOT32:
		10218	case BFD_RELOC_386_GOTOFF:
		10219	case BFD_RELOC_386_GOTPC:
		10220	case BFD_RELOC_386_TLS_GD:
		10221	case BFD_RELOC_386_TLS_LDM:
		10222	case BFD_RELOC_386_TLS_LDO_32:
		10223	case BFD_RELOC_386_TLS_IE_32:
		10224	case BFD_RELOC_386_TLS_IE:
		10225	case BFD_RELOC_386_TLS_GOTIE:
		10226	case BFD_RELOC_386_TLS_LE_32:
		10227	case BFD_RELOC_386_TLS_LE:
		10228	case BFD_RELOC_386_TLS_GOTDESC:
		10229	case BFD_RELOC_386_TLS_DESC_CALL:
		10230	case BFD_RELOC_X86_64_TLSGD:
		10231	case BFD_RELOC_X86_64_TLSLD:
		10232	case BFD_RELOC_X86_64_DTPOFF32:
		10233	case BFD_RELOC_X86_64_DTPOFF64:
		10234	case BFD_RELOC_X86_64_GOTTPOFF:
		10235	case BFD_RELOC_X86_64_TPOFF32:
		10236	case BFD_RELOC_X86_64_TPOFF64:
		10237	case BFD_RELOC_X86_64_GOTOFF64:
		10238	case BFD_RELOC_X86_64_GOTPC32:
		10239	case BFD_RELOC_X86_64_GOT64:
		10240	case BFD_RELOC_X86_64_GOTPCREL64:
		10241	case BFD_RELOC_X86_64_GOTPC64:
		10242	case BFD_RELOC_X86_64_GOTPLT64:
		10243	case BFD_RELOC_X86_64_PLTOFF64:
		10244	case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
		10245	case BFD_RELOC_X86_64_TLSDESC_CALL:
		10246	case BFD_RELOC_RVA:
		10247	case BFD_RELOC_VTABLE_ENTRY:
		10248	case BFD_RELOC_VTABLE_INHERIT:
		10249	#ifdef TE_PE
		10250	case BFD_RELOC_32_SECREL:
		10251	#endif
		10252	code = fixp->fx_r_type;
		10253	break;
		10254	case BFD_RELOC_X86_64_32S:
		10255	if (!fixp->fx_pcrel)
		10256	{
		10257	/* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
		10258	code = fixp->fx_r_type;
		10259	break;
		10260	}
		10261	default:
		10262	if (fixp->fx_pcrel)
		10263	{
		10264	switch (fixp->fx_size)
		10265	{
		10266	default:
		10267	as_bad_where (fixp->fx_file, fixp->fx_line,
		10268	_("can not do %d byte pc-relative relocation"),
		10269	fixp->fx_size);
		10270	code = BFD_RELOC_32_PCREL;
		10271	break;
		10272	case 1: code = BFD_RELOC_8_PCREL; break;
		10273	case 2: code = BFD_RELOC_16_PCREL; break;
		10274	case 4:
		10275	code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
		10276	? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
		10277	break;
		10278	#ifdef BFD64
		10279	case 8: code = BFD_RELOC_64_PCREL; break;
		10280	#endif
		10281	}
		10282	}
		10283	else
		10284	{
		10285	switch (fixp->fx_size)
		10286	{
		10287	default:
		10288	as_bad_where (fixp->fx_file, fixp->fx_line,
		10289	_("can not do %d byte relocation"),
		10290	fixp->fx_size);
		10291	code = BFD_RELOC_32;
		10292	break;
		10293	case 1: code = BFD_RELOC_8; break;
		10294	case 2: code = BFD_RELOC_16; break;
		10295	case 4: code = BFD_RELOC_32; break;
		10296	#ifdef BFD64
		10297	case 8: code = BFD_RELOC_64; break;
		10298	#endif
		10299	}
		10300	}
		10301	break;
		10302	}
		10303
		10304	if ((code == BFD_RELOC_32
		10305	\|\| code == BFD_RELOC_32_PCREL
		10306	\|\| code == BFD_RELOC_X86_64_32S)
		10307	&& GOT_symbol
		10308	&& fixp->fx_addsy == GOT_symbol)
		10309	{
		10310	if (!object_64bit)
		10311	code = BFD_RELOC_386_GOTPC;
		10312	else
		10313	code = BFD_RELOC_X86_64_GOTPC32;
		10314	}
		10315	if ((code == BFD_RELOC_64 \|\| code == BFD_RELOC_64_PCREL)
		10316	&& GOT_symbol
		10317	&& fixp->fx_addsy == GOT_symbol)
		10318	{
		10319	code = BFD_RELOC_X86_64_GOTPC64;
		10320	}
		10321
		10322	rel = (arelent *) xmalloc (sizeof (arelent));
		10323	rel->sym_ptr_ptr = (asymbol *) xmalloc (sizeof (asymbol ));
		10324	*rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
		10325
		10326	rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
		10327
		10328	if (!use_rela_relocations)
		10329	{
		10330	/* HACK: Since i386 ELF uses Rel instead of Rela, encode the
		10331	vtable entry to be used in the relocation's section offset. */
		10332	if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
		10333	rel->address = fixp->fx_offset;
		10334	#if defined (OBJ_COFF) && defined (TE_PE)
		10335	else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
		10336	rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
		10337	else
		10338	#endif
		10339	rel->addend = 0;
		10340	}
		10341	/* Use the rela in 64bit mode. */
		10342	else
		10343	{
		10344	if (disallow_64bit_reloc)
		10345	switch (code)
		10346	{
		10347	case BFD_RELOC_X86_64_DTPOFF64:
		10348	case BFD_RELOC_X86_64_TPOFF64:
		10349	case BFD_RELOC_64_PCREL:
		10350	case BFD_RELOC_X86_64_GOTOFF64:
		10351	case BFD_RELOC_X86_64_GOT64:
		10352	case BFD_RELOC_X86_64_GOTPCREL64:
		10353	case BFD_RELOC_X86_64_GOTPC64:
		10354	case BFD_RELOC_X86_64_GOTPLT64:
		10355	case BFD_RELOC_X86_64_PLTOFF64:
		10356	as_bad_where (fixp->fx_file, fixp->fx_line,
		10357	_("cannot represent relocation type %s in x32 mode"),
		10358	bfd_get_reloc_code_name (code));
		10359	break;
		10360	default:
		10361	break;
		10362	}
		10363
		10364	if (!fixp->fx_pcrel)
		10365	rel->addend = fixp->fx_offset;
		10366	else
		10367	switch (code)
		10368	{
		10369	case BFD_RELOC_X86_64_PLT32:
		10370	case BFD_RELOC_X86_64_PLT32_BND:
		10371	case BFD_RELOC_X86_64_GOT32:
		10372	case BFD_RELOC_X86_64_GOTPCREL:
		10373	case BFD_RELOC_X86_64_TLSGD:
		10374	case BFD_RELOC_X86_64_TLSLD:
		10375	case BFD_RELOC_X86_64_GOTTPOFF:
		10376	case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
		10377	case BFD_RELOC_X86_64_TLSDESC_CALL:
		10378	rel->addend = fixp->fx_offset - fixp->fx_size;
		10379	break;
		10380	default:
		10381	rel->addend = (section->vma
		10382	- fixp->fx_size
		10383	+ fixp->fx_addnumber
		10384	+ md_pcrel_from (fixp));
		10385	break;
		10386	}
		10387	}
		10388
		10389	rel->howto = bfd_reloc_type_lookup (stdoutput, code);
		10390	if (rel->howto == NULL)
		10391	{
		10392	as_bad_where (fixp->fx_file, fixp->fx_line,
		10393	_("cannot represent relocation type %s"),
		10394	bfd_get_reloc_code_name (code));
		10395	/* Set howto to a garbage value so that we can keep going. */
		10396	rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
		10397	gas_assert (rel->howto != NULL);
		10398	}
		10399
		10400	return rel;
		10401	}
		10402
		10403	#include "tc-i386-intel.c"
		10404
		10405	void
		10406	tc_x86_parse_to_dw2regnum (expressionS *exp)
		10407	{
		10408	int saved_naked_reg;
		10409	char saved_register_dot;
		10410
		10411	saved_naked_reg = allow_naked_reg;
		10412	allow_naked_reg = 1;
		10413	saved_register_dot = register_chars['.'];
		10414	register_chars['.'] = '.';
		10415	allow_pseudo_reg = 1;
		10416	expression_and_evaluate (exp);
		10417	allow_pseudo_reg = 0;
		10418	register_chars['.'] = saved_register_dot;
		10419	allow_naked_reg = saved_naked_reg;
		10420
		10421	if (exp->X_op == O_register && exp->X_add_number >= 0)
		10422	{
		10423	if ((addressT) exp->X_add_number < i386_regtab_size)
		10424	{
		10425	exp->X_op = O_constant;
		10426	exp->X_add_number = i386_regtab[exp->X_add_number]
		10427	.dw2_regnum[flag_code >> 1];
		10428	}
		10429	else
		10430	exp->X_op = O_illegal;
		10431	}
		10432	}
		10433
		10434	void
		10435	tc_x86_frame_initial_instructions (void)
		10436	{
		10437	static unsigned int sp_regno[2];
		10438
		10439	if (!sp_regno[flag_code >> 1])
		10440	{
		10441	char *saved_input = input_line_pointer;
		10442	char sp[][4] = {"esp", "rsp"};
		10443	expressionS exp;
		10444
		10445	input_line_pointer = sp[flag_code >> 1];
		10446	tc_x86_parse_to_dw2regnum (&exp);
		10447	gas_assert (exp.X_op == O_constant);
		10448	sp_regno[flag_code >> 1] = exp.X_add_number;
		10449	input_line_pointer = saved_input;
		10450	}
		10451
		10452	cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
		10453	cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
		10454	}
		10455
		10456	int
		10457	x86_dwarf2_addr_size (void)
		10458	{
		10459	#if defined (OBJ_MAYBE_ELF) \|\| defined (OBJ_ELF)
		10460	if (x86_elf_abi == X86_64_X32_ABI)
		10461	return 4;
		10462	#endif
		10463	return bfd_arch_bits_per_address (stdoutput) / 8;
		10464	}
		10465
		10466	int
		10467	i386_elf_section_type (const char *str, size_t len)
		10468	{
		10469	if (flag_code == CODE_64BIT
		10470	&& len == sizeof ("unwind") - 1
		10471	&& strncmp (str, "unwind", 6) == 0)
		10472	return SHT_X86_64_UNWIND;
		10473
		10474	return -1;
		10475	}
		10476
		10477	#ifdef TE_SOLARIS
		10478	void
		10479	i386_solaris_fix_up_eh_frame (segT sec)
		10480	{
		10481	if (flag_code == CODE_64BIT)
		10482	elf_section_type (sec) = SHT_X86_64_UNWIND;
		10483	}
		10484	#endif
		10485
		10486	#ifdef TE_PE
		10487	void
		10488	tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
		10489	{
		10490	expressionS exp;
		10491
		10492	exp.X_op = O_secrel;
		10493	exp.X_add_symbol = symbol;
		10494	exp.X_add_number = 0;
		10495	emit_expr (&exp, size);
		10496	}
		10497	#endif
		10498
		10499	#if defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_ELF)
		10500	/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
		10501
		10502	bfd_vma
		10503	x86_64_section_letter (int letter, char **ptr_msg)
		10504	{
		10505	if (flag_code == CODE_64BIT)
		10506	{
		10507	if (letter == 'l')
		10508	return SHF_X86_64_LARGE;
		10509
		10510	*ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
		10511	}
		10512	else
		10513	*ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
		10514	return -1;
		10515	}
		10516
		10517	bfd_vma
		10518	x86_64_section_word (char *str, size_t len)
		10519	{
		10520	if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
		10521	return SHF_X86_64_LARGE;
		10522
		10523	return -1;
		10524	}
		10525
		10526	static void
		10527	handle_large_common (int small ATTRIBUTE_UNUSED)
		10528	{
		10529	if (flag_code != CODE_64BIT)
		10530	{
		10531	s_comm_internal (0, elf_common_parse);
		10532	as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
		10533	}
		10534	else
		10535	{
		10536	static segT lbss_section;
		10537	asection *saved_com_section_ptr = elf_com_section_ptr;
		10538	asection *saved_bss_section = bss_section;
		10539
		10540	if (lbss_section == NULL)
		10541	{
		10542	flagword applicable;
		10543	segT seg = now_seg;
		10544	subsegT subseg = now_subseg;
		10545
		10546	/* The .lbss section is for local .largecomm symbols. */
		10547	lbss_section = subseg_new (".lbss", 0);
		10548	applicable = bfd_applicable_section_flags (stdoutput);
		10549	bfd_set_section_flags (stdoutput, lbss_section,
		10550	applicable & SEC_ALLOC);
		10551	seg_info (lbss_section)->bss = 1;
		10552
		10553	subseg_set (seg, subseg);
		10554	}
		10555
		10556	elf_com_section_ptr = &_bfd_elf_large_com_section;
		10557	bss_section = lbss_section;
		10558
		10559	s_comm_internal (0, elf_common_parse);
		10560
		10561	elf_com_section_ptr = saved_com_section_ptr;
		10562	bss_section = saved_bss_section;
		10563	}
		10564	}
		10565	#endif /* OBJ_ELF \|\| OBJ_MAYBE_ELF */

Subversion Repositories Kolibri OS

(root)/contrib/toolchain/binutils/gas/config/tc-i386.c @ 8031 – Rev 5222