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6400 | punk_joker | 1 | ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
2 | ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny22.xml ************ |
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3 | ;************************************************************************* |
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4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
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5 | ;* |
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6 | ;* Number : AVR000 |
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7 | ;* File Name : "tn22def.inc" |
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8 | ;* Title : Register/Bit Definitions for the ATtiny22 |
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9 | ;* Date : 2005-01-11 |
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10 | ;* Version : 2.14 |
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11 | ;* Support E-mail : avr@atmel.com |
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12 | ;* Target MCU : ATtiny22 |
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13 | ;* |
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14 | ;* DESCRIPTION |
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15 | ;* When including this file in the assembly program file, all I/O register |
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16 | ;* names and I/O register bit names appearing in the data book can be used. |
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17 | ;* In addition, the six registers forming the three data pointers X, Y and |
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18 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
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19 | ;* SRAM is also defined |
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20 | ;* |
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21 | ;* The Register names are represented by their hexadecimal address. |
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22 | ;* |
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23 | ;* The Register Bit names are represented by their bit number (0-7). |
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24 | ;* |
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25 | ;* Please observe the difference in using the bit names with instructions |
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26 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
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27 | ;* (skip if bit in register set/cleared). The following example illustrates |
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28 | ;* this: |
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29 | ;* |
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30 | ;* in r16,PORTB ;read PORTB latch |
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31 | ;* sbr r16,(1< |
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32 | ;* out PORTB,r16 ;output to PORTB |
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33 | ;* |
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34 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register |
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35 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
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36 | ;* rjmp TOV0_is_set ;jump if set |
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37 | ;* ... ;otherwise do something else |
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38 | ;************************************************************************* |
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39 | |||
40 | #ifndef _TN22DEF_INC_ |
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41 | #define _TN22DEF_INC_ |
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42 | |||
43 | |||
44 | #pragma partinc 0 |
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45 | |||
46 | ; ***** SPECIFY DEVICE *************************************************** |
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47 | .device ATtiny22 |
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48 | #pragma AVRPART ADMIN PART_NAME ATtiny22 |
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49 | .equ SIGNATURE_000 = 0x1e |
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50 | .equ SIGNATURE_001 = 0x91 |
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51 | .equ SIGNATURE_002 = 0x06 |
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52 | |||
53 | #pragma AVRPART CORE CORE_VERSION V1 |
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54 | |||
55 | |||
56 | ; ***** I/O REGISTER DEFINITIONS ***************************************** |
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57 | ; NOTE: |
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58 | ; Definitions marked "MEMORY MAPPED"are extended I/O ports |
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59 | ; and cannot be used with IN/OUT instructions |
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60 | .equ SREG = 0x3f |
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61 | .equ SPL = 0x3d |
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62 | .equ GIMSK = 0x3b |
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63 | .equ GIFR = 0x3a |
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64 | .equ TIMSK = 0x39 |
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65 | .equ TIFR = 0x38 |
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66 | .equ MCUCR = 0x35 |
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67 | .equ MCUSR = 0x34 |
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68 | .equ TCCR0 = 0x33 |
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69 | .equ TCNT0 = 0x32 |
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70 | .equ WDTCR = 0x21 |
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71 | .equ EEAR = 0x1e |
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72 | .equ EEDR = 0x1d |
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73 | .equ EECR = 0x1c |
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74 | .equ PORTB = 0x18 |
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75 | .equ DDRB = 0x17 |
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76 | .equ PINB = 0x16 |
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77 | |||
78 | |||
79 | ; ***** BIT DEFINITIONS ************************************************** |
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80 | |||
81 | ; ***** CPU ************************** |
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82 | ; SREG - Status Register |
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83 | .equ SREG_C = 0 ; Carry Flag |
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84 | .equ SREG_Z = 1 ; Zero Flag |
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85 | .equ SREG_N = 2 ; Negative Flag |
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86 | .equ SREG_V = 3 ; Two's Complement Overflow Flag |
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87 | .equ SREG_S = 4 ; Sign Bit |
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88 | .equ SREG_H = 5 ; Half Carry Flag |
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89 | .equ SREG_T = 6 ; Bit Copy Storage |
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90 | .equ SREG_I = 7 ; Global Interrupt Enable |
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91 | |||
92 | ; SPL - Stack Pointer Low |
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93 | .equ SP0 = 0 ; Stack pointer bit 0 |
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94 | .equ SP1 = 1 ; Stack pointer bit 1 |
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95 | .equ SP2 = 2 ; Stack pointer bit 2 |
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96 | .equ SP3 = 3 ; Stack pointer bit 3 |
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97 | .equ SP4 = 4 |
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98 | .equ SP5 = 5 ; Stack pointer bit 5 |
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99 | .equ SP6 = 6 ; Stack pointer bit 6 |
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100 | .equ SP7 = 7 ; Stack pointer bit 7 |
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101 | |||
102 | ; MCUCR - MCU Control Register |
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103 | .equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
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104 | .equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
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105 | .equ SM = 4 ; Sleep Mode |
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106 | .equ SE = 5 ; Sleep Enable |
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107 | |||
108 | ; MCUSR - MCU Status register |
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109 | .equ PORF = 0 ; Power-On Reset Flag |
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110 | .equ EXTRF = 1 ; External Reset Flag |
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111 | |||
112 | |||
113 | ; ***** TIMER_COUNTER_0 ************** |
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114 | ; TIMSK - Timer/Counter Interrupt Mask Register |
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115 | .equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
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116 | |||
117 | ; TIFR - Timer/Counter Interrupt Flag register |
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118 | .equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
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119 | |||
120 | ; TCCR0 - Timer/Counter0 Control Register |
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121 | .equ CS00 = 0 ; Clock Select0 bit 0 |
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122 | .equ CS01 = 1 ; Clock Select0 bit 1 |
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123 | .equ CS02 = 2 ; Clock Select0 bit 2 |
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124 | |||
125 | ; TCNT0 - Timer Counter 0 |
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126 | .equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
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127 | .equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
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128 | .equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
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129 | .equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
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130 | .equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
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131 | .equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
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132 | .equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
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133 | .equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
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134 | |||
135 | |||
136 | ; ***** EEPROM *********************** |
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137 | ; EEAR - EEPROM Read/Write Access |
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138 | .equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
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139 | .equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
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140 | .equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
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141 | .equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
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142 | .equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
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143 | .equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
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144 | .equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
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145 | .equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7 |
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146 | |||
147 | ; EEDR - EEPROM Data Register |
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148 | .equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
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149 | .equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
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150 | .equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
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151 | .equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
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152 | .equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
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153 | .equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
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154 | .equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
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155 | .equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
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156 | |||
157 | ; EECR - EEPROM Control Register |
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158 | .equ EERE = 0 ; EEPROM Read Enable |
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159 | .equ EEWE = 1 ; EEPROM Write Enable |
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160 | .equ EEMWE = 2 ; EEPROM Master Write Enable |
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161 | |||
162 | |||
163 | ; ***** WATCHDOG ********************* |
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164 | ; WDTCR - Watchdog Timer Control Register |
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165 | .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
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166 | .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
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167 | .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
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168 | .equ WDE = 3 ; Watch Dog Enable |
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169 | .equ WDTOE = 4 ; RW |
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170 | .equ WDDE = WDTOE ; For compatibility |
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171 | |||
172 | |||
173 | ; ***** PORTB ************************ |
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174 | ; PORTB - Data Register, Port B |
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175 | .equ PORTB0 = 0 ; |
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176 | .equ PB0 = 0 ; For compatibility |
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177 | .equ PORTB1 = 1 ; |
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178 | .equ PB1 = 1 ; For compatibility |
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179 | .equ PORTB2 = 2 ; |
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180 | .equ PB2 = 2 ; For compatibility |
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181 | .equ PORTB3 = 3 ; |
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182 | .equ PB3 = 3 ; For compatibility |
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183 | .equ PORTB4 = 4 ; |
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184 | .equ PB4 = 4 ; For compatibility |
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185 | |||
186 | ; DDRB - Data Direction Register, Port B |
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187 | .equ DDB0 = 0 ; |
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188 | .equ DDB1 = 1 ; |
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189 | .equ DDB2 = 2 ; |
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190 | .equ DDB3 = 3 ; |
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191 | .equ DDB4 = 4 ; |
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192 | |||
193 | ; PINB - Input Pins, Port B |
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194 | .equ PINB0 = 0 ; |
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195 | .equ PINB1 = 1 ; |
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196 | .equ PINB2 = 2 ; |
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197 | .equ PINB3 = 3 ; |
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198 | .equ PINB4 = 4 ; |
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199 | |||
200 | |||
201 | |||
202 | ; ***** LOCKSBITS ******************************************************** |
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203 | .equ LB1 = 0 ; Lockbit |
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204 | .equ LB2 = 1 ; Lockbit |
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205 | |||
206 | |||
207 | ; ***** FUSES ************************************************************ |
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208 | ; LOW fuse bits |
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209 | |||
210 | |||
211 | |||
212 | ; ***** CPU REGISTER DEFINITIONS ***************************************** |
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213 | .def XH = r27 |
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214 | .def XL = r26 |
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215 | .def YH = r29 |
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216 | .def YL = r28 |
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217 | .def ZH = r31 |
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218 | .def ZL = r30 |
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219 | |||
220 | |||
221 | |||
222 | ; ***** DATA MEMORY DECLARATIONS ***************************************** |
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223 | .equ FLASHEND = 0x03ff ; Note: Word address |
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224 | .equ IOEND = 0x003f |
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225 | .equ SRAM_START = 0x0060 |
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226 | .equ SRAM_SIZE = 128 |
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227 | .equ RAMEND = 0x00df |
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228 | .equ XRAMEND = 0x0000 |
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229 | .equ E2END = 0x007f |
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230 | .equ EEPROMEND = 0x007f |
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231 | .equ EEADRBITS = 7 |
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232 | #pragma AVRPART MEMORY PROG_FLASH 2048 |
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233 | #pragma AVRPART MEMORY EEPROM 128 |
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234 | #pragma AVRPART MEMORY INT_SRAM SIZE 128 |
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235 | #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
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236 | |||
237 | |||
238 | |||
239 | |||
240 | |||
241 | ; ***** INTERRUPT VECTORS ************************************************ |
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242 | .equ INT0addr = 0x0001 ; External Interrupt 0 |
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243 | .equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow |
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244 | |||
245 | .equ INT_VECTORS_SIZE = 3 ; size in words |
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246 | |||
247 | #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
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248 | |||
249 | #endif /* _TN22DEF_INC_ */ |
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250 | |||
251 | ; ***** END OF FILE ****************************************************** |