WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/pwm3def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:30 *** Source: AT90PWM3.xml **********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "pwm3def.inc"
		8	;* Title : Register/Bit Definitions for the AT90PWM3
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : AT90PWM3
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _PWM3DEF_INC_
		41	#define _PWM3DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device AT90PWM3
		48	#pragma AVRPART ADMIN PART_NAME AT90PWM3
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x93
		51	.equ SIGNATURE_002 = 0x81
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ PICR2H = 0xff ; MEMORY MAPPED
		61	.equ PICR2L = 0xfe ; MEMORY MAPPED
		62	.equ PFRC2B = 0xfd ; MEMORY MAPPED
		63	.equ PFRC2A = 0xfc ; MEMORY MAPPED
		64	.equ PCTL2 = 0xfb ; MEMORY MAPPED
		65	.equ PCNF2 = 0xfa ; MEMORY MAPPED
		66	.equ OCR2RBH = 0xf9 ; MEMORY MAPPED
		67	.equ OCR2RBL = 0xf8 ; MEMORY MAPPED
		68	.equ OCR2SBH = 0xf7 ; MEMORY MAPPED
		69	.equ OCR2SBL = 0xf6 ; MEMORY MAPPED
		70	.equ OCR2RAH = 0xf5 ; MEMORY MAPPED
		71	.equ OCR2RAL = 0xf4 ; MEMORY MAPPED
		72	.equ OCR2SAH = 0xf3 ; MEMORY MAPPED
		73	.equ OCR2SAL = 0xf2 ; MEMORY MAPPED
		74	.equ POM2 = 0xf1 ; MEMORY MAPPED
		75	.equ PSOC2 = 0xf0 ; MEMORY MAPPED
		76	.equ PICR1H = 0xef ; MEMORY MAPPED
		77	.equ PICR1L = 0xee ; MEMORY MAPPED
		78	.equ PFRC1B = 0xed ; MEMORY MAPPED
		79	.equ PFRC1A = 0xec ; MEMORY MAPPED
		80	.equ PCTL1 = 0xeb ; MEMORY MAPPED
		81	.equ PCNF1 = 0xea ; MEMORY MAPPED
		82	.equ OCR1RBH = 0xe9 ; MEMORY MAPPED
		83	.equ OCR1RBL = 0xe8 ; MEMORY MAPPED
		84	.equ OCR1SBH = 0xe7 ; MEMORY MAPPED
		85	.equ OCR1SBL = 0xe6 ; MEMORY MAPPED
		86	.equ OCR1RAH = 0xe5 ; MEMORY MAPPED
		87	.equ OCR1RAL = 0xe4 ; MEMORY MAPPED
		88	.equ OCR1SAH = 0xe3 ; MEMORY MAPPED
		89	.equ OCR1SAL = 0xe2 ; MEMORY MAPPED
		90	.equ PSOC1 = 0xe0 ; MEMORY MAPPED
		91	.equ PICR0H = 0xdf ; MEMORY MAPPED
		92	.equ PICR0L = 0xde ; MEMORY MAPPED
		93	.equ PFRC0B = 0xdd ; MEMORY MAPPED
		94	.equ PFRC0A = 0xdc ; MEMORY MAPPED
		95	.equ PCTL0 = 0xdb ; MEMORY MAPPED
		96	.equ PCNF0 = 0xda ; MEMORY MAPPED
		97	.equ OCR0RBH = 0xd9 ; MEMORY MAPPED
		98	.equ OCR0RBL = 0xd8 ; MEMORY MAPPED
		99	.equ OCR0SBH = 0xd7 ; MEMORY MAPPED
		100	.equ OCR0SBL = 0xd6 ; MEMORY MAPPED
		101	.equ OCR0RAH = 0xd5 ; MEMORY MAPPED
		102	.equ OCR0RAL = 0xd4 ; MEMORY MAPPED
		103	.equ OCR0SAH = 0xd3 ; MEMORY MAPPED
		104	.equ OCR0SAL = 0xd2 ; MEMORY MAPPED
		105	.equ PSOC0 = 0xd0 ; MEMORY MAPPED
		106	.equ EUDR = 0xce ; MEMORY MAPPED
		107	.equ MUBRRH = 0xcd ; MEMORY MAPPED
		108	.equ MUBRRL = 0xcc ; MEMORY MAPPED
		109	.equ EUCSRC = 0xca ; MEMORY MAPPED
		110	.equ EUCSRB = 0xc9 ; MEMORY MAPPED
		111	.equ EUCSRA = 0xc8 ; MEMORY MAPPED
		112	.equ UDR = 0xc6 ; MEMORY MAPPED
		113	.equ UBRRH = 0xc5 ; MEMORY MAPPED
		114	.equ UBRRL = 0xc4 ; MEMORY MAPPED
		115	.equ UCSRC = 0xc2 ; MEMORY MAPPED
		116	.equ UCSRB = 0xc1 ; MEMORY MAPPED
		117	.equ UCSRA = 0xc0 ; MEMORY MAPPED
		118	.equ AC2CON = 0xaf ; MEMORY MAPPED
		119	.equ AC1CON = 0xae ; MEMORY MAPPED
		120	.equ AC0CON = 0xad ; MEMORY MAPPED
		121	.equ DACH = 0xac ; MEMORY MAPPED
		122	.equ DACL = 0xab ; MEMORY MAPPED
		123	.equ DACON = 0xaa ; MEMORY MAPPED
		124	.equ PIM2 = 0xa5 ; MEMORY MAPPED
		125	.equ PIFR2 = 0xa4 ; MEMORY MAPPED
		126	.equ PIM1 = 0xa3 ; MEMORY MAPPED
		127	.equ PIFR1 = 0xa2 ; MEMORY MAPPED
		128	.equ PIM0 = 0xa1 ; MEMORY MAPPED
		129	.equ PIFR0 = 0xa0 ; MEMORY MAPPED
		130	.equ OCR1BH = 0x8b ; MEMORY MAPPED
		131	.equ OCR1BL = 0x8a ; MEMORY MAPPED
		132	.equ OCR1AH = 0x89 ; MEMORY MAPPED
		133	.equ OCR1AL = 0x88 ; MEMORY MAPPED
		134	.equ ICR1H = 0x87 ; MEMORY MAPPED
		135	.equ ICR1L = 0x86 ; MEMORY MAPPED
		136	.equ TCNT1H = 0x85 ; MEMORY MAPPED
		137	.equ TCNT1L = 0x84 ; MEMORY MAPPED
		138	.equ TCCR1C = 0x82 ; MEMORY MAPPED
		139	.equ TCCR1B = 0x81 ; MEMORY MAPPED
		140	.equ TCCR1A = 0x80 ; MEMORY MAPPED
		141	.equ DIDR1 = 0x7f ; MEMORY MAPPED
		142	.equ DIDR0 = 0x7e ; MEMORY MAPPED
		143	.equ ADMUX = 0x7c ; MEMORY MAPPED
		144	.equ ADCSRB = 0x7b ; MEMORY MAPPED
		145	.equ ADCSRA = 0x7a ; MEMORY MAPPED
		146	.equ ADCH = 0x79 ; MEMORY MAPPED
		147	.equ ADCL = 0x78 ; MEMORY MAPPED
		148	.equ AMP1CSR = 0x77 ; MEMORY MAPPED
		149	.equ AMP0CSR = 0x76 ; MEMORY MAPPED
		150	.equ TIMSK1 = 0x6f ; MEMORY MAPPED
		151	.equ TIMSK0 = 0x6e ; MEMORY MAPPED
		152	.equ EICRA = 0x69 ; MEMORY MAPPED
		153	.equ OSCCAL = 0x66 ; MEMORY MAPPED
		154	.equ PRR = 0x64 ; MEMORY MAPPED
		155	.equ CLKPR = 0x61 ; MEMORY MAPPED
		156	.equ WDTCSR = 0x60 ; MEMORY MAPPED
		157	.equ SREG = 0x3f
		158	.equ SPH = 0x3e
		159	.equ SPL = 0x3d
		160	.equ SPMCSR = 0x37
		161	.equ MCUCR = 0x35
		162	.equ MCUSR = 0x34
		163	.equ SMCR = 0x33
		164	.equ ACSR = 0x30
		165	.equ SPDR = 0x2e
		166	.equ SPSR = 0x2d
		167	.equ SPCR = 0x2c
		168	.equ PLLCSR = 0x29
		169	.equ OCR0B = 0x28
		170	.equ OCR0A = 0x27
		171	.equ TCNT0 = 0x26
		172	.equ TCCR0B = 0x25
		173	.equ TCCR0A = 0x24
		174	.equ GTCCR = 0x23
		175	.equ EEARH = 0x22
		176	.equ EEARL = 0x21
		177	.equ EEDR = 0x20
		178	.equ EECR = 0x1f
		179	.equ GPIOR0 = 0x1e
		180	.equ EIMSK = 0x1d
		181	.equ EIFR = 0x1c
		182	.equ GPIOR3 = 0x1b
		183	.equ GPIOR2 = 0x1a
		184	.equ GPIOR1 = 0x19
		185	.equ TIFR1 = 0x16
		186	.equ TIFR0 = 0x15
		187	.equ PORTE = 0x0e
		188	.equ DDRE = 0x0d
		189	.equ PINE = 0x0c
		190	.equ PORTD = 0x0b
		191	.equ DDRD = 0x0a
		192	.equ PIND = 0x09
		193	.equ PORTC = 0x08
		194	.equ DDRC = 0x07
		195	.equ PINC = 0x06
		196	.equ PORTB = 0x05
		197	.equ DDRB = 0x04
		198	.equ PINB = 0x03
		199
		200
		201	; *** BIT DEFINITIONS ************************************************
		202
		203	; *** PORTB **********************
		204	; PORTB - Port B Data Register
		205	.equ PORTB0 = 0 ; Port B Data Register bit 0
		206	.equ PB0 = 0 ; For compatibility
		207	.equ PORTB1 = 1 ; Port B Data Register bit 1
		208	.equ PB1 = 1 ; For compatibility
		209	.equ PORTB2 = 2 ; Port B Data Register bit 2
		210	.equ PB2 = 2 ; For compatibility
		211	.equ PORTB3 = 3 ; Port B Data Register bit 3
		212	.equ PB3 = 3 ; For compatibility
		213	.equ PORTB4 = 4 ; Port B Data Register bit 4
		214	.equ PB4 = 4 ; For compatibility
		215	.equ PORTB5 = 5 ; Port B Data Register bit 5
		216	.equ PB5 = 5 ; For compatibility
		217	.equ PORTB6 = 6 ; Port B Data Register bit 6
		218	.equ PB6 = 6 ; For compatibility
		219	.equ PORTB7 = 7 ; Port B Data Register bit 7
		220	.equ PB7 = 7 ; For compatibility
		221
		222	; DDRB - Port B Data Direction Register
		223	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		224	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		225	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		226	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		227	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		228	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		229	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		230	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		231
		232	; PINB - Port B Input Pins
		233	.equ PINB0 = 0 ; Port B Input Pins bit 0
		234	.equ PINB1 = 1 ; Port B Input Pins bit 1
		235	.equ PINB2 = 2 ; Port B Input Pins bit 2
		236	.equ PINB3 = 3 ; Port B Input Pins bit 3
		237	.equ PINB4 = 4 ; Port B Input Pins bit 4
		238	.equ PINB5 = 5 ; Port B Input Pins bit 5
		239	.equ PINB6 = 6 ; Port B Input Pins bit 6
		240	.equ PINB7 = 7 ; Port B Input Pins bit 7
		241
		242
		243	; *** PORTC **********************
		244	; PORTC - Port C Data Register
		245	.equ PORTC0 = 0 ; Port C Data Register bit 0
		246	.equ PC0 = 0 ; For compatibility
		247	.equ PORTC1 = 1 ; Port C Data Register bit 1
		248	.equ PC1 = 1 ; For compatibility
		249	.equ PORTC2 = 2 ; Port C Data Register bit 2
		250	.equ PC2 = 2 ; For compatibility
		251	.equ PORTC3 = 3 ; Port C Data Register bit 3
		252	.equ PC3 = 3 ; For compatibility
		253	.equ PORTC4 = 4 ; Port C Data Register bit 4
		254	.equ PC4 = 4 ; For compatibility
		255	.equ PORTC5 = 5 ; Port C Data Register bit 5
		256	.equ PC5 = 5 ; For compatibility
		257	.equ PORTC6 = 6 ; Port C Data Register bit 6
		258	.equ PC6 = 6 ; For compatibility
		259	.equ PORTC7 = 7 ; Port C Data Register bit 7
		260	.equ PC7 = 7 ; For compatibility
		261
		262	; DDRC - Port C Data Direction Register
		263	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		264	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		265	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		266	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		267	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		268	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		269	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		270	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		271
		272	; PINC - Port C Input Pins
		273	.equ PINC0 = 0 ; Port C Input Pins bit 0
		274	.equ PINC1 = 1 ; Port C Input Pins bit 1
		275	.equ PINC2 = 2 ; Port C Input Pins bit 2
		276	.equ PINC3 = 3 ; Port C Input Pins bit 3
		277	.equ PINC4 = 4 ; Port C Input Pins bit 4
		278	.equ PINC5 = 5 ; Port C Input Pins bit 5
		279	.equ PINC6 = 6 ; Port C Input Pins bit 6
		280	.equ PINC7 = 7 ; Port C Input Pins bit 7
		281
		282
		283	; *** PORTD **********************
		284	; PORTD - Port D Data Register
		285	.equ PORTD0 = 0 ; Port D Data Register bit 0
		286	.equ PD0 = 0 ; For compatibility
		287	.equ PORTD1 = 1 ; Port D Data Register bit 1
		288	.equ PD1 = 1 ; For compatibility
		289	.equ PORTD2 = 2 ; Port D Data Register bit 2
		290	.equ PD2 = 2 ; For compatibility
		291	.equ PORTD3 = 3 ; Port D Data Register bit 3
		292	.equ PD3 = 3 ; For compatibility
		293	.equ PORTD4 = 4 ; Port D Data Register bit 4
		294	.equ PD4 = 4 ; For compatibility
		295	.equ PORTD5 = 5 ; Port D Data Register bit 5
		296	.equ PD5 = 5 ; For compatibility
		297	.equ PORTD6 = 6 ; Port D Data Register bit 6
		298	.equ PD6 = 6 ; For compatibility
		299	.equ PORTD7 = 7 ; Port D Data Register bit 7
		300	.equ PD7 = 7 ; For compatibility
		301
		302	; DDRD - Port D Data Direction Register
		303	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		304	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		305	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		306	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		307	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		308	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		309	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		310	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		311
		312	; PIND - Port D Input Pins
		313	.equ PIND0 = 0 ; Port D Input Pins bit 0
		314	.equ PIND1 = 1 ; Port D Input Pins bit 1
		315	.equ PIND2 = 2 ; Port D Input Pins bit 2
		316	.equ PIND3 = 3 ; Port D Input Pins bit 3
		317	.equ PIND4 = 4 ; Port D Input Pins bit 4
		318	.equ PIND5 = 5 ; Port D Input Pins bit 5
		319	.equ PIND6 = 6 ; Port D Input Pins bit 6
		320	.equ PIND7 = 7 ; Port D Input Pins bit 7
		321
		322
		323	; *** BOOT_LOAD ******************
		324	; SPMCSR - Store Program Memory Control Register
		325	.equ SPMCR = SPMCSR ; For compatibility
		326	.equ SPMEN = 0 ; Store Program Memory Enable
		327	.equ PGERS = 1 ; Page Erase
		328	.equ PGWRT = 2 ; Page Write
		329	.equ BLBSET = 3 ; Boot Lock Bit Set
		330	.equ RWWSRE = 4 ; Read While Write section read enable
		331	.equ ASRE = RWWSRE ; For compatibility
		332	.equ RWWSB = 6 ; Read While Write Section Busy
		333	.equ ASB = RWWSB ; For compatibility
		334	.equ SPMIE = 7 ; SPM Interrupt Enable
		335
		336
		337	; *** EEPROM *********************
		338	; EEDR - EEPROM Data Register
		339	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		340	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		341	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		342	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		343	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		344	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		345	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		346	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		347
		348	; EECR - EEPROM Control Register
		349	.equ EERE = 0 ; EEPROM Read Enable
		350	.equ EEWE = 1 ; EEPROM Write Enable
		351	.equ EEMWE = 2 ; EEPROM Master Write Enable
		352	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		353
		354
		355	; *** PSC0 ***********************
		356	; PICR0H - PSC 0 Input Capture Register High
		357	.equ PICR0_8 = 0 ;
		358	.equ PICR0_9 = 1 ;
		359	.equ PICR0_10 = 2 ;
		360	.equ PICR0_11 = 3 ;
		361
		362	; PICR0L - PSC 0 Input Capture Register Low
		363	.equ PICR0_0 = 0 ;
		364	.equ PICR0_1 = 1 ;
		365	.equ PICR0_2 = 2 ;
		366	.equ PICR0_3 = 3 ;
		367	.equ PICR0_4 = 4 ;
		368	.equ PICR0_5 = 5 ;
		369	.equ PICR0_6 = 6 ;
		370	.equ PICR0_7 = 7 ;
		371
		372	; PFRC0B - PSC 0 Input B Control
		373	.equ PRFM0B0 = 0 ; PSC 0 Retrigger and Fault Mode for Part B
		374	.equ PRFM0B1 = 1 ; PSC 0 Retrigger and Fault Mode for Part B
		375	.equ PRFM0B2 = 2 ; PSC 0 Retrigger and Fault Mode for Part B
		376	.equ PRFM0B3 = 3 ; PSC 0 Retrigger and Fault Mode for Part B
		377	.equ PFLTE0B = 4 ; PSC 0 Filter Enable on Input Part B
		378	.equ PELEV0B = 5 ; PSC 0 Edge Level Selector on Input Part B
		379	.equ PISEL0B = 6 ; PSC 0 Input Select for Part B
		380	.equ PCAE0B = 7 ; PSC 0 Capture Enable Input Part B
		381
		382	; PFRC0A - PSC 0 Input A Control
		383	.equ PRFM0A0 = 0 ; PSC 0 Retrigger and Fault Mode for Part A
		384	.equ PRFM0A1 = 1 ; PSC 0 Retrigger and Fault Mode for Part A
		385	.equ PRFM0A2 = 2 ; PSC 0 Retrigger and Fault Mode for Part A
		386	.equ PRFM0A3 = 3 ; PSC 0 Retrigger and Fault Mode for Part A
		387	.equ PFLTE0A = 4 ; PSC 0 Filter Enable on Input Part A
		388	.equ PELEV0A = 5 ; PSC 0 Edge Level Selector on Input Part A
		389	.equ PISEL0A = 6 ; PSC 0 Input Select for Part A
		390	.equ PCAE0A = 7 ; PSC 0 Capture Enable Input Part A
		391
		392	; PCTL0 - PSC 0 Control Register
		393	.equ PRUN0 = 0 ; PSC 0 Run
		394	.equ PCCYC0 = 1 ; PSC0 Complete Cycle
		395	.equ PARUN0 = 2 ; PSC0 Auto Run
		396	.equ PAOC0A = 3 ; PSC 0 Asynchronous Output Control A
		397	.equ PAOC0B = 4 ; PSC 0 Asynchronous Output Control B
		398	.equ PBFM0 = 5 ; PSC 0 Balance Flank Width Modulation
		399	.equ PPRE00 = 6 ; PSC 0 Prescaler Select 0
		400	.equ PPRE01 = 7 ; PSC 0 Prescaler Select 1
		401
		402	; PCNF0 - PSC 0 Configuration Register
		403	.equ PCLKSEL0 = 1 ; PSC 0 Input Clock Select
		404	.equ POP0 = 2 ; PSC 0 Output Polarity
		405	.equ PMODE00 = 3 ; PSC 0 Mode
		406	.equ PMODE01 = 4 ; PSC 0 Mode
		407	.equ PLOCK0 = 5 ; PSC 0 Lock
		408	.equ PALOCK0 = 6 ; PSC 0 Autolock
		409	.equ PFIFTY0 = 7 ; PSC 0 Fifty
		410
		411	; OCR0RBH - Output Compare RB Register High
		412	.equ OCR0RB_8 = 0 ;
		413	.equ OCR0RB_9 = 1 ;
		414	.equ OCR0RB_00 = 2 ;
		415	.equ OCR0RB_01 = 3 ;
		416	.equ OCR0RB_02 = 4 ;
		417	.equ OCR0RB_03 = 5 ;
		418	.equ OCR0RB_04 = 6 ;
		419	.equ OCR0RB_05 = 7 ;
		420
		421	; OCR0RBL - Output Compare RB Register Low
		422	.equ OCR0RB_0 = 0 ;
		423	.equ OCR0RB_1 = 1 ;
		424	.equ OCR0RB_2 = 2 ;
		425	.equ OCR0RB_3 = 3 ;
		426	.equ OCR0RB_4 = 4 ;
		427	.equ OCR0RB_5 = 5 ;
		428	.equ OCR0RB_6 = 6 ;
		429	.equ OCR0RB_7 = 7 ;
		430
		431	; OCR0SBH - Output Compare SB Register High
		432	.equ OCR0SB_8 = 0 ;
		433	.equ OCR0SB_9 = 1 ;
		434	.equ OCR0SB_00 = 2 ;
		435	.equ OCR0SB_01 = 3 ;
		436
		437	; OCR0SBL - Output Compare SB Register Low
		438	.equ OCR0SB_0 = 0 ;
		439	.equ OCR0SB_1 = 1 ;
		440	.equ OCR0SB_2 = 2 ;
		441	.equ OCR0SB_3 = 3 ;
		442	.equ OCR0SB_4 = 4 ;
		443	.equ OCR0SB_5 = 5 ;
		444	.equ OCR0SB_6 = 6 ;
		445	.equ OCR0SB_7 = 7 ;
		446
		447	; OCR0RAH - Output Compare RA Register High
		448	.equ OCR0RA_8 = 0 ;
		449	.equ OCR0RA_9 = 1 ;
		450	.equ OCR0RA_00 = 2 ;
		451	.equ OCR0RA_01 = 3 ;
		452
		453	; OCR0RAL - Output Compare RA Register Low
		454	.equ OCR0RA_0 = 0 ;
		455	.equ OCR0RA_1 = 1 ;
		456	.equ OCR0RA_2 = 2 ;
		457	.equ OCR0RA_3 = 3 ;
		458	.equ OCR0RA_4 = 4 ;
		459	.equ OCR0RA_5 = 5 ;
		460	.equ OCR0RA_6 = 6 ;
		461	.equ OCR0RA_7 = 7 ;
		462
		463	; OCR0SAH - Output Compare SA Register High
		464	.equ OCR0SA_8 = 0 ;
		465	.equ OCR0SA_9 = 1 ;
		466	.equ OCR0SA_00 = 2 ;
		467	.equ OCR0SA_01 = 3 ;
		468
		469	; OCR0SAL - Output Compare SA Register Low
		470	.equ OCR0SA_0 = 0 ;
		471	.equ OCR0SA_1 = 1 ;
		472	.equ OCR0SA_2 = 2 ;
		473	.equ OCR0SA_3 = 3 ;
		474	.equ OCR0SA_4 = 4 ;
		475	.equ OCR0SA_5 = 5 ;
		476	.equ OCR0SA_6 = 6 ;
		477	.equ OCR0SA_7 = 7 ;
		478
		479	; PSOC0 - PSC0 Synchro and Output Configuration
		480	.equ POEN0A = 0 ; PSCOUT00 Output Enable
		481	.equ POEN0B = 2 ; PSCOUT01 Output Enable
		482	.equ PSYNC00 = 4 ; Synchronization Out for ADC Selection
		483	.equ PSYNC01 = 5 ; Synchronization Out for ADC Selection
		484
		485	; PIM0 - PSC0 Interrupt Mask Register
		486	.equ PEOPE0 = 0 ; End of Cycle Interrupt Enable
		487	.equ PEVE0A = 3 ; External Event A Interrupt Enable
		488	.equ PEVE0B = 4 ; External Event B Interrupt Enable
		489	.equ PSEIE0 = 5 ; PSC 0 Synchro Error Interrupt Enable
		490
		491	; PIFR0 - PSC0 Interrupt Flag Register
		492	.equ PEOP0 = 0 ; End of PSC0 Interrupt
		493	.equ PRN00 = 1 ; Ramp Number
		494	.equ PRN01 = 2 ; Ramp Number
		495	.equ PEV0A = 3 ; External Event A Interrupt
		496	.equ PEV0B = 4 ; External Event B Interrupt
		497	.equ PSEI0 = 5 ; PSC 0 Synchro Error Interrupt
		498
		499
		500	; *** PSC1 ***********************
		501	; PICR1H - PSC 1 Input Capture Register High
		502	.equ PICR1_8 = 0 ;
		503	.equ PICR1_9 = 1 ;
		504	.equ PICR1_10 = 2 ;
		505	.equ PICR1_11 = 3 ;
		506
		507	; PICR1L - PSC 1 Input Capture Register Low
		508	.equ PICR1_0 = 0 ;
		509	.equ PICR1_1 = 1 ;
		510	.equ PICR1_2 = 2 ;
		511	.equ PICR1_3 = 3 ;
		512	.equ PICR1_4 = 4 ;
		513	.equ PICR1_5 = 5 ;
		514	.equ PICR1_6 = 6 ;
		515	.equ PICR1_7 = 7 ;
		516
		517	; PFRC1B - PSC 1 Input B Control
		518	.equ PRFM1B0 = 0 ; PSC 1 Retrigger and Fault Mode for Part B
		519	.equ PRFM1B1 = 1 ; PSC 1 Retrigger and Fault Mode for Part B
		520	.equ PRFM1B2 = 2 ; PSC 1 Retrigger and Fault Mode for Part B
		521	.equ PRFM1B3 = 3 ; PSC 1 Retrigger and Fault Mode for Part B
		522	.equ PFLTE1B = 4 ; PSC 1 Filter Enable on Input Part B
		523	.equ PELEV1B = 5 ; PSC 1 Edge Level Selector on Input Part B
		524	.equ PISEL1B = 6 ; PSC 1 Input Select for Part B
		525	.equ PCAE1B = 7 ; PSC 1 Capture Enable Input Part B
		526
		527	; PFRC1A - PSC 1 Input B Control
		528	.equ PRFM1A0 = 0 ; PSC 1 Retrigger and Fault Mode for Part A
		529	.equ PRFM1A1 = 1 ; PSC 1 Retrigger and Fault Mode for Part A
		530	.equ PRFM1A2 = 2 ; PSC 1 Retrigger and Fault Mode for Part A
		531	.equ PRFM1A3 = 3 ; PSC 1 Retrigger and Fault Mode for Part A
		532	.equ PFLTE1A = 4 ; PSC 1 Filter Enable on Input Part A
		533	.equ PELEV1A = 5 ; PSC 1 Edge Level Selector on Input Part A
		534	.equ PISEL1A = 6 ; PSC 1 Input Select for Part A
		535	.equ PCAE1A = 7 ; PSC 1 Capture Enable Input Part A
		536
		537	; PCTL1 - PSC 1 Control Register
		538	.equ PRUN1 = 0 ; PSC 1 Run
		539	.equ PCCYC1 = 1 ; PSC1 Complete Cycle
		540	.equ PARUN1 = 2 ; PSC1 Auto Run
		541	.equ PAOC1A = 3 ; PSC 1 Asynchronous Output Control A
		542	.equ PAOC1B = 4 ; PSC 1 Asynchronous Output Control B
		543	.equ PBFM1 = 5 ; Balance Flank Width Modulation
		544	.equ PPRE10 = 6 ; PSC 1 Prescaler Select 0
		545	.equ PPRE11 = 7 ; PSC 1 Prescaler Select 1
		546
		547	; PCNF1 - PSC 1 Configuration Register
		548	.equ PCLKSEL1 = 1 ; PSC 1 Input Clock Select
		549	.equ POP1 = 2 ; PSC 1 Output Polarity
		550	.equ PMODE10 = 3 ; PSC 1 Mode
		551	.equ PMODE11 = 4 ; PSC 1 Mode
		552	.equ PLOCK1 = 5 ; PSC 1 Lock
		553	.equ PALOCK1 = 6 ; PSC 1 Autolock
		554	.equ PFIFTY1 = 7 ; PSC 1 Fifty
		555
		556	; OCR1RBH - Output Compare RB Register High
		557	.equ OCR1RB_8 = 0 ;
		558	.equ OCR1RB_9 = 1 ;
		559	.equ OCR1RB_10 = 2 ;
		560	.equ OCR1RB_11 = 3 ;
		561	.equ OCR1RB_12 = 4 ;
		562	.equ OCR1RB_13 = 5 ;
		563	.equ OCR1RB_14 = 6 ;
		564	.equ OCR1RB_15 = 7 ;
		565
		566	; OCR1RBL - Output Compare RB Register Low
		567	.equ OCR1RB_0 = 0 ;
		568	.equ OCR1RB_1 = 1 ;
		569	.equ OCR1RB_2 = 2 ;
		570	.equ OCR1RB_3 = 3 ;
		571	.equ OCR1RB_4 = 4 ;
		572	.equ OCR1RB_5 = 5 ;
		573	.equ OCR1RB_6 = 6 ;
		574	.equ OCR1RB_7 = 7 ;
		575
		576	; OCR1SBH - Output Compare SB Register High
		577	.equ OCR1SB_8 = 0 ;
		578	.equ OCR1SB_9 = 1 ;
		579	.equ OCR1SB_10 = 2 ;
		580	.equ OCR1SB_11 = 3 ;
		581
		582	; OCR1SBL - Output Compare SB Register Low
		583	.equ OCR1SB_0 = 0 ;
		584	.equ OCR1SB_1 = 1 ;
		585	.equ OCR1SB_2 = 2 ;
		586	.equ OCR1SB_3 = 3 ;
		587	.equ OCR1SB_4 = 4 ;
		588	.equ OCR1SB_5 = 5 ;
		589	.equ OCR1SB_6 = 6 ;
		590	.equ OCR1SB_7 = 7 ;
		591
		592	; OCR1RAH - Output Compare RA Register High
		593	.equ OCR1RA_8 = 0 ;
		594	.equ OCR1RA_9 = 1 ;
		595	.equ OCR1RA_10 = 2 ;
		596	.equ OCR1RA_11 = 3 ;
		597
		598	; OCR1RAL - Output Compare RA Register Low
		599	.equ OCR1RA_0 = 0 ;
		600	.equ OCR1RA_1 = 1 ;
		601	.equ OCR1RA_2 = 2 ;
		602	.equ OCR1RA_3 = 3 ;
		603	.equ OCR1RA_4 = 4 ;
		604	.equ OCR1RA_5 = 5 ;
		605	.equ OCR1RA_6 = 6 ;
		606	.equ OCR1RA_7 = 7 ;
		607
		608	; OCR1SAH - Output Compare SA Register High
		609	.equ OCR1SA_8 = 0 ;
		610	.equ OCR1SA_9 = 1 ;
		611	.equ OCR1SA_10 = 2 ;
		612	.equ OCR1SA_11 = 3 ;
		613
		614	; OCR1SAL - Output Compare SA Register Low
		615	.equ OCR1SA_0 = 0 ;
		616	.equ OCR1SA_1 = 1 ;
		617	.equ OCR1SA_2 = 2 ;
		618	.equ OCR1SA_3 = 3 ;
		619	.equ OCR1SA_4 = 4 ;
		620	.equ OCR1SA_5 = 5 ;
		621	.equ OCR1SA_6 = 6 ;
		622	.equ OCR1SA_7 = 7 ;
		623
		624	; PSOC1 - PSC1 Synchro and Output Configuration
		625	.equ POEN1A = 0 ; PSCOUT10 Output Enable
		626	.equ POEN1B = 2 ; PSCOUT11 Output Enable
		627	.equ PSYNC1_0 = 4 ; Synchronization Out for ADC Selection
		628	.equ PSYNC1_1 = 5 ; Synchronization Out for ADC Selection
		629
		630	; PIM1 - PSC1 Interrupt Mask Register
		631	.equ PEOPE1 = 0 ; End of Cycle Interrupt Enable
		632	.equ PEVE1A = 3 ; External Event A Interrupt Enable
		633	.equ PEVE1B = 4 ; External Event B Interrupt Enable
		634	.equ PSEIE1 = 5 ; PSC 1 Synchro Error Interrupt Enable
		635
		636	; PIFR1 - PSC1 Interrupt Flag Register
		637	.equ PEOP1 = 0 ; End of PSC1 Interrupt
		638	.equ PRN10 = 1 ; Ramp Number
		639	.equ PRN11 = 2 ; Ramp Number
		640	.equ PEV1A = 3 ; External Event A Interrupt
		641	.equ PEV1B = 4 ; External Event B Interrupt
		642	.equ PSEI1 = 5 ; PSC 1 Synchro Error Interrupt
		643
		644
		645	; *** PSC2 ***********************
		646	; PICR2H - PSC 2 Input Capture Register High
		647	.equ PICR2_8 = 0 ;
		648	.equ PICR2_9 = 1 ;
		649	.equ PICR2_10 = 2 ;
		650	.equ PICR2_11 = 3 ;
		651
		652	; PICR2L - PSC 2 Input Capture Register Low
		653	.equ PICR2_0 = 0 ;
		654	.equ PICR2_1 = 1 ;
		655	.equ PICR2_2 = 2 ;
		656	.equ PICR2_3 = 3 ;
		657	.equ PICR2_4 = 4 ;
		658	.equ PICR2_5 = 5 ;
		659	.equ PICR2_6 = 6 ;
		660	.equ PICR2_7 = 7 ;
		661
		662	; PFRC2B - PSC 2 Input B Control
		663	.equ PRFM2B0 = 0 ; PSC 2 Retrigger and Fault Mode for Part B
		664	.equ PRFM2B1 = 1 ; PSC 2 Retrigger and Fault Mode for Part B
		665	.equ PRFM2B2 = 2 ; PSC 2 Retrigger and Fault Mode for Part B
		666	.equ PRFM2B3 = 3 ; PSC 2 Retrigger and Fault Mode for Part B
		667	.equ PFLTE2B = 4 ; PSC 2 Filter Enable on Input Part B
		668	.equ PELEV2B = 5 ; PSC 2 Edge Level Selector on Input Part B
		669	.equ PISEL2B = 6 ; PSC 2 Input Select for Part B
		670	.equ PCAE2B = 7 ; PSC 2 Capture Enable Input Part B
		671
		672	; PFRC2A - PSC 2 Input B Control
		673	.equ PRFM2A0 = 0 ; PSC 2 Retrigger and Fault Mode for Part A
		674	.equ PRFM2A1 = 1 ; PSC 2 Retrigger and Fault Mode for Part A
		675	.equ PRFM2A2 = 2 ; PSC 2 Retrigger and Fault Mode for Part A
		676	.equ PRFM2A3 = 3 ; PSC 2 Retrigger and Fault Mode for Part A
		677	.equ PFLTE2A = 4 ; PSC 2 Filter Enable on Input Part A
		678	.equ PELEV2A = 5 ; PSC 2 Edge Level Selector on Input Part A
		679	.equ PISEL2A = 6 ; PSC 2 Input Select for Part A
		680	.equ PCAE2A = 7 ; PSC 2 Capture Enable Input Part A
		681
		682	; PCTL2 - PSC 2 Control Register
		683	.equ PRUN2 = 0 ; PSC 2 Run
		684	.equ PCCYC2 = 1 ; PSC2 Complete Cycle
		685	.equ PARUN2 = 2 ; PSC2 Auto Run
		686	.equ PAOC2A = 3 ; PSC 2 Asynchronous Output Control A
		687	.equ PAOC2B = 4 ; PSC 2 Asynchronous Output Control B
		688	.equ PBFM2 = 5 ; Balance Flank Width Modulation
		689	.equ PPRE20 = 6 ; PSC 2 Prescaler Select 0
		690	.equ PPRE21 = 7 ; PSC 2 Prescaler Select 1
		691
		692	; PCNF2 - PSC 2 Configuration Register
		693	.equ POME2 = 0 ; PSC 2 Output Matrix Enable
		694	.equ PCLKSEL2 = 1 ; PSC 2 Input Clock Select
		695	.equ POP2 = 2 ; PSC 2 Output Polarity
		696	.equ PMODE20 = 3 ; PSC 2 Mode
		697	.equ PMODE21 = 4 ; PSC 2 Mode
		698	.equ PLOCK2 = 5 ; PSC 2 Lock
		699	.equ PALOCK2 = 6 ; PSC 2 Autolock
		700	.equ PFIFTY2 = 7 ; PSC 2 Fifty
		701
		702	; OCR2RBH - Output Compare RB Register High
		703	.equ OCR2RB_8 = 0 ;
		704	.equ OCR2RB_9 = 1 ;
		705	.equ OCR2RB_10 = 2 ;
		706	.equ OCR2RB_11 = 3 ;
		707	.equ OCR2RB_12 = 4 ;
		708	.equ OCR2RB_13 = 5 ;
		709	.equ OCR2RB_14 = 6 ;
		710	.equ OCR2RB_15 = 7 ;
		711
		712	; OCR2RBL - Output Compare RB Register Low
		713	.equ OCR2RB_0 = 0 ;
		714	.equ OCR2RB_1 = 1 ;
		715	.equ OCR2RB_2 = 2 ;
		716	.equ OCR2RB_3 = 3 ;
		717	.equ OCR2RB_4 = 4 ;
		718	.equ OCR2RB_5 = 5 ;
		719	.equ OCR2RB_6 = 6 ;
		720	.equ OCR2RB_7 = 7 ;
		721
		722	; OCR2SBH - Output Compare SB Register High
		723	.equ OCR2SB_8 = 0 ;
		724	.equ OCR2SB_9 = 1 ;
		725	.equ OCR2SB_10 = 2 ;
		726	.equ OCR2SB_11 = 3 ;
		727
		728	; OCR2SBL - Output Compare SB Register Low
		729	.equ OCR2SB_0 = 0 ;
		730	.equ OCR2SB_1 = 1 ;
		731	.equ OCR2SB_2 = 2 ;
		732	.equ OCR2SB_3 = 3 ;
		733	.equ OCR2SB_4 = 4 ;
		734	.equ OCR2SB_5 = 5 ;
		735	.equ OCR2SB_6 = 6 ;
		736	.equ OCR2SB_7 = 7 ;
		737
		738	; OCR2RAH - Output Compare RA Register High
		739	.equ OCR2RA_8 = 0 ;
		740	.equ OCR2RA_9 = 1 ;
		741	.equ OCR2RA_10 = 2 ;
		742	.equ OCR2RA_11 = 3 ;
		743
		744	; OCR2RAL - Output Compare RA Register Low
		745	.equ OCR2RA_0 = 0 ;
		746	.equ OCR2RA_1 = 1 ;
		747	.equ OCR2RA_2 = 2 ;
		748	.equ OCR2RA_3 = 3 ;
		749	.equ OCR2RA_4 = 4 ;
		750	.equ OCR2RA_5 = 5 ;
		751	.equ OCR2RA_6 = 6 ;
		752	.equ OCR2RA_7 = 7 ;
		753
		754	; OCR2SAH - Output Compare SA Register High
		755	.equ OCR2SA_8 = 0 ;
		756	.equ OCR2SA_9 = 1 ;
		757	.equ OCR2SA_10 = 2 ;
		758	.equ OCR2SA_11 = 3 ;
		759
		760	; OCR2SAL - Output Compare SA Register Low
		761	.equ OCR2SA_0 = 0 ;
		762	.equ OCR2SA_1 = 1 ;
		763	.equ OCR2SA_2 = 2 ;
		764	.equ OCR2SA_3 = 3 ;
		765	.equ OCR2SA_4 = 4 ;
		766	.equ OCR2SA_5 = 5 ;
		767	.equ OCR2SA_6 = 6 ;
		768	.equ OCR2SA_7 = 7 ;
		769
		770	; POM2 - PSC 2 Output Matrix
		771	.equ POMV2A0 = 0 ; Output Matrix Output A Ramp 0
		772	.equ POMV2A1 = 1 ; Output Matrix Output A Ramp 1
		773	.equ POMV2A2 = 2 ; Output Matrix Output A Ramp 2
		774	.equ POMV2A3 = 3 ; Output Matrix Output A Ramp 3
		775	.equ POMV2B0 = 4 ; Output Matrix Output B Ramp 0
		776	.equ POMV2B1 = 5 ; Output Matrix Output B Ramp 2
		777	.equ POMV2B2 = 6 ; Output Matrix Output B Ramp 2
		778	.equ POMV2B3 = 7 ; Output Matrix Output B Ramp 3
		779
		780	; PSOC2 - PSC2 Synchro and Output Configuration
		781	.equ POEN2A = 0 ; PSCOUT20 Output Enable
		782	.equ POEN2C = 1 ; PSCOUT22 Output Enable
		783	.equ POEN2B = 2 ; PSCOUT21 Output Enable
		784	.equ POEN2D = 3 ; PSCOUT23 Output Enable
		785	.equ PSYNC2_0 = 4 ; Synchronization Out for ADC Selection
		786	.equ PSYNC2_1 = 5 ; Synchronization Out for ADC Selection
		787	.equ POS22 = 6 ; PSC 2 Output 22 Select
		788	.equ POS23 = 7 ; PSC 2 Output 23 Select
		789
		790	; PIM2 - PSC2 Interrupt Mask Register
		791	.equ PEOPE2 = 0 ; End of Cycle Interrupt Enable
		792	.equ PEVE2A = 3 ; External Event A Interrupt Enable
		793	.equ PEVE2B = 4 ; External Event B Interrupt Enable
		794	.equ PSEIE2 = 5 ; PSC 2 Synchro Error Interrupt Enable
		795
		796	; PIFR2 - PSC2 Interrupt Flag Register
		797	.equ PEOP2 = 0 ; End of PSC2 Interrupt
		798	.equ PRN20 = 1 ; Ramp Number
		799	.equ PRN21 = 2 ; Ramp Number
		800	.equ PEV2A = 3 ; External Event A Interrupt
		801	.equ PEV2B = 4 ; External Event B Interrupt
		802	.equ PSEI2 = 5 ; PSC 2 Synchro Error Interrupt
		803
		804
		805	; *** EUSART *********************
		806	; EUDR - EUSART I/O Data Register
		807	.equ EUDR0 = 0 ; EUSART I/O Data Register bit 0
		808	.equ EUDR1 = 1 ; EUSART I/O Data Register bit 1
		809	.equ EUDR2 = 2 ; EUSART I/O Data Register bit 2
		810	.equ EUDR3 = 3 ; EUSART I/O Data Register bit 3
		811	.equ EUDR4 = 4 ; EUSART I/O Data Register bit 4
		812	.equ EUDR5 = 5 ; EUSART I/O Data Register bit 5
		813	.equ EUDR6 = 6 ; EUSART I/O Data Register bit 6
		814	.equ EUDR7 = 7 ; EUSART I/O Data Register bit 7
		815
		816	; EUCSRA - EUSART Control and Status Register A
		817	.equ URxS0 = 0 ; EUSART Control and Status Register A Bit 0
		818	.equ URxS1 = 1 ; EUSART Control and Status Register A Bit 1
		819	.equ URxS2 = 2 ; EUSART Control and Status Register A Bit 2
		820	.equ URxS3 = 3 ; EUSART Control and Status Register A Bit 3
		821	.equ UTxS0 = 4 ; EUSART Control and Status Register A Bit 4
		822	.equ UTxS1 = 5 ; EUSART Control and Status Register A Bit 5
		823	.equ UTxS2 = 6 ; EUSART Control and Status Register A Bit 6
		824	.equ UTxS3 = 7 ; EUSART Control and Status Register A Bit 7
		825
		826	; EUCSRB - EUSART Control Register B
		827	.equ BODR = 0 ; Order Bit
		828	.equ EMCH = 1 ; Manchester Mode Bit
		829	.equ EUSBS = 3 ; EUSBS Enable Bit
		830	.equ EUSART = 4 ; EUSART Enable Bit
		831
		832	; EUCSRC - EUSART Status Register C
		833	.equ STP0 = 0 ; Stop Bit 0
		834	.equ STP1 = 1 ; Stop Bit 1
		835	.equ F1617 = 2 ; F1617 Bit
		836	.equ FEM = 3 ; Frame Error Manchester Bit
		837
		838	; MUBRRH - Manchester Receiver Baud Rate Register High Byte
		839	.equ MUBRR8 = 0 ; Manchester Receiver Baud Rate Register Bit 8
		840	.equ MUBRR9 = 1 ; Manchester Receiver Baud Rate Register Bit 9
		841	.equ MUBRR10 = 2 ; Manchester Receiver Baud Rate Register Bit 10
		842	.equ MUBRR11 = 3 ; Manchester Receiver Baud Rate Register Bit 11
		843	.equ MUBRR12 = 4 ; Manchester Receiver Baud Rate Register Bit 12
		844	.equ MUBRR13 = 5 ; Manchester Receiver Baud Rate Register Bit 13
		845	.equ MUBRR14 = 6 ; Manchester Receiver Baud Rate Register Bit 14
		846	.equ MUBRR15 = 7 ; Manchester Receiver Baud Rate Register Bit 15
		847
		848	; MUBRRL - Manchester Receiver Baud Rate Register Low Byte
		849	.equ MUBRR0 = 0 ; Manchester Receiver Baud Rate Register Bit 0
		850	.equ MUBRR1 = 1 ; Manchester Receiver Baud Rate Register Bit 1
		851	.equ MUBRR2 = 2 ; Manchester Receiver Baud Rate Register Bit 2
		852	.equ MUBRR3 = 3 ; Manchester Receiver Baud Rate Register Bit 3
		853	.equ MUBRR4 = 4 ; Manchester Receiver Baud Rate Register Bit 4
		854	.equ MUBRR5 = 5 ; Manchester Receiver Baud Rate Register Bit 5
		855	.equ MUBRR6 = 6 ; Manchester Receiver Baud Rate Register Bit 6
		856	.equ MUBRR7 = 7 ; Manchester Receiver Baud Rate Register Bit 7
		857
		858
		859	; *** ANALOG_COMPARATOR **********
		860	; AC0CON - Analog Comparator 0 Control Register
		861	.equ AC0M0 = 0 ; Analog Comparator 0 Multiplexer Register
		862	.equ AC0M1 = 1 ; Analog Comparator 0 Multiplexer Regsiter
		863	.equ AC0M2 = 2 ; Analog Comparator 0 Multiplexer Register
		864	.equ AC0IS0 = 4 ; Analog Comparator 0 Interrupt Select Bit
		865	.equ AC0IS1 = 5 ; Analog Comparator 0 Interrupt Select Bit
		866	.equ AC0IE = 6 ; Analog Comparator 0 Interrupt Enable Bit
		867	.equ AC0EN = 7 ; Analog Comparator 0 Enable Bit
		868
		869	; AC1CON - Analog Comparator 1 Control Register
		870	.equ AC1M0 = 0 ; Analog Comparator 1 Multiplexer Register
		871	.equ AC1M1 = 1 ; Analog Comparator 1 Multiplexer Regsiter
		872	.equ AC1M2 = 2 ; Analog Comparator 1 Multiplexer Register
		873	.equ AC1ICE = 3 ; Analog Comparator 1 Interrupt Capture Enable Bit
		874	.equ AC1IS0 = 4 ; Analog Comparator 1 Interrupt Select Bit
		875	.equ AC1IS1 = 5 ; Analog Comparator 1 Interrupt Select Bit
		876	.equ AC1IE = 6 ; Analog Comparator 1 Interrupt Enable Bit
		877	.equ AC1EN = 7 ; Analog Comparator 1 Enable Bit
		878
		879	; AC2CON - Analog Comparator 2 Control Register
		880	.equ AC2M0 = 0 ; Analog Comparator 2 Multiplexer Register
		881	.equ AC2M1 = 1 ; Analog Comparator 2 Multiplexer Regsiter
		882	.equ AC2M2 = 2 ; Analog Comparator 2 Multiplexer Register
		883	.equ AC2SADE = 3 ; Analog Comparator 2 Start A/D Conversion Enable Bit
		884	.equ AC2IS0 = 4 ; Analog Comparator 2 Interrupt Select Bit
		885	.equ AC2IS1 = 5 ; Analog Comparator 2 Interrupt Select Bit
		886	.equ AC2IE = 6 ; Analog Comparator 2 Interrupt Enable Bit
		887	.equ AC2EN = 7 ; Analog Comparator 2 Enable Bit
		888
		889
		890	; *** DA_CONVERTER ***************
		891	; DACH - DAC Data Register High Byte
		892	.equ DACH0 = 0 ; DAC Data Register High Byte Bit 0
		893	.equ DACH1 = 1 ; DAC Data Register High Byte Bit 1
		894	.equ DACH2 = 2 ; DAC Data Register High Byte Bit 2
		895	.equ DACH3 = 3 ; DAC Data Register High Byte Bit 3
		896	.equ DACH4 = 4 ; DAC Data Register High Byte Bit 4
		897	.equ DACH5 = 5 ; DAC Data Register High Byte Bit 5
		898	.equ DACH6 = 6 ; DAC Data Register High Byte Bit 6
		899	.equ DACH7 = 7 ; DAC Data Register High Byte Bit 7
		900
		901	; DACL - DAC Data Register Low Byte
		902	.equ DACL1 = 1 ; DAC Data Register Low Byte Bit 1
		903	.equ DACL2 = 2 ; DAC Data Register Low Byte Bit 2
		904	.equ DACL3 = 3 ; DAC Data Register Low Byte Bit 3
		905	.equ DACL4 = 4 ; DAC Data Register Low Byte Bit 4
		906	.equ DACL5 = 5 ; DAC Data Register Low Byte Bit 5
		907	.equ DACL6 = 6 ; DAC Data Register Low Byte Bit 6
		908	.equ DACL7 = 7 ; DAC Data Register Low Byte Bit 7
		909
		910	; DACON - DAC Control Register
		911	.equ DAEN = 0 ; DAC Enable Bit
		912	.equ DAOE = 1 ; DAC Output Enable Bit
		913	.equ DALA = 2 ; DAC Left Adjust
		914	.equ DATS0 = 4 ; DAC Trigger Selection Bit 0
		915	.equ DATS1 = 5 ; DAC Trigger Selection Bit 1
		916	.equ DATS2 = 6 ; DAC Trigger Selection Bit 2
		917	.equ DAATE = 7 ; DAC Auto Trigger Enable Bit
		918
		919
		920	; *** CPU ************************
		921	; SREG - Status Register
		922	.equ SREG_C = 0 ; Carry Flag
		923	.equ SREG_Z = 1 ; Zero Flag
		924	.equ SREG_N = 2 ; Negative Flag
		925	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		926	.equ SREG_S = 4
		927	.equ SREG_H = 5 ; Half Carry Flag
		928	.equ SREG_T = 6 ; Bit Copy Storage
		929	.equ SREG_I = 7 ; Global Interrupt Enable
		930
		931	; MCUCR - MCU Control Register
		932	.equ IVCE = 0 ; Interrupt Vector Change Enable
		933	.equ IVSEL = 1 ; Interrupt Vector Select
		934	.equ PUD = 4 ; Pull-up disable
		935	.equ SPIPS = 7 ; SPI Pin Select
		936
		937	; MCUSR - MCU Status Register
		938	.equ PORF = 0 ; Power-on reset flag
		939	.equ EXTRF = 1 ; External Reset Flag
		940	.equ BORF = 2 ; Brown-out Reset Flag
		941	.equ WDRF = 3 ; Watchdog Reset Flag
		942
		943	; OSCCAL - Oscillator Calibration Value
		944	.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
		945	.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
		946	.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
		947	.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
		948	.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
		949	.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
		950	.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
		951
		952	; CLKPR -
		953	.equ CLKPS0 = 0 ;
		954	.equ CLKPS1 = 1 ;
		955	.equ CLKPS2 = 2 ;
		956	.equ CLKPS3 = 3 ;
		957	.equ CPKPCE = 7 ;
		958
		959	; SMCR - Sleep Mode Control Register
		960	.equ SE = 0 ; Sleep Enable
		961	.equ SM0 = 1 ; Sleep Mode Select bit 0
		962	.equ SM1 = 2 ; Sleep Mode Select bit 1
		963	.equ SM2 = 3 ; Sleep Mode Select bit 2
		964
		965	; GPIOR3 - General Purpose IO Register 3
		966	.equ GPIOR30 = 0 ; General Purpose IO Register 3 bit 0
		967	.equ GPIOR31 = 1 ; General Purpose IO Register 3 bit 1
		968	.equ GPIOR32 = 2 ; General Purpose IO Register 3 bit 2
		969	.equ GPIOR33 = 3 ; General Purpose IO Register 3 bit 3
		970	.equ GPIOR34 = 4 ; General Purpose IO Register 3 bit 4
		971	.equ GPIOR35 = 5 ; General Purpose IO Register 3 bit 5
		972	.equ GPIOR36 = 6 ; General Purpose IO Register 3 bit 6
		973	.equ GPIOR37 = 7 ; General Purpose IO Register 3 bit 7
		974
		975	; GPIOR2 - General Purpose IO Register 2
		976	.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
		977	.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
		978	.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
		979	.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
		980	.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
		981	.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
		982	.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
		983	.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
		984
		985	; GPIOR1 - General Purpose IO Register 1
		986	.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
		987	.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
		988	.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
		989	.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
		990	.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
		991	.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
		992	.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
		993	.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
		994
		995	; GPIOR0 - General Purpose IO Register 0
		996	.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
		997	.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
		998	.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
		999	.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
		1000	.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
		1001	.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
		1002	.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
		1003	.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
		1004
		1005	; PLLCSR - PLL Control And Status Register
		1006	.equ PLOCK = 0 ; PLL Lock Detector
		1007	.equ PLLE = 1 ; PLL Enable
		1008	.equ PCKE = 2 ; PCK Enable
		1009
		1010
		1011	; *** PORTE **********************
		1012	; PORTE - Port E Data Register
		1013	.equ PORTE0 = 0 ;
		1014	.equ PE0 = 0 ; For compatibility
		1015	.equ PORTE1 = 1 ;
		1016	.equ PE1 = 1 ; For compatibility
		1017	.equ PORTE2 = 2 ;
		1018	.equ PE2 = 2 ; For compatibility
		1019
		1020	; DDRE - Port E Data Direction Register
		1021	.equ DDE0 = 0 ;
		1022	.equ DDE1 = 1 ;
		1023	.equ DDE2 = 2 ;
		1024
		1025	; PINE - Port E Input Pins
		1026	.equ PINE0 = 0 ;
		1027	.equ PINE1 = 1 ;
		1028	.equ PINE2 = 2 ;
		1029
		1030
		1031	; *** TIMER_COUNTER_0 ************
		1032	; TIMSK0 - Timer/Counter0 Interrupt Mask Register
		1033	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		1034	.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
		1035	.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
		1036
		1037	; TIFR0 - Timer/Counter0 Interrupt Flag register
		1038	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		1039	.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
		1040	.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
		1041
		1042	; TCCR0A - Timer/Counter Control Register A
		1043	.equ WGM00 = 0 ; Waveform Generation Mode
		1044	.equ WGM01 = 1 ; Waveform Generation Mode
		1045	.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
		1046	.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
		1047	.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
		1048	.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
		1049
		1050	; TCCR0B - Timer/Counter Control Register B
		1051	.equ CS00 = 0 ; Clock Select
		1052	.equ CS01 = 1 ; Clock Select
		1053	.equ CS02 = 2 ; Clock Select
		1054	.equ WGM02 = 3 ;
		1055	.equ FOC0B = 6 ; Force Output Compare B
		1056	.equ FOC0A = 7 ; Force Output Compare A
		1057
		1058	; TCNT0 - Timer/Counter0
		1059	.equ TCNT0_0 = 0 ;
		1060	.equ TCNT0_1 = 1 ;
		1061	.equ TCNT0_2 = 2 ;
		1062	.equ TCNT0_3 = 3 ;
		1063	.equ TCNT0_4 = 4 ;
		1064	.equ TCNT0_5 = 5 ;
		1065	.equ TCNT0_6 = 6 ;
		1066	.equ TCNT0_7 = 7 ;
		1067
		1068	; OCR0A - Timer/Counter0 Output Compare Register
		1069	.equ OCR0_0 = 0 ;
		1070	.equ OCR0_1 = 1 ;
		1071	.equ OCR0_2 = 2 ;
		1072	.equ OCR0_3 = 3 ;
		1073	.equ OCR0_4 = 4 ;
		1074	.equ OCR0_5 = 5 ;
		1075	.equ OCR0_6 = 6 ;
		1076	.equ OCR0_7 = 7 ;
		1077
		1078	; OCR0B - Timer/Counter0 Output Compare Register
		1079	;.equ OCR0_0 = 0 ;
		1080	;.equ OCR0_1 = 1 ;
		1081	;.equ OCR0_2 = 2 ;
		1082	;.equ OCR0_3 = 3 ;
		1083	;.equ OCR0_4 = 4 ;
		1084	;.equ OCR0_5 = 5 ;
		1085	;.equ OCR0_6 = 6 ;
		1086	;.equ OCR0_7 = 7 ;
		1087
		1088	; GTCCR - General Timer/Counter Control Register
		1089	.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
		1090	.equ ICPSEL1 = 6 ; Timer1 Input Capture Selection Bit
		1091	.equ TSM = 7 ; Timer/Counter Synchronization Mode
		1092
		1093
		1094	; *** TIMER_COUNTER_1 ************
		1095	; TIMSK1 - Timer/Counter Interrupt Mask Register
		1096	.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
		1097	.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		1098	.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		1099	.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		1100
		1101	; TIFR1 - Timer/Counter Interrupt Flag register
		1102	.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
		1103	.equ OCF1A = 1 ; Output Compare Flag 1A
		1104	.equ OCF1B = 2 ; Output Compare Flag 1B
		1105	.equ ICF1 = 5 ; Input Capture Flag 1
		1106
		1107	; TCCR1A - Timer/Counter1 Control Register A
		1108	.equ WGM10 = 0 ; Waveform Generation Mode
		1109	.equ WGM11 = 1 ; Waveform Generation Mode
		1110	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		1111	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		1112	.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
		1113	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		1114
		1115	; TCCR1B - Timer/Counter1 Control Register B
		1116	.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
		1117	.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
		1118	.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
		1119	.equ WGM12 = 3 ; Waveform Generation Mode
		1120	.equ WGM13 = 4 ; Waveform Generation Mode
		1121	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		1122	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		1123
		1124	; TCCR1C - Timer/Counter1 Control Register C
		1125	.equ FOC1B = 6 ;
		1126	.equ FOC1A = 7 ;
		1127
		1128	; GTCCR - General Timer/Counter Control Register
		1129	.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
		1130	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		1131
		1132
		1133	; *** AD_CONVERTER ***************
		1134	; ADMUX - The ADC multiplexer Selection Register
		1135	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		1136	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		1137	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		1138	.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
		1139	.equ ADLAR = 5 ; Left Adjust Result
		1140	.equ REFS0 = 6 ; Reference Selection Bit 0
		1141	.equ REFS1 = 7 ; Reference Selection Bit 1
		1142
		1143	; ADCSRA - The ADC Control and Status register
		1144	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		1145	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		1146	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		1147	.equ ADIE = 3 ; ADC Interrupt Enable
		1148	.equ ADIF = 4 ; ADC Interrupt Flag
		1149	.equ ADATE = 5 ; ADC Auto Trigger Enable
		1150	.equ ADSC = 6 ; ADC Start Conversion
		1151	.equ ADEN = 7 ; ADC Enable
		1152
		1153	; ADCH - ADC Data Register High Byte
		1154	.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
		1155	.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
		1156	.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
		1157	.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
		1158	.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
		1159	.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
		1160	.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
		1161	.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
		1162
		1163	; ADCL - ADC Data Register Low Byte
		1164	.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
		1165	.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
		1166	.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
		1167	.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
		1168	.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
		1169	.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
		1170	.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
		1171	.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
		1172
		1173	; ADCSRB - ADC Control and Status Register B
		1174	.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
		1175	.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
		1176	.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
		1177	.equ ADASCR = 3 ;
		1178	.equ ADAP = 4 ;
		1179
		1180	; DIDR0 - Digital Input Disable Register 0
		1181	.equ ADC0D = 0 ; ADC0 Digital input Disable
		1182	.equ ADC1D = 1 ; ADC1 Digital input Disable
		1183	.equ ADC2D = 2 ; ADC2 Digital input Disable
		1184	.equ ADC3D = 3 ; ADC3 Digital input Disable
		1185	.equ ADC4D = 4 ; ADC4 Digital input Disable
		1186	.equ ADC5D = 5 ; ADC5 Digital input Disable
		1187	.equ ADC6D = 6 ; ADC6 Digital input Disable
		1188	.equ ADC7D = 7 ; ADC7 Digital input Disable
		1189
		1190	; DIDR1 -
		1191	.equ ADC8D = 0 ;
		1192	.equ ADC9D = 1 ;
		1193	.equ ADC10D = 2 ;
		1194	.equ AMP0ND = 3 ;
		1195	.equ AMP0PD = 4 ;
		1196	.equ ACMP0D = 5 ;
		1197
		1198
		1199	; *** USART **********************
		1200	; UDR - USART I/O Data Register
		1201	.equ UDR0 = 0 ; USART I/O Data Register bit 0
		1202	.equ UDR1 = 1 ; USART I/O Data Register bit 1
		1203	.equ UDR2 = 2 ; USART I/O Data Register bit 2
		1204	.equ UDR3 = 3 ; USART I/O Data Register bit 3
		1205	.equ UDR4 = 4 ; USART I/O Data Register bit 4
		1206	.equ UDR5 = 5 ; USART I/O Data Register bit 5
		1207	.equ UDR6 = 6 ; USART I/O Data Register bit 6
		1208	.equ UDR7 = 7 ; USART I/O Data Register bit 7
		1209
		1210	; UCSRA - USART Control and Status register A
		1211	.equ MPCM = 0 ; Multi-processor Communication Mode
		1212	.equ U2X = 1 ; Double USART Transmission Bit
		1213	.equ UPE = 2 ; USART Parity Error
		1214	.equ DOR = 3 ; Data Overrun
		1215	.equ FE = 4 ; Framing Error
		1216	.equ UDRE = 5 ; USART Data Register Empty
		1217	.equ TXC = 6 ; USART Transmitt Complete
		1218	.equ RXC = 7 ; USART Receive Complete
		1219
		1220	; UCSRB - USART Control an Status register B
		1221	.equ TXB8 = 0 ; Transmit Data Bit 8
		1222	.equ RXB8 = 1 ; Receive Data Bit 8
		1223	.equ UCSZ2 = 2 ; Character Size
		1224	.equ TXEN = 3 ; Transmitter Enable
		1225	.equ RXEN = 4 ; Receiver Enable
		1226	.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable
		1227	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		1228	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		1229
		1230	; UCSRC - USART Control an Status register C
		1231	.equ UCPOL = 0 ; Clock Polarity
		1232	.equ UCSZ0 = 1 ; Character Size Bit 0
		1233	.equ UCSZ1 = 2 ; Character Size Bit 1
		1234	.equ USBS = 3 ; Stop Bit Select
		1235	.equ UPM0 = 4 ; Parity Mode Bit 0
		1236	.equ UPM1 = 5 ; Parity Mode Bit 1
		1237	.equ UMSEL0 = 6 ; USART Mode Select
		1238
		1239	; UBRRH - USART Baud Rate Register High Byte
		1240	.equ UBRR8 = 0 ; USART Baud Rate Register Bit 8
		1241	.equ UBRR9 = 1 ; USART Baud Rate Register Bit 9
		1242	.equ UBRR10 = 2 ; USART Baud Rate Register Bit 10
		1243	.equ UBRR11 = 3 ; USART Baud Rate Register Bit 11
		1244
		1245	; UBRRL - USART Baud Rate Register Low Byte
		1246	.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
		1247	.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
		1248	.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
		1249	.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
		1250	.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
		1251	.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
		1252	.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
		1253	.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
		1254
		1255
		1256	; *** SPI ************************
		1257	; SPDR - SPI Data Register
		1258	.equ SPDR0 = 0 ; SPI Data Register bit 0
		1259	.equ SPDR1 = 1 ; SPI Data Register bit 1
		1260	.equ SPDR2 = 2 ; SPI Data Register bit 2
		1261	.equ SPDR3 = 3 ; SPI Data Register bit 3
		1262	.equ SPDR4 = 4 ; SPI Data Register bit 4
		1263	.equ SPDR5 = 5 ; SPI Data Register bit 5
		1264	.equ SPDR6 = 6 ; SPI Data Register bit 6
		1265	.equ SPDR7 = 7 ; SPI Data Register bit 7
		1266
		1267	; SPSR - SPI Status Register
		1268	.equ SPI2X = 0 ; Double SPI Speed Bit
		1269	.equ WCOL = 6 ; Write Collision Flag
		1270	.equ SPIF = 7 ; SPI Interrupt Flag
		1271
		1272	; SPCR - SPI Control Register
		1273	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		1274	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		1275	.equ CPHA = 2 ; Clock Phase
		1276	.equ CPOL = 3 ; Clock polarity
		1277	.equ MSTR = 4 ; Master/Slave Select
		1278	.equ DORD = 5 ; Data Order
		1279	.equ SPE = 6 ; SPI Enable
		1280	.equ SPIE = 7 ; SPI Interrupt Enable
		1281
		1282
		1283	; *** WATCHDOG *******************
		1284	; WDTCSR - Watchdog Timer Control Register
		1285	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		1286	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		1287	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		1288	.equ WDE = 3 ; Watch Dog Enable
		1289	.equ WDCE = 4 ; Watchdog Change Enable
		1290	.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
		1291	.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
		1292	.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
		1293
		1294
		1295	; *** EXTERNAL_INTERRUPT *********
		1296	; EICRA - External Interrupt Control Register A
		1297	.equ ISC00 = 0 ; External Interrupt Sense Control Bit
		1298	.equ ISC01 = 1 ; External Interrupt Sense Control Bit
		1299	.equ ISC10 = 2 ; External Interrupt Sense Control Bit
		1300	.equ ISC11 = 3 ; External Interrupt Sense Control Bit
		1301	.equ ISC20 = 4 ; External Interrupt Sense Control Bit
		1302	.equ ISC21 = 5 ; External Interrupt Sense Control Bit
		1303	.equ ISC30 = 6 ; External Interrupt Sense Control Bit
		1304	.equ ISC31 = 7 ; External Interrupt Sense Control Bit
		1305
		1306	; EIMSK - External Interrupt Mask Register
		1307	.equ INT0 = 0 ; External Interrupt Request 0 Enable
		1308	.equ INT1 = 1 ; External Interrupt Request 1 Enable
		1309	.equ INT2 = 2 ; External Interrupt Request 2 Enable
		1310	.equ INT3 = 3 ; External Interrupt Request 3 Enable
		1311
		1312	; EIFR - External Interrupt Flag Register
		1313	.equ INTF0 = 0 ; External Interrupt Flag 0
		1314	.equ INTF1 = 1 ; External Interrupt Flag 1
		1315	.equ INTF2 = 2 ; External Interrupt Flag 2
		1316	.equ INTF3 = 3 ; External Interrupt Flag 3
		1317
		1318
		1319
		1320	; *** LOCKSBITS ******************************************************
		1321	.equ LB1 = 0 ; Lock bit
		1322	.equ LB2 = 1 ; Lock bit
		1323	.equ BLB01 = 2 ; Boot Lock bit
		1324	.equ BLB02 = 3 ; Boot Lock bit
		1325	.equ BLB11 = 4 ; Boot lock bit
		1326	.equ BLB12 = 5 ; Boot lock bit
		1327
		1328
		1329	; *** FUSES **********************************************************
		1330	; LOW fuse bits
		1331	.equ CKSEL0 = 0 ; Select Clock Source
		1332	.equ CKSEL1 = 1 ; Select Clock Source
		1333	.equ CKSEL2 = 2 ; Select Clock Source
		1334	.equ CKSEL3 = 3 ; Select Clock Source
		1335	.equ SUT0 = 4 ; Select start-up time
		1336	.equ SUT1 = 5 ; Select start-up time
		1337	.equ CKOUT = 6 ; Oscillator output option
		1338	.equ CLKDIV8 = 7 ; Divide clock by 8
		1339
		1340	; HIGH fuse bits
		1341	.equ BOOTRST = 0 ; Select Reset Vector
		1342	.equ BOOTSZ0 = 1 ; Select Boot Size
		1343	.equ BOOTSZ1 = 2 ; Select Boot Size
		1344	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		1345	.equ WDTON = 4 ; Watchdog timer always on
		1346	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		1347	.equ JTAGEN = 6 ; Enable JTAG
		1348	.equ OCDEN = 7 ; Enable OCD
		1349
		1350	; EXTENDED fuse bits
		1351	.equ TA0SEL = 0 ; (Reserved to factory tests)
		1352	.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level
		1353	.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level
		1354	.equ BODLEVEL2 = 3 ; Brown out detector trigger level
		1355
		1356
		1357
		1358	; *** CPU REGISTER DEFINITIONS ***************************************
		1359	.def XH = r27
		1360	.def XL = r26
		1361	.def YH = r29
		1362	.def YL = r28
		1363	.def ZH = r31
		1364	.def ZL = r30
		1365
		1366
		1367
		1368	; *** DATA MEMORY DECLARATIONS ***************************************
		1369	.equ FLASHEND = 0x0fff ; Note: Word address
		1370	.equ IOEND = 0x00ff
		1371	.equ SRAM_START = 0x0100
		1372	.equ SRAM_SIZE = 512
		1373	.equ RAMEND = 0x02ff
		1374	.equ XRAMEND = 0x0000
		1375	.equ E2END = 0x01ff
		1376	.equ EEPROMEND = 0x01ff
		1377	.equ EEADRBITS = 9
		1378	#pragma AVRPART MEMORY PROG_FLASH 8192
		1379	#pragma AVRPART MEMORY EEPROM 512
		1380	#pragma AVRPART MEMORY INT_SRAM SIZE 512
		1381	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
		1382
		1383
		1384
		1385	; *** BOOTLOADER DECLARATIONS ****************************************
		1386	.equ NRWW_START_ADDR = 0xc00
		1387	.equ NRWW_STOP_ADDR = 0xfff
		1388	.equ RWW_START_ADDR = 0x0
		1389	.equ RWW_STOP_ADDR = 0xbff
		1390	.equ PAGESIZE = 32
		1391	.equ FIRSTBOOTSTART = 0xf80
		1392	.equ SECONDBOOTSTART = 0xf00
		1393	.equ THIRDBOOTSTART = 0xe00
		1394	.equ FOURTHBOOTSTART = 0xc00
		1395	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		1396	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		1397
		1398
		1399
		1400	; *** INTERRUPT VECTORS **********************************************
		1401	.equ PSC2_CAPTaddr = 0x0001 ; PSC2 Capture Event
		1402	.equ PSC2_ECaddr = 0x0002 ; PSC2 End Cycle
		1403	.equ PSC1_CAPTaddr = 0x0003 ; PSC1 Capture Event
		1404	.equ PSC1_ECaddr = 0x0004 ; PSC1 End Cycle
		1405	.equ PSC0_CAPTaddr = 0x0005 ; PSC0 Capture Event
		1406	.equ PSC0_ECaddr = 0x0006 ; PSC0 End Cycle
		1407	.equ ACI0addr = 0x0007 ; Analog Comparator 0
		1408	.equ ACI1addr = 0x0008 ; Analog Comparator 1
		1409	.equ ACI2addr = 0x0009 ; Analog Comparator 2
		1410	.equ INT0addr = 0x000a ; External Interrupt Request 0
		1411	.equ ICP1addr = 0x000b ; Timer/Counter1 Capture Event
		1412	.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A
		1413	.equ OC1Baddr = 0x000d ; Timer/Counter Compare Match B
		1414	.equ OVF1addr = 0x000f ; Timer/Counter1 Overflow
		1415	.equ OC0Aaddr = 0x0010 ; Timer/Counter0 Compare Match A
		1416	.equ OVF0addr = 0x0011 ; Timer/Counter0 Overflow
		1417	.equ ADCCaddr = 0x0012 ; ADC Conversion Complete
		1418	.equ INT1addr = 0x0013 ; External Interrupt Request 1
		1419	.equ SPIaddr = 0x0014 ; SPI Serial Transfer Complete
		1420	.equ URXCaddr = 0x0015 ; USART, Rx Complete
		1421	.equ UDREaddr = 0x0016 ; USART Data Register Empty
		1422	.equ UTXCaddr = 0x0017 ; USART, Tx Complete
		1423	.equ INT2addr = 0x0018 ; External Interrupt Request 2
		1424	.equ WDTaddr = 0x0019 ; Watchdog Timeout Interrupt
		1425	.equ ERDYaddr = 0x001a ; EEPROM Ready
		1426	.equ OC0Baddr = 0x001b ; Timer Counter 0 Compare Match B
		1427	.equ INT3addr = 0x001c ; External Interrupt Request 3
		1428	.equ SPMRaddr = 0x001f ; Store Program Memory Read
		1429
		1430	.equ INT_VECTORS_SIZE = 29 ; size in words
		1431
		1432	#endif /* _PWM3DEF_INC_ */
		1433
		1434	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/pwm3def.inc – Rev 6400