WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m8515def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:31 *** Source: ATmega8515.xml ********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m8515def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega8515
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega8515
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M8515DEF_INC_
		41	#define _M8515DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega8515
		48	#pragma AVRPART ADMIN PART_NAME ATmega8515
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x93
		51	.equ SIGNATURE_002 = 0x06
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ SREG = 0x3f
		61	.equ SPH = 0x3e
		62	.equ SPL = 0x3d
		63	.equ GICR = 0x3b
		64	.equ GIFR = 0x3a
		65	.equ TIMSK = 0x39
		66	.equ TIFR = 0x38
		67	.equ SPMCR = 0x37
		68	.equ EMCUCR = 0x36
		69	.equ MCUCR = 0x35
		70	.equ MCUCSR = 0x34
		71	.equ TCCR0 = 0x33
		72	.equ TCNT0 = 0x32
		73	.equ OCR0 = 0x31
		74	.equ SFIOR = 0x30
		75	.equ TCCR1A = 0x2f
		76	.equ TCCR1B = 0x2e
		77	.equ TCNT1H = 0x2d
		78	.equ TCNT1L = 0x2c
		79	.equ OCR1AH = 0x2b
		80	.equ OCR1AL = 0x2a
		81	.equ OCR1BH = 0x29
		82	.equ OCR1BL = 0x28
		83	.equ ICR1H = 0x25
		84	.equ ICR1L = 0x24
		85	.equ WDTCR = 0x21
		86	.equ UBRRH = 0x20
		87	.equ UCSRC = 0x20
		88	.equ EEARH = 0x1f
		89	.equ EEARL = 0x1e
		90	.equ EEDR = 0x1d
		91	.equ EECR = 0x1c
		92	.equ PORTA = 0x1b
		93	.equ DDRA = 0x1a
		94	.equ PINA = 0x19
		95	.equ PORTB = 0x18
		96	.equ DDRB = 0x17
		97	.equ PINB = 0x16
		98	.equ PORTC = 0x15
		99	.equ DDRC = 0x14
		100	.equ PINC = 0x13
		101	.equ PORTD = 0x12
		102	.equ DDRD = 0x11
		103	.equ PIND = 0x10
		104	.equ SPDR = 0x0f
		105	.equ SPSR = 0x0e
		106	.equ SPCR = 0x0d
		107	.equ UDR = 0x0c
		108	.equ UCSRA = 0x0b
		109	.equ UCSRB = 0x0a
		110	.equ UBRRL = 0x09
		111	.equ ACSR = 0x08
		112	.equ PORTE = 0x07
		113	.equ DDRE = 0x06
		114	.equ PINE = 0x05
		115	.equ OSCCAL = 0x04
		116
		117
		118	; *** BIT DEFINITIONS ************************************************
		119
		120	; *** ANALOG_COMPARATOR **********
		121	; ACSR - Analog Comparator Control And Status Register
		122	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		123	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		124	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		125	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		126	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		127	.equ ACO = 5 ; Analog Compare Output
		128	.equ ACBG = 6 ; Analog Comparator Bandgap Select
		129	.equ AINBG = ACBG ; For compatibility
		130	.equ ACD = 7 ; Analog Comparator Disable
		131
		132
		133	; *** USART **********************
		134	; UDR - USART I/O Data Register
		135	.equ UDR0 = 0 ; USART I/O Data Register bit 0
		136	.equ UDR1 = 1 ; USART I/O Data Register bit 1
		137	.equ UDR2 = 2 ; USART I/O Data Register bit 2
		138	.equ UDR3 = 3 ; USART I/O Data Register bit 3
		139	.equ UDR4 = 4 ; USART I/O Data Register bit 4
		140	.equ UDR5 = 5 ; USART I/O Data Register bit 5
		141	.equ UDR6 = 6 ; USART I/O Data Register bit 6
		142	.equ UDR7 = 7 ; USART I/O Data Register bit 7
		143
		144	; UCSRA - USART Control and Status Register A
		145	.equ MPCM = 0 ; Multi-processor Communication Mode
		146	.equ U2X = 1 ; Double the USART transmission speed
		147	.equ UPE = 2 ; Parity Error
		148	.equ PE = UPE ; For compatibility
		149	.equ DOR = 3 ; Data overRun
		150	.equ FE = 4 ; Framing Error
		151	.equ UDRE = 5 ; USART Data Register Empty
		152	.equ TXC = 6 ; USART Transmitt Complete
		153	.equ RXC = 7 ; USART Receive Complete
		154
		155	; UCSRB - USART Control and Status Register B
		156	.equ TXB8 = 0 ; Transmit Data Bit 8
		157	.equ RXB8 = 1 ; Receive Data Bit 8
		158	.equ UCSZ2 = 2 ; Character Size Bit 2
		159	.equ CHR9 = UCSZ2 ; For compatibility
		160	.equ TXEN = 3 ; Transmitter Enable
		161	.equ RXEN = 4 ; Receiver Enable
		162	.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
		163	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		164	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		165
		166	; UCSRC - USART Control and Status Register C
		167	.equ UCPOL = 0 ; Clock Polarity
		168	.equ UCSZ0 = 1 ; Character Size Bit 0
		169	.equ UCSZ1 = 2 ; Character Size Bit 1
		170	.equ USBS = 3 ; Stop Bit Select
		171	.equ UPM0 = 4 ; Parity Mode Bit 0
		172	.equ UPM1 = 5 ; Parity Mode Bit 1
		173	.equ UMSEL = 6 ; USART Mode Select
		174	.equ URSEL = 7 ; Register Select
		175
		176	; UBRRH - USART Baud Rate Register High Byte
		177	.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
		178	.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
		179	.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
		180	.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
		181	;.equ URSEL = 7 ; Register Select
		182
		183
		184	; *** SPI ************************
		185	; SPDR - SPI Data Register
		186	.equ SPDR0 = 0 ; SPI Data Register bit 0
		187	.equ SPDR1 = 1 ; SPI Data Register bit 1
		188	.equ SPDR2 = 2 ; SPI Data Register bit 2
		189	.equ SPDR3 = 3 ; SPI Data Register bit 3
		190	.equ SPDR4 = 4 ; SPI Data Register bit 4
		191	.equ SPDR5 = 5 ; SPI Data Register bit 5
		192	.equ SPDR6 = 6 ; SPI Data Register bit 6
		193	.equ SPDR7 = 7 ; SPI Data Register bit 7
		194
		195	; SPSR - SPI Status Register
		196	.equ SPI2X = 0 ; Double SPI Speed Bit
		197	.equ WCOL = 6 ; Write Collision Flag
		198	.equ SPIF = 7 ; SPI Interrupt Flag
		199
		200	; SPCR - SPI Control Register
		201	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		202	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		203	.equ CPHA = 2 ; Clock Phase
		204	.equ CPOL = 3 ; Clock polarity
		205	.equ MSTR = 4 ; Master/Slave Select
		206	.equ DORD = 5 ; Data Order
		207	.equ SPE = 6 ; SPI Enable
		208	.equ SPIE = 7 ; SPI Interrupt Enable
		209
		210
		211	; *** CPU ************************
		212	; SREG - Status Register
		213	.equ SREG_C = 0 ; Carry Flag
		214	.equ SREG_Z = 1 ; Zero Flag
		215	.equ SREG_N = 2 ; Negative Flag
		216	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		217	.equ SREG_S = 4 ; Sign Bit
		218	.equ SREG_H = 5 ; Half Carry Flag
		219	.equ SREG_T = 6 ; Bit Copy Storage
		220	.equ SREG_I = 7 ; Global Interrupt Enable
		221
		222	; EMCUCR - Extended MCU Control Register
		223	.equ ISC2 = 0 ; Interrupt Sense Control 2
		224	.equ SRW11 = 1 ; Wait State Select Bits for Upper Sector, bit 1
		225	.equ SRW00 = 2 ; Wait State Select Bits for Lower Sector, bit 0
		226	.equ SRW01 = 3 ; Wait State Select Bits for Lower Sector, bit 1
		227	.equ SRL0 = 4 ; Wait State Selector Limit bit 0
		228	.equ SRL1 = 5 ; Wait State Selector Limit bit 1
		229	.equ SRL2 = 6 ; Wait State Selector Limit bit 2
		230	.equ SM0 = 7 ; Sleep Mode Select Bit 0
		231
		232	; MCUCR - MCU Control Register
		233	.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
		234	.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
		235	.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
		236	.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
		237	.equ SM1 = 4 ; Sleep Mode Select Bit 1
		238	.equ SE = 5 ; Sleep Enable
		239	.equ SRW10 = 6 ; Wait State Select Bits for Upper Sector, bit 0
		240	.equ SRE = 7 ; External SRAM/XMEM Enable
		241
		242	; MCUCSR - MCU Control And Status Register
		243	.equ MCUSR = MCUCSR ; For compatibility
		244	.equ PORF = 0 ; Power-on reset flag
		245	.equ EXTRF = 1 ; External Reset Flag
		246	.equ BORF = 2 ; Brown-out Reset Flag
		247	.equ WDRF = 3 ; Watchdog Reset Flag
		248	.equ SM2 = 5 ; Sleep Mode Select Bit 2
		249
		250	; OSCCAL - Oscillator Calibration Value
		251	.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
		252	.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
		253	.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
		254	.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
		255	.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
		256	.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
		257	.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
		258	.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
		259
		260	; SPMCR - Store Program Memory Control Register
		261	.equ SPMEN = 0 ; Store Program Memory Enable
		262	.equ PGERS = 1 ; Page Erase
		263	.equ PGWRT = 2 ; Page Write
		264	.equ BLBSET = 3 ; Boot Lock Bit Set
		265	.equ RWWSRE = 4 ; Read-While-Write Section Read Enable
		266	.equ ASRE = RWWSRE ; For compatibility
		267	.equ RWWSB = 6 ; Read-While-Write Section Busy
		268	.equ ASB = RWWSB ; For compatibility
		269	.equ SPMIE = 7 ; SPM Interrupt Enable
		270
		271	; SFIOR - Special Function IO Register
		272	.equ PSR10 = 0 ; Prescaler Reset Timer / Counter 1 and Timer / Counter 0
		273	.equ PUD = 2 ; Pull-up Disable
		274	.equ XMM0 = 3 ; External Memory High Mask Bit 0
		275	.equ XMM1 = 4 ; External Memory High Mask Bit 1
		276	.equ XMM2 = 5 ; External Memory High Mask Bit 2
		277	.equ XMBK = 6 ; External Memory Bus Keeper Enable
		278
		279
		280	; *** EXTERNAL_INTERRUPT *********
		281	; GICR - General Interrupt Control Register
		282	.equ GIMSK = GICR ; For compatibility
		283	.equ IVCE = 0 ; Interrupt Vector Change Enable
		284	.equ IVSEL = 1 ; Interrupt Vector Select
		285	.equ INT2 = 5 ; External Interrupt Request 2 Enable
		286	.equ INT0 = 6 ; External Interrupt Request 0 Enable
		287	.equ INT1 = 7 ; External Interrupt Request 1 Enable
		288
		289	; GIFR - General Interrupt Flag Register
		290	.equ INTF2 = 5 ; External Interrupt Flag 2
		291	.equ INTF0 = 6 ; External Interrupt Flag 0
		292	.equ INTF1 = 7 ; External Interrupt Flag 1
		293
		294
		295	; *** WATCHDOG *******************
		296	; WDTCR - Watchdog Timer Control Register
		297	.equ WDTCSR = WDTCR ; For compatibility
		298	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		299	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		300	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		301	.equ WDE = 3 ; Watch Dog Enable
		302	.equ WDCE = 4 ; Watchdog Change Enable
		303	.equ WDTOE = WDCE ; For compatibility
		304
		305
		306	; *** TIMER_COUNTER_0 ************
		307	; TCCR0 - Timer/Counter 0 Control Register
		308	.equ CS00 = 0 ; Clock Select 1
		309	.equ CS01 = 1 ; Clock Select 1
		310	.equ CS02 = 2 ; Clock Select 2
		311	.equ WGM01 = 3 ; Waveform Generation Mode 1
		312	.equ CTC0 = WGM01 ; For compatibility
		313	.equ COM00 = 4 ; Compare match Output Mode 0
		314	.equ COM01 = 5 ; Compare Match Output Mode 1
		315	.equ WGM00 = 6 ; Waveform Generation Mode 0
		316	.equ PWM0 = WGM00 ; For compatibility
		317	.equ FOC0 = 7 ; Force Output Compare
		318
		319	; TCNT0 - Timer/Counter 0 Register
		320	.equ TCNT0_0 = 0 ;
		321	.equ TCNT0_1 = 1 ;
		322	.equ TCNT0_2 = 2 ;
		323	.equ TCNT0_3 = 3 ;
		324	.equ TCNT0_4 = 4 ;
		325	.equ TCNT0_5 = 5 ;
		326	.equ TCNT0_6 = 6 ;
		327	.equ TCNT0_7 = 7 ;
		328
		329	; OCR0 - Timer/Counter 0 Output Compare Register
		330	.equ OCR0_0 = 0 ;
		331	.equ OCR0_1 = 1 ;
		332	.equ OCR0_2 = 2 ;
		333	.equ OCR0_3 = 3 ;
		334	.equ OCR0_4 = 4 ;
		335	.equ OCR0_5 = 5 ;
		336	.equ OCR0_6 = 6 ;
		337	.equ OCR0_7 = 7 ;
		338
		339	; TIMSK - Timer/Counter Interrupt Mask Register
		340	.equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register
		341	.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
		342
		343	; TIFR - Timer/Counter Interrupt Flag register
		344	.equ OCF0 = 0 ; Output Compare Flag 0
		345	.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
		346
		347
		348	; *** TIMER_COUNTER_1 ************
		349	; TIMSK - Timer/Counter Interrupt Mask Register
		350	.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
		351	.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		352	.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		353	.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
		354
		355	; TIFR - Timer/Counter Interrupt Flag register
		356	.equ ICF1 = 3 ; Input Capture Flag 1
		357	.equ OCF1B = 5 ; Output Compare Flag 1B
		358	.equ OCF1A = 6 ; Output Compare Flag 1A
		359	.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
		360
		361	; TCCR1A - Timer/Counter1 Control Register A
		362	.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
		363	.equ PWM10 = WGM10 ; For compatibility
		364	.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
		365	.equ PWM11 = WGM11 ; For compatibility
		366	.equ FOC1B = 2 ; Force Output Compare for Channel B
		367	.equ FOC1A = 3 ; Force Output Compare for Channel A
		368	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		369	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		370	.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
		371	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		372
		373	; TCCR1B - Timer/Counter1 Control Register B
		374	.equ CS10 = 0 ; Clock Select1 bit 0
		375	.equ CS11 = 1 ; Clock Select1 bit 1
		376	.equ CS12 = 2 ; Clock Select1 bit 2
		377	.equ WGM12 = 3 ; Pulse Width Modulator Select Bit 2
		378	.equ CTC10 = WGM12 ; For compatibility
		379	.equ WGM13 = 4 ; Pulse Width Modulator Select Bit 3
		380	.equ CTC11 = WGM13 ; For compatibility
		381	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		382	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		383
		384
		385	; *** PORTA **********************
		386	; PORTA - Port A Data Register
		387	.equ PORTA0 = 0 ; Port A Data Register bit 0
		388	.equ PA0 = 0 ; For compatibility
		389	.equ PORTA1 = 1 ; Port A Data Register bit 1
		390	.equ PA1 = 1 ; For compatibility
		391	.equ PORTA2 = 2 ; Port A Data Register bit 2
		392	.equ PA2 = 2 ; For compatibility
		393	.equ PORTA3 = 3 ; Port A Data Register bit 3
		394	.equ PA3 = 3 ; For compatibility
		395	.equ PORTA4 = 4 ; Port A Data Register bit 4
		396	.equ PA4 = 4 ; For compatibility
		397	.equ PORTA5 = 5 ; Port A Data Register bit 5
		398	.equ PA5 = 5 ; For compatibility
		399	.equ PORTA6 = 6 ; Port A Data Register bit 6
		400	.equ PA6 = 6 ; For compatibility
		401	.equ PORTA7 = 7 ; Port A Data Register bit 7
		402	.equ PA7 = 7 ; For compatibility
		403
		404	; DDRA - Port A Data Direction Register
		405	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		406	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		407	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		408	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		409	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		410	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		411	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		412	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		413
		414	; PINA - Port A Input Pins
		415	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		416	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		417	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		418	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		419	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		420	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		421	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		422	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		423
		424
		425	; *** PORTB **********************
		426	; PORTB - Port B Data Register
		427	.equ PORTB0 = 0 ; Port B Data Register bit 0
		428	.equ PB0 = 0 ; For compatibility
		429	.equ PORTB1 = 1 ; Port B Data Register bit 1
		430	.equ PB1 = 1 ; For compatibility
		431	.equ PORTB2 = 2 ; Port B Data Register bit 2
		432	.equ PB2 = 2 ; For compatibility
		433	.equ PORTB3 = 3 ; Port B Data Register bit 3
		434	.equ PB3 = 3 ; For compatibility
		435	.equ PORTB4 = 4 ; Port B Data Register bit 4
		436	.equ PB4 = 4 ; For compatibility
		437	.equ PORTB5 = 5 ; Port B Data Register bit 5
		438	.equ PB5 = 5 ; For compatibility
		439	.equ PORTB6 = 6 ; Port B Data Register bit 6
		440	.equ PB6 = 6 ; For compatibility
		441	.equ PORTB7 = 7 ; Port B Data Register bit 7
		442	.equ PB7 = 7 ; For compatibility
		443
		444	; DDRB - Port B Data Direction Register
		445	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		446	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		447	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		448	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		449	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		450	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		451	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		452	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		453
		454	; PINB - Port B Input Pins
		455	.equ PINB0 = 0 ; Port B Input Pins bit 0
		456	.equ PINB1 = 1 ; Port B Input Pins bit 1
		457	.equ PINB2 = 2 ; Port B Input Pins bit 2
		458	.equ PINB3 = 3 ; Port B Input Pins bit 3
		459	.equ PINB4 = 4 ; Port B Input Pins bit 4
		460	.equ PINB5 = 5 ; Port B Input Pins bit 5
		461	.equ PINB6 = 6 ; Port B Input Pins bit 6
		462	.equ PINB7 = 7 ; Port B Input Pins bit 7
		463
		464
		465	; *** PORTC **********************
		466	; PORTC - Port C Data Register
		467	.equ PORTC0 = 0 ; Port C Data Register bit 0
		468	.equ PC0 = 0 ; For compatibility
		469	.equ PORTC1 = 1 ; Port C Data Register bit 1
		470	.equ PC1 = 1 ; For compatibility
		471	.equ PORTC2 = 2 ; Port C Data Register bit 2
		472	.equ PC2 = 2 ; For compatibility
		473	.equ PORTC3 = 3 ; Port C Data Register bit 3
		474	.equ PC3 = 3 ; For compatibility
		475	.equ PORTC4 = 4 ; Port C Data Register bit 4
		476	.equ PC4 = 4 ; For compatibility
		477	.equ PORTC5 = 5 ; Port C Data Register bit 5
		478	.equ PC5 = 5 ; For compatibility
		479	.equ PORTC6 = 6 ; Port C Data Register bit 6
		480	.equ PC6 = 6 ; For compatibility
		481	.equ PORTC7 = 7 ; Port C Data Register bit 7
		482	.equ PC7 = 7 ; For compatibility
		483
		484	; DDRC - Port C Data Direction Register
		485	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		486	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		487	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		488	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		489	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		490	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		491	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		492	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		493
		494	; PINC - Port C Input Pins
		495	.equ PINC0 = 0 ; Port C Input Pins bit 0
		496	.equ PINC1 = 1 ; Port C Input Pins bit 1
		497	.equ PINC2 = 2 ; Port C Input Pins bit 2
		498	.equ PINC3 = 3 ; Port C Input Pins bit 3
		499	.equ PINC4 = 4 ; Port C Input Pins bit 4
		500	.equ PINC5 = 5 ; Port C Input Pins bit 5
		501	.equ PINC6 = 6 ; Port C Input Pins bit 6
		502	.equ PINC7 = 7 ; Port C Input Pins bit 7
		503
		504
		505	; *** PORTD **********************
		506	; PORTD - Port D Data Register
		507	.equ PORTD0 = 0 ; Port D Data Register bit 0
		508	.equ PD0 = 0 ; For compatibility
		509	.equ PORTD1 = 1 ; Port D Data Register bit 1
		510	.equ PD1 = 1 ; For compatibility
		511	.equ PORTD2 = 2 ; Port D Data Register bit 2
		512	.equ PD2 = 2 ; For compatibility
		513	.equ PORTD3 = 3 ; Port D Data Register bit 3
		514	.equ PD3 = 3 ; For compatibility
		515	.equ PORTD4 = 4 ; Port D Data Register bit 4
		516	.equ PD4 = 4 ; For compatibility
		517	.equ PORTD5 = 5 ; Port D Data Register bit 5
		518	.equ PD5 = 5 ; For compatibility
		519	.equ PORTD6 = 6 ; Port D Data Register bit 6
		520	.equ PD6 = 6 ; For compatibility
		521	.equ PORTD7 = 7 ; Port D Data Register bit 7
		522	.equ PD7 = 7 ; For compatibility
		523
		524	; DDRD - Port D Data Direction Register
		525	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		526	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		527	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		528	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		529	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		530	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		531	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		532	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		533
		534	; PIND - Port D Input Pins
		535	.equ PIND0 = 0 ; Port D Input Pins bit 0
		536	.equ PIND1 = 1 ; Port D Input Pins bit 1
		537	.equ PIND2 = 2 ; Port D Input Pins bit 2
		538	.equ PIND3 = 3 ; Port D Input Pins bit 3
		539	.equ PIND4 = 4 ; Port D Input Pins bit 4
		540	.equ PIND5 = 5 ; Port D Input Pins bit 5
		541	.equ PIND6 = 6 ; Port D Input Pins bit 6
		542	.equ PIND7 = 7 ; Port D Input Pins bit 7
		543
		544
		545	; *** PORTE **********************
		546	; PORTE - Port E Data Register
		547	.equ PORTE0 = 0 ;
		548	.equ PE0 = 0 ; For compatibility
		549	.equ PORTE1 = 1 ;
		550	.equ PE1 = 1 ; For compatibility
		551	.equ PORTE2 = 2 ;
		552	.equ PE2 = 2 ; For compatibility
		553
		554	; DDRE - Port E Data Direction Register
		555	.equ DDE0 = 0 ;
		556	.equ DDE1 = 1 ;
		557	.equ DDE2 = 2 ;
		558
		559	; PINE - Port E Input Pins
		560	.equ PINE0 = 0 ;
		561	.equ PINE1 = 1 ;
		562	.equ PINE2 = 2 ;
		563
		564
		565	; *** EEPROM *********************
		566	; EEDR - EEPROM Data Register
		567	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		568	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		569	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		570	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		571	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		572	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		573	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		574	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		575
		576	; EECR - EEPROM Control Register
		577	.equ EERE = 0 ; EEPROM Read Enable
		578	.equ EEWE = 1 ; EEPROM Write Enable
		579	.equ EEMWE = 2 ; EEPROM Master Write Enable
		580	.equ EEWEE = EEMWE ; For compatibility
		581	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		582
		583
		584
		585	; *** LOCKSBITS ******************************************************
		586	.equ LB1 = 0 ; Lock bit
		587	.equ LB2 = 1 ; Lock bit
		588	.equ BLB01 = 2 ; Boot Lock bit
		589	.equ BLB02 = 3 ; Boot Lock bit
		590	.equ BLB11 = 4 ; Boot lock bit
		591	.equ BLB12 = 5 ; Boot lock bit
		592
		593
		594	; *** FUSES **********************************************************
		595	; LOW fuse bits
		596	.equ CKSEL0 = 0 ; Select Clock Source
		597	.equ CKSEL1 = 1 ; Select Clock Source
		598	.equ CKSEL2 = 2 ; Select Clock Source
		599	.equ CKSEL3 = 3 ; Select Clock Source
		600	.equ SUT0 = 4 ; Select start-up time
		601	.equ SUT1 = 5 ; Select start-up time
		602	.equ BODEN = 6 ; Brown out detector enable
		603	.equ BODLEVEL = 7 ; Brown out detector trigger level
		604
		605	; HIGH fuse bits
		606	.equ BOOTRST = 0 ; Select Reset Vector
		607	.equ BOOTSZ0 = 1 ; Select Boot Size
		608	.equ BOOTSZ1 = 2 ; Select Boot Size
		609	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		610	.equ CKOPT = 4 ; Oscillator Options
		611	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		612	.equ WDTON = 6 ; Watchdog timer always on
		613	.equ S8515C = 7 ; AT90S4414/8515 compabillity mode
		614
		615
		616
		617	; *** CPU REGISTER DEFINITIONS ***************************************
		618	.def XH = r27
		619	.def XL = r26
		620	.def YH = r29
		621	.def YL = r28
		622	.def ZH = r31
		623	.def ZL = r30
		624
		625
		626
		627	; *** DATA MEMORY DECLARATIONS ***************************************
		628	.equ FLASHEND = 0x0fff ; Note: Word address
		629	.equ IOEND = 0x003f
		630	.equ SRAM_START = 0x0060
		631	.equ SRAM_SIZE = 512
		632	.equ RAMEND = 0x025f
		633	.equ XRAMEND = 0xffff
		634	.equ E2END = 0x01ff
		635	.equ EEPROMEND = 0x01ff
		636	.equ EEADRBITS = 9
		637	#pragma AVRPART MEMORY PROG_FLASH 8192
		638	#pragma AVRPART MEMORY EEPROM 512
		639	#pragma AVRPART MEMORY INT_SRAM SIZE 512
		640	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
		641
		642
		643
		644	; *** BOOTLOADER DECLARATIONS ****************************************
		645	.equ NRWW_START_ADDR = 0xc00
		646	.equ NRWW_STOP_ADDR = 0xfff
		647	.equ RWW_START_ADDR = 0x0
		648	.equ RWW_STOP_ADDR = 0xbff
		649	.equ PAGESIZE = 32
		650	.equ FIRSTBOOTSTART = 0xf80
		651	.equ SECONDBOOTSTART = 0xf00
		652	.equ THIRDBOOTSTART = 0xe00
		653	.equ FOURTHBOOTSTART = 0xc00
		654	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		655	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		656
		657
		658
		659	; *** INTERRUPT VECTORS **********************************************
		660	.equ INT0addr = 0x0001 ; External Interrupt Request 0
		661	.equ INT1addr = 0x0002 ; External Interrupt Request 1
		662	.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
		663	.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
		664	.equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB
		665	.equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow
		666	.equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow
		667	.equ SPIaddr = 0x0008 ; Serial Transfer Complete
		668	.equ URXCaddr = 0x0009 ; UART, Rx Complete
		669	.equ UDREaddr = 0x000a ; UART Data Register Empty
		670	.equ UTXCaddr = 0x000b ; UART, Tx Complete
		671	.equ ACIaddr = 0x000c ; Analog Comparator
		672	.equ INT2addr = 0x000d ; External Interrupt Request 2
		673	.equ OC0addr = 0x000e ; Timer 0 Compare Match
		674	.equ ERDYaddr = 0x000f ; EEPROM Ready
		675	.equ SPMRaddr = 0x0010 ; Store Program Memory Ready
		676
		677	.equ INT_VECTORS_SIZE = 17 ; size in words
		678
		679	#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
		680
		681	#endif /* _M8515DEF_INC_ */
		682
		683	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/m8515def.inc – Rev 6400