WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m32def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:31 *** Source: ATmega32.xml **********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m32def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega32
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega32
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M32DEF_INC_
		41	#define _M32DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega32
		48	#pragma AVRPART ADMIN PART_NAME ATmega32
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x95
		51	.equ SIGNATURE_002 = 0x02
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ SREG = 0x3f
		61	.equ SPH = 0x3e
		62	.equ SPL = 0x3d
		63	.equ OCR0 = 0x3c
		64	.equ GICR = 0x3b
		65	.equ GIFR = 0x3a
		66	.equ TIMSK = 0x39
		67	.equ TIFR = 0x38
		68	.equ SPMCR = 0x37
		69	.equ TWCR = 0x36
		70	.equ MCUCR = 0x35
		71	.equ MCUCSR = 0x34
		72	.equ TCCR0 = 0x33
		73	.equ TCNT0 = 0x32
		74	.equ OSCCAL = 0x31
		75	.equ OCDR = 0x31
		76	.equ SFIOR = 0x30
		77	.equ TCCR1A = 0x2f
		78	.equ TCCR1B = 0x2e
		79	.equ TCNT1H = 0x2d
		80	.equ TCNT1L = 0x2c
		81	.equ OCR1AH = 0x2b
		82	.equ OCR1AL = 0x2a
		83	.equ OCR1BH = 0x29
		84	.equ OCR1BL = 0x28
		85	.equ ICR1H = 0x27
		86	.equ ICR1L = 0x26
		87	.equ TCCR2 = 0x25
		88	.equ TCNT2 = 0x24
		89	.equ OCR2 = 0x23
		90	.equ ASSR = 0x22
		91	.equ WDTCR = 0x21
		92	.equ UBRRH = 0x20
		93	.equ UCSRC = 0x20
		94	.equ EEARH = 0x1f
		95	.equ EEARL = 0x1e
		96	.equ EEDR = 0x1d
		97	.equ EECR = 0x1c
		98	.equ PORTA = 0x1b
		99	.equ DDRA = 0x1a
		100	.equ PINA = 0x19
		101	.equ PORTB = 0x18
		102	.equ DDRB = 0x17
		103	.equ PINB = 0x16
		104	.equ PORTC = 0x15
		105	.equ DDRC = 0x14
		106	.equ PINC = 0x13
		107	.equ PORTD = 0x12
		108	.equ DDRD = 0x11
		109	.equ PIND = 0x10
		110	.equ SPDR = 0x0f
		111	.equ SPSR = 0x0e
		112	.equ SPCR = 0x0d
		113	.equ UDR = 0x0c
		114	.equ UCSRA = 0x0b
		115	.equ UCSRB = 0x0a
		116	.equ UBRRL = 0x09
		117	.equ ACSR = 0x08
		118	.equ ADMUX = 0x07
		119	.equ ADCSRA = 0x06
		120	.equ ADCH = 0x05
		121	.equ ADCL = 0x04
		122	.equ TWDR = 0x03
		123	.equ TWAR = 0x02
		124	.equ TWSR = 0x01
		125	.equ TWBR = 0x00
		126
		127
		128	; *** BIT DEFINITIONS ************************************************
		129
		130	; *** EEPROM *********************
		131	; EEDR - EEPROM Data Register
		132	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		133	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		134	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		135	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		136	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		137	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		138	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		139	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		140
		141	; EECR - EEPROM Control Register
		142	.equ EERE = 0 ; EEPROM Read Enable
		143	.equ EEWE = 1 ; EEPROM Write Enable
		144	.equ EEMWE = 2 ; EEPROM Master Write Enable
		145	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		146
		147
		148	; *** WATCHDOG *******************
		149	; WDTCR - Watchdog Timer Control Register
		150	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		151	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		152	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		153	.equ WDE = 3 ; Watch Dog Enable
		154	.equ WDTOE = 4 ; RW
		155	.equ WDDE = WDTOE ; For compatibility
		156
		157
		158	; *** EXTERNAL_INTERRUPT *********
		159	; GICR - General Interrupt Control Register
		160	.equ GIMSK = GICR ; For compatibility
		161	.equ IVCE = 0 ; Interrupt Vector Change Enable
		162	.equ IVSEL = 1 ; Interrupt Vector Select
		163	.equ INT2 = 5 ; External Interrupt Request 2 Enable
		164	.equ INT0 = 6 ; External Interrupt Request 0 Enable
		165	.equ INT1 = 7 ; External Interrupt Request 1 Enable
		166
		167	; GIFR - General Interrupt Flag Register
		168	.equ INTF2 = 5 ; External Interrupt Flag 2
		169	.equ INTF0 = 6 ; External Interrupt Flag 0
		170	.equ INTF1 = 7 ; External Interrupt Flag 1
		171
		172	; MCUCR - General Interrupt Control Register
		173	.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
		174	.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
		175	.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
		176	.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
		177
		178	; MCUCSR - MCU Control And Status Register
		179	.equ ISC2 = 6 ; Interrupt Sense Control 2
		180
		181
		182	; *** TIMER_COUNTER_0 ************
		183	; TCCR0 - Timer/Counter Control Register
		184	.equ CS00 = 0 ; Clock Select 1
		185	.equ CS01 = 1 ; Clock Select 1
		186	.equ CS02 = 2 ; Clock Select 2
		187	.equ WGM01 = 3 ; Waveform Generation Mode 1
		188	.equ CTC0 = WGM01 ; For compatibility
		189	.equ COM00 = 4 ; Compare match Output Mode 0
		190	.equ COM01 = 5 ; Compare Match Output Mode 1
		191	.equ WGM00 = 6 ; Waveform Generation Mode
		192	.equ PWM0 = WGM00 ; For compatibility
		193	.equ FOC0 = 7 ; Force Output Compare
		194
		195	; TCNT0 - Timer/Counter Register
		196	.equ TCNT0_0 = 0 ;
		197	.equ TCNT0_1 = 1 ;
		198	.equ TCNT0_2 = 2 ;
		199	.equ TCNT0_3 = 3 ;
		200	.equ TCNT0_4 = 4 ;
		201	.equ TCNT0_5 = 5 ;
		202	.equ TCNT0_6 = 6 ;
		203	.equ TCNT0_7 = 7 ;
		204
		205	; OCR0 - Output Compare Register
		206	.equ OCR0_0 = 0 ;
		207	.equ OCR0_1 = 1 ;
		208	.equ OCR0_2 = 2 ;
		209	.equ OCR0_3 = 3 ;
		210	.equ OCR0_4 = 4 ;
		211	.equ OCR0_5 = 5 ;
		212	.equ OCR0_6 = 6 ;
		213	.equ OCR0_7 = 7 ;
		214
		215	; TIMSK - Timer/Counter Interrupt Mask Register
		216	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		217	.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
		218
		219	; TIFR - Timer/Counter Interrupt Flag register
		220	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		221	.equ OCF0 = 1 ; Output Compare Flag 0
		222
		223
		224	; *** TIMER_COUNTER_2 ************
		225	; TIMSK - Timer/Counter Interrupt Mask register
		226	.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
		227	.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
		228
		229	; TIFR - Timer/Counter Interrupt Flag Register
		230	.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
		231	.equ OCF2 = 7 ; Output Compare Flag 2
		232
		233	; TCCR2 - Timer/Counter2 Control Register
		234	.equ CS20 = 0 ; Clock Select bit 0
		235	.equ CS21 = 1 ; Clock Select bit 1
		236	.equ CS22 = 2 ; Clock Select bit 2
		237	.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match
		238	.equ COM20 = 4 ; Compare Output Mode bit 0
		239	.equ COM21 = 5 ; Compare Output Mode bit 1
		240	.equ PWM2 = 6 ; Pulse Width Modulator Enable
		241	.equ FOC2 = 7 ; Force Output Compare
		242
		243	; TCNT2 - Timer/Counter2
		244	.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
		245	.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
		246	.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
		247	.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
		248	.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
		249	.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
		250	.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
		251	.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
		252
		253	; OCR2 - Timer/Counter2 Output Compare Register
		254	.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
		255	.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
		256	.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
		257	.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
		258	.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
		259	.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
		260	.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
		261	.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
		262
		263	; ASSR - Asynchronous Status Register
		264	.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy
		265	.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
		266	.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
		267	.equ AS2 = 3 ; Asynchronous Timer/counter2
		268
		269
		270	; *** TIMER_COUNTER_1 ************
		271	; TIMSK - Timer/Counter Interrupt Mask Register
		272	.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
		273	.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		274	.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		275	.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		276
		277	; TIFR - Timer/Counter Interrupt Flag register
		278	.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
		279	.equ OCF1B = 3 ; Output Compare Flag 1B
		280	.equ OCF1A = 4 ; Output Compare Flag 1A
		281	.equ ICF1 = 5 ; Input Capture Flag 1
		282
		283	; TCCR1A - Timer/Counter1 Control Register A
		284	.equ WGM10 = 0 ; Waveform Generation Mode
		285	.equ PWM10 = WGM10 ; For compatibility
		286	.equ WGM11 = 1 ; Waveform Generation Mode
		287	.equ PWM11 = WGM11 ; For compatibility
		288	.equ FOC1B = 2 ; Force Output Compare 1B
		289	.equ FOC1A = 3 ; Force Output Compare 1A
		290	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		291	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		292	.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
		293	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		294
		295	; TCCR1B - Timer/Counter1 Control Register B
		296	.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
		297	.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
		298	.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
		299	.equ WGM12 = 3 ; Waveform Generation Mode
		300	.equ CTC10 = WGM12 ; For compatibility
		301	.equ CTC1 = WGM12 ; For compatibility
		302	.equ WGM13 = 4 ; Waveform Generation Mode
		303	.equ CTC11 = WGM13 ; For compatibility
		304	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		305	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		306
		307
		308	; *** SPI ************************
		309	; SPDR - SPI Data Register
		310	.equ SPDR0 = 0 ; SPI Data Register bit 0
		311	.equ SPDR1 = 1 ; SPI Data Register bit 1
		312	.equ SPDR2 = 2 ; SPI Data Register bit 2
		313	.equ SPDR3 = 3 ; SPI Data Register bit 3
		314	.equ SPDR4 = 4 ; SPI Data Register bit 4
		315	.equ SPDR5 = 5 ; SPI Data Register bit 5
		316	.equ SPDR6 = 6 ; SPI Data Register bit 6
		317	.equ SPDR7 = 7 ; SPI Data Register bit 7
		318
		319	; SPSR - SPI Status Register
		320	.equ SPI2X = 0 ; Double SPI Speed Bit
		321	.equ WCOL = 6 ; Write Collision Flag
		322	.equ SPIF = 7 ; SPI Interrupt Flag
		323
		324	; SPCR - SPI Control Register
		325	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		326	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		327	.equ CPHA = 2 ; Clock Phase
		328	.equ CPOL = 3 ; Clock polarity
		329	.equ MSTR = 4 ; Master/Slave Select
		330	.equ DORD = 5 ; Data Order
		331	.equ SPE = 6 ; SPI Enable
		332	.equ SPIE = 7 ; SPI Interrupt Enable
		333
		334
		335	; *** USART **********************
		336	; UDR - USART I/O Data Register
		337	.equ UDR0 = 0 ; USART I/O Data Register bit 0
		338	.equ UDR1 = 1 ; USART I/O Data Register bit 1
		339	.equ UDR2 = 2 ; USART I/O Data Register bit 2
		340	.equ UDR3 = 3 ; USART I/O Data Register bit 3
		341	.equ UDR4 = 4 ; USART I/O Data Register bit 4
		342	.equ UDR5 = 5 ; USART I/O Data Register bit 5
		343	.equ UDR6 = 6 ; USART I/O Data Register bit 6
		344	.equ UDR7 = 7 ; USART I/O Data Register bit 7
		345
		346	; UCSRA - USART Control and Status Register A
		347	.equ USR = UCSRA ; For compatibility
		348	.equ MPCM = 0 ; Multi-processor Communication Mode
		349	.equ U2X = 1 ; Double the USART transmission speed
		350	.equ UPE = 2 ; Parity Error
		351	.equ PE = UPE ; For compatibility
		352	.equ DOR = 3 ; Data overRun
		353	.equ FE = 4 ; Framing Error
		354	.equ UDRE = 5 ; USART Data Register Empty
		355	.equ TXC = 6 ; USART Transmitt Complete
		356	.equ RXC = 7 ; USART Receive Complete
		357
		358	; UCSRB - USART Control and Status Register B
		359	.equ UCR = UCSRB ; For compatibility
		360	.equ TXB8 = 0 ; Transmit Data Bit 8
		361	.equ RXB8 = 1 ; Receive Data Bit 8
		362	.equ UCSZ2 = 2 ; Character Size
		363	.equ CHR9 = UCSZ2 ; For compatibility
		364	.equ TXEN = 3 ; Transmitter Enable
		365	.equ RXEN = 4 ; Receiver Enable
		366	.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
		367	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		368	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		369
		370	; UCSRC - USART Control and Status Register C
		371	.equ UCPOL = 0 ; Clock Polarity
		372	.equ UCSZ0 = 1 ; Character Size
		373	.equ UCSZ1 = 2 ; Character Size
		374	.equ USBS = 3 ; Stop Bit Select
		375	.equ UPM0 = 4 ; Parity Mode Bit 0
		376	.equ UPM1 = 5 ; Parity Mode Bit 1
		377	.equ UMSEL = 6 ; USART Mode Select
		378	.equ URSEL = 7 ; Register Select
		379
		380	.equ UBRRHI = UBRRH ; For compatibility
		381
		382	; *** TWI ************************
		383	; TWBR - TWI Bit Rate register
		384	.equ TWBR0 = 0 ;
		385	.equ TWBR1 = 1 ;
		386	.equ TWBR2 = 2 ;
		387	.equ TWBR3 = 3 ;
		388	.equ TWBR4 = 4 ;
		389	.equ TWBR5 = 5 ;
		390	.equ TWBR6 = 6 ;
		391	.equ TWBR7 = 7 ;
		392
		393	; TWCR - TWI Control Register
		394	.equ TWIE = 0 ; TWI Interrupt Enable
		395	.equ TWEN = 2 ; TWI Enable Bit
		396	.equ TWWC = 3 ; TWI Write Collition Flag
		397	.equ TWSTO = 4 ; TWI Stop Condition Bit
		398	.equ TWSTA = 5 ; TWI Start Condition Bit
		399	.equ TWEA = 6 ; TWI Enable Acknowledge Bit
		400	.equ TWINT = 7 ; TWI Interrupt Flag
		401
		402	; TWSR - TWI Status Register
		403	.equ TWS3 = 3 ; TWI Status
		404	.equ TWS4 = 4 ; TWI Status
		405	.equ TWS5 = 5 ; TWI Status
		406	.equ TWS6 = 6 ; TWI Status
		407	.equ TWS7 = 7 ; TWI Status
		408
		409	; TWDR - TWI Data register
		410	.equ TWD0 = 0 ; TWI Data Register Bit 0
		411	.equ TWD1 = 1 ; TWI Data Register Bit 1
		412	.equ TWD2 = 2 ; TWI Data Register Bit 2
		413	.equ TWD3 = 3 ; TWI Data Register Bit 3
		414	.equ TWD4 = 4 ; TWI Data Register Bit 4
		415	.equ TWD5 = 5 ; TWI Data Register Bit 5
		416	.equ TWD6 = 6 ; TWI Data Register Bit 6
		417	.equ TWD7 = 7 ; TWI Data Register Bit 7
		418
		419	; TWAR - TWI (Slave) Address register
		420	.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
		421	.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
		422	.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
		423	.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
		424	.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
		425	.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
		426	.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
		427	.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
		428
		429
		430	; *** ANALOG_COMPARATOR **********
		431	; SFIOR - Special Function IO Register
		432	.equ ACME = 3 ; Analog Comparator Multiplexer Enable
		433
		434	; ACSR - Analog Comparator Control And Status Register
		435	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		436	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		437	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		438	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		439	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		440	.equ ACO = 5 ; Analog Compare Output
		441	.equ ACBG = 6 ; Analog Comparator Bandgap Select
		442	.equ ACD = 7 ; Analog Comparator Disable
		443
		444
		445	; *** AD_CONVERTER ***************
		446	; ADMUX - The ADC multiplexer Selection Register
		447	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		448	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		449	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		450	.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
		451	.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
		452	.equ ADLAR = 5 ; Left Adjust Result
		453	.equ REFS0 = 6 ; Reference Selection Bit 0
		454	.equ REFS1 = 7 ; Reference Selection Bit 1
		455
		456	; ADCSRA - The ADC Control and Status register
		457	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		458	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		459	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		460	.equ ADIE = 3 ; ADC Interrupt Enable
		461	.equ ADIF = 4 ; ADC Interrupt Flag
		462	.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
		463	.equ ADFR = ADATE ; For compatibility
		464	.equ ADSC = 6 ; ADC Start Conversion
		465	.equ ADEN = 7 ; ADC Enable
		466
		467	; ADCH - ADC Data Register High Byte
		468	.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
		469	.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
		470	.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
		471	.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
		472	.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
		473	.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
		474	.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
		475	.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
		476
		477	; ADCL - ADC Data Register Low Byte
		478	.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
		479	.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
		480	.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
		481	.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
		482	.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
		483	.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
		484	.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
		485	.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
		486
		487
		488	; *** PORTA **********************
		489	; PORTA - Port A Data Register
		490	.equ PORTA0 = 0 ; Port A Data Register bit 0
		491	.equ PA0 = 0 ; For compatibility
		492	.equ PORTA1 = 1 ; Port A Data Register bit 1
		493	.equ PA1 = 1 ; For compatibility
		494	.equ PORTA2 = 2 ; Port A Data Register bit 2
		495	.equ PA2 = 2 ; For compatibility
		496	.equ PORTA3 = 3 ; Port A Data Register bit 3
		497	.equ PA3 = 3 ; For compatibility
		498	.equ PORTA4 = 4 ; Port A Data Register bit 4
		499	.equ PA4 = 4 ; For compatibility
		500	.equ PORTA5 = 5 ; Port A Data Register bit 5
		501	.equ PA5 = 5 ; For compatibility
		502	.equ PORTA6 = 6 ; Port A Data Register bit 6
		503	.equ PA6 = 6 ; For compatibility
		504	.equ PORTA7 = 7 ; Port A Data Register bit 7
		505	.equ PA7 = 7 ; For compatibility
		506
		507	; DDRA - Port A Data Direction Register
		508	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		509	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		510	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		511	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		512	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		513	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		514	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		515	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		516
		517	; PINA - Port A Input Pins
		518	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		519	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		520	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		521	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		522	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		523	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		524	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		525	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		526
		527
		528	; *** PORTB **********************
		529	; PORTB - Port B Data Register
		530	.equ PORTB0 = 0 ; Port B Data Register bit 0
		531	.equ PB0 = 0 ; For compatibility
		532	.equ PORTB1 = 1 ; Port B Data Register bit 1
		533	.equ PB1 = 1 ; For compatibility
		534	.equ PORTB2 = 2 ; Port B Data Register bit 2
		535	.equ PB2 = 2 ; For compatibility
		536	.equ PORTB3 = 3 ; Port B Data Register bit 3
		537	.equ PB3 = 3 ; For compatibility
		538	.equ PORTB4 = 4 ; Port B Data Register bit 4
		539	.equ PB4 = 4 ; For compatibility
		540	.equ PORTB5 = 5 ; Port B Data Register bit 5
		541	.equ PB5 = 5 ; For compatibility
		542	.equ PORTB6 = 6 ; Port B Data Register bit 6
		543	.equ PB6 = 6 ; For compatibility
		544	.equ PORTB7 = 7 ; Port B Data Register bit 7
		545	.equ PB7 = 7 ; For compatibility
		546
		547	; DDRB - Port B Data Direction Register
		548	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		549	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		550	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		551	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		552	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		553	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		554	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		555	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		556
		557	; PINB - Port B Input Pins
		558	.equ PINB0 = 0 ; Port B Input Pins bit 0
		559	.equ PINB1 = 1 ; Port B Input Pins bit 1
		560	.equ PINB2 = 2 ; Port B Input Pins bit 2
		561	.equ PINB3 = 3 ; Port B Input Pins bit 3
		562	.equ PINB4 = 4 ; Port B Input Pins bit 4
		563	.equ PINB5 = 5 ; Port B Input Pins bit 5
		564	.equ PINB6 = 6 ; Port B Input Pins bit 6
		565	.equ PINB7 = 7 ; Port B Input Pins bit 7
		566
		567
		568	; *** PORTC **********************
		569	; PORTC - Port C Data Register
		570	.equ PORTC0 = 0 ; Port C Data Register bit 0
		571	.equ PC0 = 0 ; For compatibility
		572	.equ PORTC1 = 1 ; Port C Data Register bit 1
		573	.equ PC1 = 1 ; For compatibility
		574	.equ PORTC2 = 2 ; Port C Data Register bit 2
		575	.equ PC2 = 2 ; For compatibility
		576	.equ PORTC3 = 3 ; Port C Data Register bit 3
		577	.equ PC3 = 3 ; For compatibility
		578	.equ PORTC4 = 4 ; Port C Data Register bit 4
		579	.equ PC4 = 4 ; For compatibility
		580	.equ PORTC5 = 5 ; Port C Data Register bit 5
		581	.equ PC5 = 5 ; For compatibility
		582	.equ PORTC6 = 6 ; Port C Data Register bit 6
		583	.equ PC6 = 6 ; For compatibility
		584	.equ PORTC7 = 7 ; Port C Data Register bit 7
		585	.equ PC7 = 7 ; For compatibility
		586
		587	; DDRC - Port C Data Direction Register
		588	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		589	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		590	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		591	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		592	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		593	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		594	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		595	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		596
		597	; PINC - Port C Input Pins
		598	.equ PINC0 = 0 ; Port C Input Pins bit 0
		599	.equ PINC1 = 1 ; Port C Input Pins bit 1
		600	.equ PINC2 = 2 ; Port C Input Pins bit 2
		601	.equ PINC3 = 3 ; Port C Input Pins bit 3
		602	.equ PINC4 = 4 ; Port C Input Pins bit 4
		603	.equ PINC5 = 5 ; Port C Input Pins bit 5
		604	.equ PINC6 = 6 ; Port C Input Pins bit 6
		605	.equ PINC7 = 7 ; Port C Input Pins bit 7
		606
		607
		608	; *** PORTD **********************
		609	; PORTD - Port D Data Register
		610	.equ PORTD0 = 0 ; Port D Data Register bit 0
		611	.equ PD0 = 0 ; For compatibility
		612	.equ PORTD1 = 1 ; Port D Data Register bit 1
		613	.equ PD1 = 1 ; For compatibility
		614	.equ PORTD2 = 2 ; Port D Data Register bit 2
		615	.equ PD2 = 2 ; For compatibility
		616	.equ PORTD3 = 3 ; Port D Data Register bit 3
		617	.equ PD3 = 3 ; For compatibility
		618	.equ PORTD4 = 4 ; Port D Data Register bit 4
		619	.equ PD4 = 4 ; For compatibility
		620	.equ PORTD5 = 5 ; Port D Data Register bit 5
		621	.equ PD5 = 5 ; For compatibility
		622	.equ PORTD6 = 6 ; Port D Data Register bit 6
		623	.equ PD6 = 6 ; For compatibility
		624	.equ PORTD7 = 7 ; Port D Data Register bit 7
		625	.equ PD7 = 7 ; For compatibility
		626
		627	; DDRD - Port D Data Direction Register
		628	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		629	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		630	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		631	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		632	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		633	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		634	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		635	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		636
		637	; PIND - Port D Input Pins
		638	.equ PIND0 = 0 ; Port D Input Pins bit 0
		639	.equ PIND1 = 1 ; Port D Input Pins bit 1
		640	.equ PIND2 = 2 ; Port D Input Pins bit 2
		641	.equ PIND3 = 3 ; Port D Input Pins bit 3
		642	.equ PIND4 = 4 ; Port D Input Pins bit 4
		643	.equ PIND5 = 5 ; Port D Input Pins bit 5
		644	.equ PIND6 = 6 ; Port D Input Pins bit 6
		645	.equ PIND7 = 7 ; Port D Input Pins bit 7
		646
		647
		648	; *** CPU ************************
		649	; SREG - Status Register
		650	.equ SREG_C = 0 ; Carry Flag
		651	.equ SREG_Z = 1 ; Zero Flag
		652	.equ SREG_N = 2 ; Negative Flag
		653	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		654	.equ SREG_S = 4 ; Sign Bit
		655	.equ SREG_H = 5 ; Half Carry Flag
		656	.equ SREG_T = 6 ; Bit Copy Storage
		657	.equ SREG_I = 7 ; Global Interrupt Enable
		658
		659	; MCUCR - MCU Control Register
		660	;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
		661	;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
		662	;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
		663	;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
		664	.equ SM0 = 4 ; Sleep Mode Select
		665	.equ SM1 = 5 ; Sleep Mode Select
		666	.equ SM2 = 6 ; Sleep Mode Select
		667	.equ SE = 7 ; Sleep Enable
		668
		669	; MCUCSR - MCU Control And Status Register
		670	.equ MCUSR = MCUCSR ; For compatibility
		671	.equ PORF = 0 ; Power-on reset flag
		672	.equ EXTRF = 1 ; External Reset Flag
		673	.equ BORF = 2 ; Brown-out Reset Flag
		674	.equ WDRF = 3 ; Watchdog Reset Flag
		675	.equ JTRF = 4 ; JTAG Reset Flag
		676	.equ JTD = 7 ; JTAG Interface Disable
		677
		678	; OSCCAL - Oscillator Calibration Value
		679	.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
		680	.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
		681	.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
		682	.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
		683	.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
		684	.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
		685	.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
		686	.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
		687
		688	; SFIOR - Special Function IO Register
		689	.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1&0
		690	.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
		691	.equ PUD = 2 ; Pull-up Disable
		692	.equ ADTS0 = 5 ; ADC Auto Trigger Source 0
		693	.equ ADTS1 = 6 ; ADC Auto Trigger Source 1
		694	.equ ADTS2 = 7 ; ADC Auto Trigger Source 2
		695
		696
		697	; *** BOOT_LOAD ******************
		698	; SPMCR - Store Program Memory Control Register
		699	.equ SPMEN = 0 ; Store Program Memory Enable
		700	.equ PGERS = 1 ; Page Erase
		701	.equ PGWRT = 2 ; Page Write
		702	.equ BLBSET = 3 ; Boot Lock Bit Set
		703	.equ RWWSRE = 4 ; Read While Write secion read enable
		704	.equ ASRE = RWWSRE ; For compatibility
		705	.equ RWWSB = 6 ; Read While Write Section Busy
		706	.equ ASB = RWWSB ; For compatibility
		707	.equ SPMIE = 7 ; SPM Interrupt Enable
		708
		709
		710
		711	; *** LOCKSBITS ******************************************************
		712	.equ LB1 = 0 ; Lock bit
		713	.equ LB2 = 1 ; Lock bit
		714	.equ BLB01 = 2 ; Boot Lock bit
		715	.equ BLB02 = 3 ; Boot Lock bit
		716	.equ BLB11 = 4 ; Boot lock bit
		717	.equ BLB12 = 5 ; Boot lock bit
		718
		719
		720	; *** FUSES **********************************************************
		721	; LOW fuse bits
		722	.equ CKSEL0 = 0 ; Select Clock Source
		723	.equ CKSEL1 = 1 ; Select Clock Source
		724	.equ CKSEL2 = 2 ; Select Clock Source
		725	.equ CKSEL3 = 3 ; Select Clock Source
		726	.equ BODEN = 6 ; Brown out detector enable
		727	.equ BODLEVEL = 7 ; Brown out detector trigger level
		728
		729	; HIGH fuse bits
		730	.equ BOOTRST = 0 ; Select Reset Vector
		731	.equ BOOTSZ0 = 1 ; Select Boot Size
		732	.equ BOOTSZ1 = 2 ; Select Boot Size
		733	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		734	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		735	.equ JTAGEN = 6 ; Enable JTAG
		736	.equ OCDEN = 7 ; Enable OCD
		737
		738
		739
		740	; *** CPU REGISTER DEFINITIONS ***************************************
		741	.def XH = r27
		742	.def XL = r26
		743	.def YH = r29
		744	.def YL = r28
		745	.def ZH = r31
		746	.def ZL = r30
		747
		748
		749
		750	; *** DATA MEMORY DECLARATIONS ***************************************
		751	.equ FLASHEND = 0x3fff ; Note: Word address
		752	.equ IOEND = 0x003f
		753	.equ SRAM_START = 0x0060
		754	.equ SRAM_SIZE = 2048
		755	.equ RAMEND = 0x085f
		756	.equ XRAMEND = 0x0000
		757	.equ E2END = 0x03ff
		758	.equ EEPROMEND = 0x03ff
		759	.equ EEADRBITS = 10
		760	#pragma AVRPART MEMORY PROG_FLASH 32768
		761	#pragma AVRPART MEMORY EEPROM 1024
		762	#pragma AVRPART MEMORY INT_SRAM SIZE 2048
		763	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
		764
		765
		766
		767	; *** BOOTLOADER DECLARATIONS ****************************************
		768	.equ NRWW_START_ADDR = 0x3800
		769	.equ NRWW_STOP_ADDR = 0x3fff
		770	.equ RWW_START_ADDR = 0x0
		771	.equ RWW_STOP_ADDR = 0x37ff
		772	.equ PAGESIZE = 64
		773	.equ FIRSTBOOTSTART = 0x3f00
		774	.equ SECONDBOOTSTART = 0x3e00
		775	.equ THIRDBOOTSTART = 0x3c00
		776	.equ FOURTHBOOTSTART = 0x3800
		777	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		778	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		779
		780
		781
		782	; *** INTERRUPT VECTORS **********************************************
		783	.equ INT0addr = 0x0002 ; External Interrupt Request 0
		784	.equ INT1addr = 0x0004 ; External Interrupt Request 1
		785	.equ INT2addr = 0x0006 ; External Interrupt Request 2
		786	.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match
		787	.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow
		788	.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event
		789	.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A
		790	.equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B
		791	.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow
		792	.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match
		793	.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow
		794	.equ SPIaddr = 0x0018 ; Serial Transfer Complete
		795	.equ URXCaddr = 0x001a ; USART, Rx Complete
		796	.equ UDREaddr = 0x001c ; USART Data Register Empty
		797	.equ UTXCaddr = 0x001e ; USART, Tx Complete
		798	.equ ADCCaddr = 0x0020 ; ADC Conversion Complete
		799	.equ ERDYaddr = 0x0022 ; EEPROM Ready
		800	.equ ACIaddr = 0x0024 ; Analog Comparator
		801	.equ TWIaddr = 0x0026 ; 2-wire Serial Interface
		802	.equ SPMRaddr = 0x0028 ; Store Program Memory Ready
		803
		804	.equ INT_VECTORS_SIZE = 42 ; size in words
		805
		806	#endif /* _M32DEF_INC_ */
		807
		808	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/m32def.inc – Rev 6400