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6400 | punk_joker | 1 | ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
2 | ;***** Created: 2005-01-11 10:30 ******* Source: ATmega163.xml *********** |
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3 | ;************************************************************************* |
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4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
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5 | ;* |
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6 | ;* Number : AVR000 |
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7 | ;* File Name : "m163def.inc" |
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8 | ;* Title : Register/Bit Definitions for the ATmega163 |
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9 | ;* Date : 2005-01-11 |
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10 | ;* Version : 2.14 |
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11 | ;* Support E-mail : avr@atmel.com |
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12 | ;* Target MCU : ATmega163 |
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13 | ;* |
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14 | ;* DESCRIPTION |
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15 | ;* When including this file in the assembly program file, all I/O register |
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16 | ;* names and I/O register bit names appearing in the data book can be used. |
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17 | ;* In addition, the six registers forming the three data pointers X, Y and |
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18 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
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19 | ;* SRAM is also defined |
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20 | ;* |
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21 | ;* The Register names are represented by their hexadecimal address. |
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22 | ;* |
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23 | ;* The Register Bit names are represented by their bit number (0-7). |
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24 | ;* |
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25 | ;* Please observe the difference in using the bit names with instructions |
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26 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
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27 | ;* (skip if bit in register set/cleared). The following example illustrates |
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28 | ;* this: |
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29 | ;* |
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30 | ;* in r16,PORTB ;read PORTB latch |
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31 | ;* sbr r16,(1< |
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32 | ;* out PORTB,r16 ;output to PORTB |
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33 | ;* |
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34 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register |
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35 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
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36 | ;* rjmp TOV0_is_set ;jump if set |
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37 | ;* ... ;otherwise do something else |
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38 | ;************************************************************************* |
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39 | |||
40 | #ifndef _M163DEF_INC_ |
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41 | #define _M163DEF_INC_ |
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42 | |||
43 | |||
44 | #pragma partinc 0 |
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45 | |||
46 | ; ***** SPECIFY DEVICE *************************************************** |
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47 | .device ATmega163 |
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48 | #pragma AVRPART ADMIN PART_NAME ATmega163 |
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49 | .equ SIGNATURE_000 = 0x1e |
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50 | .equ SIGNATURE_001 = 0x94 |
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51 | .equ SIGNATURE_002 = 0x02 |
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52 | |||
53 | #pragma AVRPART CORE CORE_VERSION V2E |
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54 | |||
55 | |||
56 | ; ***** I/O REGISTER DEFINITIONS ***************************************** |
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57 | ; NOTE: |
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58 | ; Definitions marked "MEMORY MAPPED"are extended I/O ports |
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59 | ; and cannot be used with IN/OUT instructions |
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60 | .equ SREG = 0x3f |
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61 | .equ SPH = 0x3e |
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62 | .equ SPL = 0x3d |
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63 | .equ GIMSK = 0x3b |
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64 | .equ GIFR = 0x3a |
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65 | .equ TIMSK = 0x39 |
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66 | .equ TIFR = 0x38 |
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67 | .equ SPMCR = 0x37 |
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68 | .equ TWCR = 0x36 |
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69 | .equ MCUCR = 0x35 |
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70 | .equ MCUSR = 0x34 |
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71 | .equ TCCR0 = 0x33 |
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72 | .equ TCNT0 = 0x32 |
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73 | .equ OSCCAL = 0x31 |
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74 | .equ SFIOR = 0x30 |
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75 | .equ TCCR1A = 0x2f |
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76 | .equ TCCR1B = 0x2e |
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77 | .equ TCNT1H = 0x2d |
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78 | .equ TCNT1L = 0x2c |
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79 | .equ OCR1AH = 0x2b |
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80 | .equ OCR1AL = 0x2a |
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81 | .equ OCR1BH = 0x29 |
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82 | .equ OCR1BL = 0x28 |
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83 | .equ ICR1H = 0x27 |
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84 | .equ ICR1L = 0x26 |
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85 | .equ TCCR2 = 0x25 |
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86 | .equ TCNT2 = 0x24 |
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87 | .equ OCR2 = 0x23 |
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88 | .equ ASSR = 0x22 |
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89 | .equ WDTCR = 0x21 |
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90 | .equ UBRRHI = 0x20 |
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91 | .equ EEARH = 0x1f |
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92 | .equ EEARL = 0x1e |
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93 | .equ EEDR = 0x1d |
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94 | .equ EECR = 0x1c |
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95 | .equ PORTA = 0x1b |
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96 | .equ DDRA = 0x1a |
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97 | .equ PINA = 0x19 |
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98 | .equ PORTB = 0x18 |
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99 | .equ DDRB = 0x17 |
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100 | .equ PINB = 0x16 |
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101 | .equ PORTC = 0x15 |
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102 | .equ DDRC = 0x14 |
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103 | .equ PINC = 0x13 |
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104 | .equ PORTD = 0x12 |
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105 | .equ DDRD = 0x11 |
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106 | .equ PIND = 0x10 |
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107 | .equ SPDR = 0x0f |
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108 | .equ SPSR = 0x0e |
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109 | .equ SPCR = 0x0d |
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110 | .equ UDR = 0x0c |
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111 | .equ UCSRA = 0x0b |
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112 | .equ UCSRB = 0x0a |
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113 | .equ UBRR = 0x09 |
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114 | .equ ACSR = 0x08 |
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115 | .equ ADMUX = 0x07 |
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116 | .equ ADCSRA = 0x06 |
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117 | .equ ADCH = 0x05 |
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118 | .equ ADCL = 0x04 |
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119 | .equ TWDR = 0x03 |
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120 | .equ TWAR = 0x02 |
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121 | .equ TWSR = 0x01 |
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122 | .equ TWBR = 0x00 |
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123 | |||
124 | |||
125 | ; ***** BIT DEFINITIONS ************************************************** |
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126 | |||
127 | ; ***** TIMER_COUNTER_0 ************** |
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128 | ; TIMSK - Timer/Counter Interrupt Mask Register |
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129 | .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
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130 | |||
131 | ; TIFR - Timer/Counter Interrupt Flag register |
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132 | .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
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133 | |||
134 | ; TCCR0 - Timer/Counter0 Control Register |
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135 | .equ CS00 = 0 ; Clock Select0 bit 0 |
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136 | .equ CS01 = 1 ; Clock Select0 bit 1 |
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137 | .equ CS02 = 2 ; Clock Select0 bit 2 |
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138 | |||
139 | ; TCNT0 - Timer Counter 0 |
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140 | .equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
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141 | .equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
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142 | .equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
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143 | .equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
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144 | .equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
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145 | .equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
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146 | .equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
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147 | .equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
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148 | |||
149 | |||
150 | ; ***** CPU ************************** |
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151 | ; SREG - Status Register |
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152 | .equ SREG_C = 0 ; Carry Flag |
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153 | .equ SREG_Z = 1 ; Zero Flag |
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154 | .equ SREG_N = 2 ; Negative Flag |
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155 | .equ SREG_V = 3 ; Two's Complement Overflow Flag |
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156 | .equ SREG_S = 4 ; Sign Bit |
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157 | .equ SREG_H = 5 ; Half Carry Flag |
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158 | .equ SREG_T = 6 ; Bit Copy Storage |
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159 | .equ SREG_I = 7 ; Global Interrupt Enable |
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160 | |||
161 | ; OSCCAL - Oscillator Calibration Value |
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162 | .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
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163 | .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
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164 | .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
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165 | .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
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166 | .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
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167 | .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
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168 | .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
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169 | .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
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170 | |||
171 | ; MCUCR - MCU Control register |
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172 | .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
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173 | .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
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174 | .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
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175 | .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
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176 | .equ SM0 = 4 ; Sleep Mode Select Bit 1 |
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177 | .equ SM1 = 5 ; Sleep Mode Select Bit 1 |
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178 | .equ SE = 6 ; Sleep enable |
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179 | |||
180 | ; MCUSR - MCU Status Register |
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181 | .equ PORF = 0 ; Power-on reset flag |
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182 | .equ EXTRF = 1 ; External Reset Flag |
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183 | .equ EXTREF = EXTRF ; For compatibility |
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184 | .equ BORF = 2 ; Brown-out Reset Flag |
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185 | .equ WDRF = 3 ; Watchdog Reset Flag |
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186 | |||
187 | ; SFIOR - MCU Status Register |
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188 | .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
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189 | .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
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190 | .equ PUD = 2 ; Pull-up Disable |
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191 | .equ ACME = 3 ; Analog Comparator multiplexer Enable |
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192 | |||
193 | |||
194 | ; ***** TIMER_COUNTER_1 ************** |
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195 | ; TIMSK - Timer/Counter Interrupt Mask Register |
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196 | .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
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197 | .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
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198 | .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
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199 | .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
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200 | |||
201 | ; TIFR - Timer/Counter Interrupt Flag register |
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202 | .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
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203 | .equ OCF1B = 3 ; Output Compare Flag 1B |
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204 | .equ OCF1A = 4 ; Output Compare Flag 1A |
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205 | .equ ICF1 = 5 ; Input Capture Flag 1 |
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206 | |||
207 | ; TCCR1A - Timer/Counter1 Control Register A |
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208 | .equ PWM10 = 0 ; Pulse Width Modulator Select Bits |
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209 | .equ PWM11 = 1 ; Pulse Width Modulator Select Bits |
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210 | .equ FOC1B = 2 ; Force Output Compare 1B |
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211 | .equ FOC1A = 3 ; Force Output Compare 1A |
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212 | .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
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213 | .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
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214 | .equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
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215 | .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
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216 | |||
217 | ; TCCR1B - Timer/Counter1 Control Register B |
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218 | .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
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219 | .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
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220 | .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
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221 | .equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
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222 | .equ ICES1 = 6 ; Input Capture 1 Edge Select |
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223 | .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
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224 | |||
225 | |||
226 | ; ***** TIMER_COUNTER_2 ************** |
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227 | ; TIMSK - Timer/Counter Interrupt Mask register |
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228 | .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
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229 | .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
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230 | |||
231 | ; TIFR - Timer/Counter Interrupt Flag Register |
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232 | .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
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233 | .equ OCF2 = 7 ; Output Compare Flag 2 |
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234 | |||
235 | ; TCCR2 - Timer/Counter2 Control Register |
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236 | .equ CS20 = 0 ; Clock Select bit 0 |
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237 | .equ CS21 = 1 ; Clock Select bit 1 |
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238 | .equ CS22 = 2 ; Clock Select bit 2 |
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239 | .equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match |
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240 | .equ COM20 = 4 ; Compare Output Mode bit 0 |
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241 | .equ COM21 = 5 ; Compare Output Mode bit 1 |
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242 | .equ PWM2 = 6 ; Pulse Width Modulator Enable |
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243 | .equ FOC2 = 7 ; Force Output Compare |
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244 | |||
245 | ; TCNT2 - Timer/Counter2 |
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246 | .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
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247 | .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
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248 | .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
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249 | .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
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250 | .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
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251 | .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
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252 | .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
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253 | .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
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254 | |||
255 | ; OCR2 - Timer/Counter2 Output Compare Register |
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256 | .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
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257 | .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
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258 | .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
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259 | .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
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260 | .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
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261 | .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
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262 | .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
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263 | .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
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264 | |||
265 | ; ASSR - Asynchronous Status Register |
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266 | .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
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267 | .equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
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268 | .equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
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269 | .equ AS2 = 3 ; Asynchronous Timer/counter2 |
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270 | |||
271 | |||
272 | ; ***** WATCHDOG ********************* |
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273 | ; WDTCR - Watchdog Timer Control Register |
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274 | .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
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275 | .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
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276 | .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
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277 | .equ WDE = 3 ; Watch Dog Enable |
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278 | .equ WDTOE = 4 ; RW |
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279 | .equ WDDE = WDTOE ; For compatibility |
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280 | |||
281 | |||
282 | ; ***** EEPROM *********************** |
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283 | ; EEDR - EEPROM Data Register |
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284 | .equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
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285 | .equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
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286 | .equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
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287 | .equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
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288 | .equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
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289 | .equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
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290 | .equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
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291 | .equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
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292 | |||
293 | ; EECR - EEPROM Control Register |
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294 | .equ EERE = 0 ; EEPROM Read Enable |
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295 | .equ EEWE = 1 ; EEPROM Write Enable |
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296 | .equ EEMWE = 2 ; EEPROM Master Write Enable |
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297 | .equ EEWEE = EEMWE ; For compatibility |
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298 | .equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
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299 | |||
300 | |||
301 | ; ***** SPI ************************** |
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302 | ; SPDR - SPI Data Register |
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303 | .equ SPDR0 = 0 ; SPI Data Register bit 0 |
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304 | .equ SPDR1 = 1 ; SPI Data Register bit 1 |
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305 | .equ SPDR2 = 2 ; SPI Data Register bit 2 |
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306 | .equ SPDR3 = 3 ; SPI Data Register bit 3 |
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307 | .equ SPDR4 = 4 ; SPI Data Register bit 4 |
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308 | .equ SPDR5 = 5 ; SPI Data Register bit 5 |
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309 | .equ SPDR6 = 6 ; SPI Data Register bit 6 |
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310 | .equ SPDR7 = 7 ; SPI Data Register bit 7 |
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311 | |||
312 | ; SPSR - SPI Status Register |
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313 | .equ SPI2X = 0 ; Double SPI Speed Bit |
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314 | .equ WCOL = 6 ; Write Collision Flag |
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315 | .equ SPIF = 7 ; SPI Interrupt Flag |
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316 | |||
317 | ; SPCR - SPI Control Register |
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318 | .equ SPR0 = 0 ; SPI Clock Rate Select 0 |
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319 | .equ SPR1 = 1 ; SPI Clock Rate Select 1 |
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320 | .equ CPHA = 2 ; Clock Phase |
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321 | .equ CPOL = 3 ; Clock polarity |
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322 | .equ MSTR = 4 ; Master/Slave Select |
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323 | .equ DORD = 5 ; Data Order |
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324 | .equ SPE = 6 ; SPI Enable |
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325 | .equ SPIE = 7 ; SPI Interrupt Enable |
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326 | |||
327 | |||
328 | ; ***** UART ************************* |
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329 | ; UDR - UART I/O Data Register |
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330 | .equ UDR0 = 0 ; UART I/O Data Register bit 0 |
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331 | .equ UDR1 = 1 ; UART I/O Data Register bit 1 |
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332 | .equ UDR2 = 2 ; UART I/O Data Register bit 2 |
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333 | .equ UDR3 = 3 ; UART I/O Data Register bit 3 |
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334 | .equ UDR4 = 4 ; UART I/O Data Register bit 4 |
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335 | .equ UDR5 = 5 ; UART I/O Data Register bit 5 |
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336 | .equ UDR6 = 6 ; UART I/O Data Register bit 6 |
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337 | .equ UDR7 = 7 ; UART I/O Data Register bit 7 |
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338 | |||
339 | ; UCSRA - UART Control and Status register A |
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340 | .equ MPCM = 0 ; Multi Processor Communication Mode |
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341 | .equ U2X = 1 ; Double the UART Transmission Speed |
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342 | .equ DOR = 3 ; Data overRun |
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343 | .equ FE = 4 ; Framing Error |
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344 | .equ UDRE = 5 ; UART Data Register Empty |
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345 | .equ TXC = 6 ; UART Transmitt Complete |
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346 | .equ RXC = 7 ; UART Receive Complete |
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347 | |||
348 | ; UCSRB - UART Control an Status register B |
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349 | .equ TXB8 = 0 ; Transmit Data Bit 8 |
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350 | .equ RXB8 = 1 ; Receive Data Bit 8 |
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351 | .equ CHR9 = 2 ; 9-bit Characters |
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352 | .equ TXEN = 3 ; Transmitter Enable |
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353 | .equ RXEN = 4 ; Receiver Enable |
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354 | .equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
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355 | .equ TXCIE = 6 ; TX Complete Interrupt Enable |
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356 | .equ RXCIE = 7 ; RX Complete Interrupt Enable |
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357 | |||
358 | ; UBRRHI - UART Baud Rate Register High Byte |
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359 | .equ UBRRHI0 = 0 ; UART Baud Rate Register High Byte bit 0 |
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360 | .equ UBRRHI1 = 1 ; UART Baud Rate Register High Byte bit 1 |
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361 | .equ UBRRHI2 = 2 ; UART Baud Rate Register High Byte bit 2 |
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362 | .equ UBRRHI3 = 3 ; UART Baud Rate Register High Byte bit 3 |
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363 | |||
364 | ; UBRR - UART Baud Rate Register |
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365 | .equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
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366 | .equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
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367 | .equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
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368 | .equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
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369 | .equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
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370 | .equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
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371 | .equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
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372 | .equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
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373 | |||
374 | |||
375 | ; ***** TWI ************************** |
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376 | ; TWBR - TWI Bit Rate register |
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377 | .equ TWBR0 = 0 ; |
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378 | .equ TWBR1 = 1 ; |
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379 | .equ TWBR2 = 2 ; |
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380 | .equ TWBR3 = 3 ; |
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381 | .equ TWBR4 = 4 ; |
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382 | .equ TWBR5 = 5 ; |
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383 | .equ TWBR6 = 6 ; |
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384 | .equ TWBR7 = 7 ; |
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385 | |||
386 | ; TWCR - TWI Control Register |
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387 | .equ TWIE = 0 ; TWI Interrupt Enable |
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388 | .equ TWEN = 2 ; TWI Enable Bit |
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389 | .equ TWWC = 3 ; TWI Write Collition Flag |
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390 | .equ TWSTO = 4 ; TWI Stop Condition Bit |
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391 | .equ TWSTA = 5 ; TWI Start Condition Bit |
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392 | .equ TWEA = 6 ; TWI Enable Acknowledge Bit |
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393 | .equ TWINT = 7 ; TWI Interrupt Flag |
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394 | |||
395 | ; TWSR - TWI Status Register |
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396 | .equ TWS3 = 3 ; TWI Status |
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397 | .equ TWS4 = 4 ; TWI Status |
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398 | .equ TWS5 = 5 ; TWI Status |
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399 | .equ TWS6 = 6 ; TWI Status |
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400 | .equ TWS7 = 7 ; TWI Status |
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401 | |||
402 | ; TWDR - TWI Data register |
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403 | .equ TWD0 = 0 ; TWI Data Register Bit 0 |
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404 | .equ TWD1 = 1 ; TWI Data Register Bit 1 |
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405 | .equ TWD2 = 2 ; TWI Data Register Bit 2 |
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406 | .equ TWD3 = 3 ; TWI Data Register Bit 3 |
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407 | .equ TWD4 = 4 ; TWI Data Register Bit 4 |
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408 | .equ TWD5 = 5 ; TWI Data Register Bit 5 |
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409 | .equ TWD6 = 6 ; TWI Data Register Bit 6 |
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410 | .equ TWD7 = 7 ; TWI Data Register Bit 7 |
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411 | |||
412 | ; TWAR - TWI (Slave) Address register |
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413 | .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
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414 | .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
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415 | .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
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416 | .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
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417 | .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
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418 | .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
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419 | .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
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420 | .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
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421 | |||
422 | |||
423 | ; ***** PORTA ************************ |
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424 | ; PORTA - Port A Data Register |
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425 | .equ PORTA0 = 0 ; Port A Data Register bit 0 |
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426 | .equ PA0 = 0 ; For compatibility |
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427 | .equ PORTA1 = 1 ; Port A Data Register bit 1 |
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428 | .equ PA1 = 1 ; For compatibility |
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429 | .equ PORTA2 = 2 ; Port A Data Register bit 2 |
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430 | .equ PA2 = 2 ; For compatibility |
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431 | .equ PORTA3 = 3 ; Port A Data Register bit 3 |
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432 | .equ PA3 = 3 ; For compatibility |
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433 | .equ PORTA4 = 4 ; Port A Data Register bit 4 |
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434 | .equ PA4 = 4 ; For compatibility |
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435 | .equ PORTA5 = 5 ; Port A Data Register bit 5 |
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436 | .equ PA5 = 5 ; For compatibility |
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437 | .equ PORTA6 = 6 ; Port A Data Register bit 6 |
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438 | .equ PA6 = 6 ; For compatibility |
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439 | .equ PORTA7 = 7 ; Port A Data Register bit 7 |
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440 | .equ PA7 = 7 ; For compatibility |
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441 | |||
442 | ; DDRA - Port A Data Direction Register |
||
443 | .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
||
444 | .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
||
445 | .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
||
446 | .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
||
447 | .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
||
448 | .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
||
449 | .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
||
450 | .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
||
451 | |||
452 | ; PINA - Port A Input Pins |
||
453 | .equ PINA0 = 0 ; Input Pins, Port A bit 0 |
||
454 | .equ PINA1 = 1 ; Input Pins, Port A bit 1 |
||
455 | .equ PINA2 = 2 ; Input Pins, Port A bit 2 |
||
456 | .equ PINA3 = 3 ; Input Pins, Port A bit 3 |
||
457 | .equ PINA4 = 4 ; Input Pins, Port A bit 4 |
||
458 | .equ PINA5 = 5 ; Input Pins, Port A bit 5 |
||
459 | .equ PINA6 = 6 ; Input Pins, Port A bit 6 |
||
460 | .equ PINA7 = 7 ; Input Pins, Port A bit 7 |
||
461 | |||
462 | |||
463 | ; ***** PORTB ************************ |
||
464 | ; PORTB - Port B Data Register |
||
465 | .equ PORTB0 = 0 ; Port B Data Register bit 0 |
||
466 | .equ PB0 = 0 ; For compatibility |
||
467 | .equ PORTB1 = 1 ; Port B Data Register bit 1 |
||
468 | .equ PB1 = 1 ; For compatibility |
||
469 | .equ PORTB2 = 2 ; Port B Data Register bit 2 |
||
470 | .equ PB2 = 2 ; For compatibility |
||
471 | .equ PORTB3 = 3 ; Port B Data Register bit 3 |
||
472 | .equ PB3 = 3 ; For compatibility |
||
473 | .equ PORTB4 = 4 ; Port B Data Register bit 4 |
||
474 | .equ PB4 = 4 ; For compatibility |
||
475 | .equ PORTB5 = 5 ; Port B Data Register bit 5 |
||
476 | .equ PB5 = 5 ; For compatibility |
||
477 | .equ PORTB6 = 6 ; Port B Data Register bit 6 |
||
478 | .equ PB6 = 6 ; For compatibility |
||
479 | .equ PORTB7 = 7 ; Port B Data Register bit 7 |
||
480 | .equ PB7 = 7 ; For compatibility |
||
481 | |||
482 | ; DDRB - Port B Data Direction Register |
||
483 | .equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
||
484 | .equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
||
485 | .equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
||
486 | .equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
||
487 | .equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
||
488 | .equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
||
489 | .equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
||
490 | .equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
||
491 | |||
492 | ; PINB - Port B Input Pins |
||
493 | .equ PINB0 = 0 ; Port B Input Pins bit 0 |
||
494 | .equ PINB1 = 1 ; Port B Input Pins bit 1 |
||
495 | .equ PINB2 = 2 ; Port B Input Pins bit 2 |
||
496 | .equ PINB3 = 3 ; Port B Input Pins bit 3 |
||
497 | .equ PINB4 = 4 ; Port B Input Pins bit 4 |
||
498 | .equ PINB5 = 5 ; Port B Input Pins bit 5 |
||
499 | .equ PINB6 = 6 ; Port B Input Pins bit 6 |
||
500 | .equ PINB7 = 7 ; Port B Input Pins bit 7 |
||
501 | |||
502 | |||
503 | ; ***** PORTC ************************ |
||
504 | ; PORTC - Port C Data Register |
||
505 | .equ PORTC0 = 0 ; Port C Data Register bit 0 |
||
506 | .equ PC0 = 0 ; For compatibility |
||
507 | .equ PORTC1 = 1 ; Port C Data Register bit 1 |
||
508 | .equ PC1 = 1 ; For compatibility |
||
509 | .equ PORTC2 = 2 ; Port C Data Register bit 2 |
||
510 | .equ PC2 = 2 ; For compatibility |
||
511 | .equ PORTC3 = 3 ; Port C Data Register bit 3 |
||
512 | .equ PC3 = 3 ; For compatibility |
||
513 | .equ PORTC4 = 4 ; Port C Data Register bit 4 |
||
514 | .equ PC4 = 4 ; For compatibility |
||
515 | .equ PORTC5 = 5 ; Port C Data Register bit 5 |
||
516 | .equ PC5 = 5 ; For compatibility |
||
517 | .equ PORTC6 = 6 ; Port C Data Register bit 6 |
||
518 | .equ PC6 = 6 ; For compatibility |
||
519 | .equ PORTC7 = 7 ; Port C Data Register bit 7 |
||
520 | .equ PC7 = 7 ; For compatibility |
||
521 | |||
522 | ; DDRC - Port C Data Direction Register |
||
523 | .equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
||
524 | .equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
||
525 | .equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
||
526 | .equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
||
527 | .equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
||
528 | .equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
||
529 | .equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
||
530 | .equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
||
531 | |||
532 | ; PINC - Port C Input Pins |
||
533 | .equ PINC0 = 0 ; Port C Input Pins bit 0 |
||
534 | .equ PINC1 = 1 ; Port C Input Pins bit 1 |
||
535 | .equ PINC2 = 2 ; Port C Input Pins bit 2 |
||
536 | .equ PINC3 = 3 ; Port C Input Pins bit 3 |
||
537 | .equ PINC4 = 4 ; Port C Input Pins bit 4 |
||
538 | .equ PINC5 = 5 ; Port C Input Pins bit 5 |
||
539 | .equ PINC6 = 6 ; Port C Input Pins bit 6 |
||
540 | .equ PINC7 = 7 ; Port C Input Pins bit 7 |
||
541 | |||
542 | |||
543 | ; ***** PORTD ************************ |
||
544 | ; PORTD - Port D Data Register |
||
545 | .equ PORTD0 = 0 ; Port D Data Register bit 0 |
||
546 | .equ PD0 = 0 ; For compatibility |
||
547 | .equ PORTD1 = 1 ; Port D Data Register bit 1 |
||
548 | .equ PD1 = 1 ; For compatibility |
||
549 | .equ PORTD2 = 2 ; Port D Data Register bit 2 |
||
550 | .equ PD2 = 2 ; For compatibility |
||
551 | .equ PORTD3 = 3 ; Port D Data Register bit 3 |
||
552 | .equ PD3 = 3 ; For compatibility |
||
553 | .equ PORTD4 = 4 ; Port D Data Register bit 4 |
||
554 | .equ PD4 = 4 ; For compatibility |
||
555 | .equ PORTD5 = 5 ; Port D Data Register bit 5 |
||
556 | .equ PD5 = 5 ; For compatibility |
||
557 | .equ PORTD6 = 6 ; Port D Data Register bit 6 |
||
558 | .equ PD6 = 6 ; For compatibility |
||
559 | .equ PORTD7 = 7 ; Port D Data Register bit 7 |
||
560 | .equ PD7 = 7 ; For compatibility |
||
561 | |||
562 | ; DDRD - Port D Data Direction Register |
||
563 | .equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
||
564 | .equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
||
565 | .equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
||
566 | .equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
||
567 | .equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
||
568 | .equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
||
569 | .equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
||
570 | .equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
||
571 | |||
572 | ; PIND - Port D Input Pins |
||
573 | .equ PIND0 = 0 ; Port D Input Pins bit 0 |
||
574 | .equ PIND1 = 1 ; Port D Input Pins bit 1 |
||
575 | .equ PIND2 = 2 ; Port D Input Pins bit 2 |
||
576 | .equ PIND3 = 3 ; Port D Input Pins bit 3 |
||
577 | .equ PIND4 = 4 ; Port D Input Pins bit 4 |
||
578 | .equ PIND5 = 5 ; Port D Input Pins bit 5 |
||
579 | .equ PIND6 = 6 ; Port D Input Pins bit 6 |
||
580 | .equ PIND7 = 7 ; Port D Input Pins bit 7 |
||
581 | |||
582 | |||
583 | ; ***** ANALOG_COMPARATOR ************ |
||
584 | ; SFIOR - Special Function IO Register |
||
585 | ;.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
||
586 | |||
587 | ; ACSR - Analog Comparator Control And Status Register |
||
588 | .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
||
589 | .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
||
590 | .equ ACIC = 2 ; Analog Comparator Input Capture Enable |
||
591 | .equ ACIE = 3 ; Analog Comparator Interrupt Enable |
||
592 | .equ ACI = 4 ; Analog Comparator Interrupt Flag |
||
593 | .equ ACO = 5 ; Analog Compare Output |
||
594 | .equ ACBG = 6 ; Analog Comparator Bandgap Select |
||
595 | .equ ACD = 7 ; Analog Comparator Disable |
||
596 | |||
597 | |||
598 | ; ***** AD_CONVERTER ***************** |
||
599 | ; ADMUX - The ADC multiplexer Selection Register |
||
600 | .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
||
601 | .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
||
602 | .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
||
603 | .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
||
604 | .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
||
605 | .equ ADLAR = 5 ; Left Adjust Result |
||
606 | .equ REFS0 = 6 ; Reference Selection Bit 0 |
||
607 | .equ REFS1 = 7 ; Reference Selection Bit 1 |
||
608 | |||
609 | ; ADCSRA - The ADC Control and Status register |
||
610 | .equ ADCSR = ADCSRA ; For compatibility |
||
611 | .equ ADPS0 = 0 ; ADC Prescaler Select Bits |
||
612 | .equ ADPS1 = 1 ; ADC Prescaler Select Bits |
||
613 | .equ ADPS2 = 2 ; ADC Prescaler Select Bits |
||
614 | .equ ADIE = 3 ; ADC Interrupt Enable |
||
615 | .equ ADIF = 4 ; ADC Interrupt Flag |
||
616 | .equ ADFR = 5 ; ADC Free Running Select |
||
617 | .equ ADSC = 6 ; ADC Start Conversion |
||
618 | .equ ADEN = 7 ; ADC Enable |
||
619 | |||
620 | ; ADCH - ADC Data Register High Byte |
||
621 | .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
||
622 | .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
||
623 | .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
||
624 | .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
||
625 | .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
||
626 | .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
||
627 | .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
||
628 | .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
||
629 | |||
630 | ; ADCL - ADC Data Register Low Byte |
||
631 | .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
||
632 | .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
||
633 | .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
||
634 | .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
||
635 | .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
||
636 | .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
||
637 | .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
||
638 | .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
||
639 | |||
640 | |||
641 | ; ***** EXTERNAL_INTERRUPT *********** |
||
642 | ; GIMSK - General Interrupt Mask Register |
||
643 | .equ INT0 = 6 ; External Interrupt Request 0 Enable |
||
644 | .equ INT1 = 7 ; External Interrupt Request 1 Enable |
||
645 | |||
646 | ; GIFR - General Interrupt Flag register |
||
647 | .equ INTF0 = 6 ; External Interrupt Flag 0 |
||
648 | .equ INTF1 = 7 ; External Interrupt Flag 1 |
||
649 | |||
650 | |||
651 | ; ***** BOOT_LOAD ******************** |
||
652 | ; SPMCR - Store Program Memory Control Register |
||
653 | .equ SPMEN = 0 ; Store Program Memory Enable |
||
654 | .equ PGERS = 1 ; Page Erase |
||
655 | .equ PGWRT = 2 ; Page Write |
||
656 | .equ BLBSET = 3 ; Boot Lock Bit Set |
||
657 | .equ ASRE = 4 ; Application section read enable |
||
658 | .equ ASB = 6 ; Application section busy |
||
659 | |||
660 | |||
661 | |||
662 | ; ***** LOCKSBITS ******************************************************** |
||
663 | .equ LB1 = 0 ; Lock bit |
||
664 | .equ LB2 = 1 ; Lock bit |
||
665 | .equ BLB01 = 2 ; Boot Lock bit |
||
666 | .equ BLB02 = 3 ; Boot Lock bit |
||
667 | .equ BLB11 = 4 ; Boot lock bit |
||
668 | .equ BLB12 = 5 ; Boot lock bit |
||
669 | |||
670 | |||
671 | ; ***** FUSES ************************************************************ |
||
672 | ; LOW fuse bits |
||
673 | |||
674 | ; HIGH fuse bits |
||
675 | |||
676 | |||
677 | |||
678 | ; ***** CPU REGISTER DEFINITIONS ***************************************** |
||
679 | .def XH = r27 |
||
680 | .def XL = r26 |
||
681 | .def YH = r29 |
||
682 | .def YL = r28 |
||
683 | .def ZH = r31 |
||
684 | .def ZL = r30 |
||
685 | |||
686 | |||
687 | |||
688 | ; ***** DATA MEMORY DECLARATIONS ***************************************** |
||
689 | .equ FLASHEND = 0x1fff ; Note: Word address |
||
690 | .equ IOEND = 0x003f |
||
691 | .equ SRAM_START = 0x0060 |
||
692 | .equ SRAM_SIZE = 1024 |
||
693 | .equ RAMEND = 0x045f |
||
694 | .equ XRAMEND = 0x0000 |
||
695 | .equ E2END = 0x01ff |
||
696 | .equ EEPROMEND = 0x01ff |
||
697 | .equ EEADRBITS = 9 |
||
698 | #pragma AVRPART MEMORY PROG_FLASH 16384 |
||
699 | #pragma AVRPART MEMORY EEPROM 512 |
||
700 | #pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
||
701 | #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
||
702 | |||
703 | |||
704 | |||
705 | ; ***** BOOTLOADER DECLARATIONS ****************************************** |
||
706 | .equ NRWW_START_ADDR = 0x0 |
||
707 | .equ NRWW_STOP_ADDR = 0x1fff |
||
708 | .equ PAGESIZE = 64 |
||
709 | .equ FIRSTBOOTSTART = 0x1f80 |
||
710 | .equ SECONDBOOTSTART = 0x1f00 |
||
711 | .equ THIRDBOOTSTART = 0x1e00 |
||
712 | .equ FOURTHBOOTSTART = 0x1c00 |
||
713 | .equ SMALLBOOTSTART = FIRSTBOOTSTART |
||
714 | .equ LARGEBOOTSTART = FOURTHBOOTSTART |
||
715 | |||
716 | |||
717 | |||
718 | ; ***** INTERRUPT VECTORS ************************************************ |
||
719 | .equ INT0addr = 0x0002 ; External Interrupt 0 |
||
720 | .equ INT1addr = 0x0004 ; External Interrupt 1 |
||
721 | .equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match |
||
722 | .equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow |
||
723 | .equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event |
||
724 | .equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A |
||
725 | .equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B |
||
726 | .equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow |
||
727 | .equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow |
||
728 | .equ SPIaddr = 0x0014 ; SPI Serial Transfer Complete |
||
729 | .equ URXCaddr = 0x0016 ; UART, RX Complete |
||
730 | .equ UDREaddr = 0x0018 ; UART Data Register Empty |
||
731 | .equ UTXCaddr = 0x001a ; UART, TX Complete |
||
732 | .equ ADCCaddr = 0x001c ; ADC Conversion Complete |
||
733 | .equ ERDYaddr = 0x001e ; EEPROM Ready |
||
734 | .equ ACIaddr = 0x0020 ; Analog Comparator |
||
735 | .equ TWIaddr = 0x0022 ; 2-Wire Serial Interface |
||
736 | |||
737 | .equ INT_VECTORS_SIZE = 36 ; size in words |
||
738 | |||
739 | #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
||
740 | |||
741 | #endif /* _M163DEF_INC_ */ |
||
742 | |||
743 | ; ***** END OF FILE ****************************************************** |