WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/8535def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:30 *** Source: AT90S8535.xml *********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "8535def.inc"
		8	;* Title : Register/Bit Definitions for the AT90S8535
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : AT90S8535
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _8535DEF_INC_
		41	#define _8535DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device AT90S8535
		48	#pragma AVRPART ADMIN PART_NAME AT90S8535
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x93
		51	.equ SIGNATURE_002 = 0x03
		52
		53	#pragma AVRPART CORE CORE_VERSION V1
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ SREG = 0x3f
		61	.equ SPH = 0x3e
		62	.equ SPL = 0x3d
		63	.equ GIMSK = 0x3b
		64	.equ GIFR = 0x3a
		65	.equ TIMSK = 0x39
		66	.equ TIFR = 0x38
		67	.equ MCUCR = 0x35
		68	.equ MCUSR = 0x34
		69	.equ TCCR0 = 0x33
		70	.equ TCNT0 = 0x32
		71	.equ TCCR1A = 0x2f
		72	.equ TCCR1B = 0x2e
		73	.equ TCNT1H = 0x2d
		74	.equ TCNT1L = 0x2c
		75	.equ OCR1AH = 0x2b
		76	.equ OCR1AL = 0x2a
		77	.equ OCR1BH = 0x29
		78	.equ OCR1BL = 0x28
		79	.equ ICR1H = 0x27
		80	.equ ICR1L = 0x26
		81	.equ TCCR2 = 0x25
		82	.equ TCNT2 = 0x24
		83	.equ OCR2 = 0x23
		84	.equ ASSR = 0x22
		85	.equ WDTCR = 0x21
		86	.equ EEARH = 0x1f
		87	.equ EEARL = 0x1e
		88	.equ EEDR = 0x1d
		89	.equ EECR = 0x1c
		90	.equ PORTA = 0x1b
		91	.equ DDRA = 0x1a
		92	.equ PINA = 0x19
		93	.equ PORTB = 0x18
		94	.equ DDRB = 0x17
		95	.equ PINB = 0x16
		96	.equ PORTC = 0x15
		97	.equ DDRC = 0x14
		98	.equ PINC = 0x13
		99	.equ PORTD = 0x12
		100	.equ DDRD = 0x11
		101	.equ PIND = 0x10
		102	.equ SPDR = 0x0f
		103	.equ SPSR = 0x0e
		104	.equ SPCR = 0x0d
		105	.equ UDR = 0x0c
		106	.equ USR = 0x0b
		107	.equ UCR = 0x0a
		108	.equ UBRR = 0x09
		109	.equ ACSR = 0x08
		110	.equ ADMUX = 0x07
		111	.equ ADCSR = 0x06
		112	.equ ADCH = 0x05
		113	.equ ADCL = 0x04
		114
		115
		116	; *** BIT DEFINITIONS ************************************************
		117
		118	; *** TIMER_COUNTER_0 ************
		119	; TIMSK - Timer/Counter Interrupt Mask Register
		120	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		121
		122	; TIFR - Timer/Counter Interrupt Flag register
		123	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		124
		125	; TCCR0 - Timer/Counter0 Control Register
		126	.equ CS00 = 0 ; Clock Select0 bit 0
		127	.equ CS01 = 1 ; Clock Select0 bit 1
		128	.equ CS02 = 2 ; Clock Select0 bit 2
		129
		130	; TCNT0 - Timer Counter 0
		131	.equ TCNT00 = 0 ; Timer Counter 0 bit 0
		132	.equ TCNT01 = 1 ; Timer Counter 0 bit 1
		133	.equ TCNT02 = 2 ; Timer Counter 0 bit 2
		134	.equ TCNT03 = 3 ; Timer Counter 0 bit 3
		135	.equ TCNT04 = 4 ; Timer Counter 0 bit 4
		136	.equ TCNT05 = 5 ; Timer Counter 0 bit 5
		137	.equ TCNT06 = 6 ; Timer Counter 0 bit 6
		138	.equ TCNT07 = 7 ; Timer Counter 0 bit 7
		139
		140
		141	; *** TIMER_COUNTER_1 ************
		142	; TIMSK - Timer/Counter Interrupt Mask Register
		143	.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
		144	.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		145	.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		146	.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		147
		148	; TIFR - Timer/Counter Interrupt Flag register
		149	.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
		150	.equ OCF1B = 3 ; Output Compare Flag 1B
		151	.equ OCF1A = 4 ; Output Compare Flag 1A
		152	.equ ICF1 = 5 ; Input Capture Flag 1
		153
		154	; TCCR1A - Timer/Counter1 Control Register A
		155	.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
		156	.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
		157	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		158	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		159	.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
		160	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		161
		162	; TCCR1B - Timer/Counter1 Control Register B
		163	.equ CS10 = 0 ; Clock Select1 bit 0
		164	.equ CS11 = 1 ; Clock Select1 bit 1
		165	.equ CS12 = 2 ; Clock Select1 bit 2
		166	.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
		167	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		168	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		169
		170
		171	; *** TIMER_COUNTER_2 ************
		172	; TCCR2 - Timer/Counter Control Register
		173	.equ CS20 = 0 ; Clock Select
		174	.equ CS21 = 1 ; Clock Select
		175	.equ CS22 = 2 ; Clock Select
		176	.equ CTC2 = 3 ; Clear Timer/Counter Compare Match
		177	.equ COM20 = 4 ; Compare Match Output Mode
		178	.equ COM21 = 5 ; Compare Match Output Mode
		179	.equ PWM2 = 6 ; Pulse Width Modulator Enable
		180
		181	; TCNT2 - Timer/Counter Register
		182	.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
		183	.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
		184	.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
		185	.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
		186	.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
		187	.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
		188	.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
		189	.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
		190
		191	; OCR2 - Output Compare Register
		192	.equ OCR2_0 = 0 ; Output Compare Register Bit 0
		193	.equ OCR2_1 = 1 ; Output Compare Register Bit 1
		194	.equ OCR2_2 = 2 ; Output Compare Register Bit 2
		195	.equ OCR2_3 = 3 ; Output Compare Register Bit 3
		196	.equ OCR2_4 = 4 ; Output Compare Register Bit 4
		197	.equ OCR2_5 = 5 ; Output Compare Register Bit 5
		198	.equ OCR2_6 = 6 ; Output Compare Register Bit 6
		199	.equ OCR2_7 = 7 ; Output Compare Register Bit 7
		200
		201	; ASSR - Asynchronous Status Register
		202	.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy
		203	.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
		204	.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
		205	.equ AS2 = 3 ; Asynchronous Timer 2
		206
		207	; TIMSK - Timer/Counter Interrupt Mask Register
		208	.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
		209	.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
		210
		211	; TIFR - Timer/Counter Interrupt Flag Register
		212	.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
		213	.equ OCF2 = 7 ; Output Compare Flag 2
		214
		215
		216	; *** UART ***********************
		217	; UDR - UART I/O Data Register
		218	.equ UDR0 = 0 ; UART I/O Data Register bit 0
		219	.equ UDR1 = 1 ; UART I/O Data Register bit 1
		220	.equ UDR2 = 2 ; UART I/O Data Register bit 2
		221	.equ UDR3 = 3 ; UART I/O Data Register bit 3
		222	.equ UDR4 = 4 ; UART I/O Data Register bit 4
		223	.equ UDR5 = 5 ; UART I/O Data Register bit 5
		224	.equ UDR6 = 6 ; UART I/O Data Register bit 6
		225	.equ UDR7 = 7 ; UART I/O Data Register bit 7
		226
		227	; USR - UART Status Register
		228	.equ DOR = 3 ; Data overRun
		229	.equ FE = 4 ; Framing Error
		230	.equ UDRE = 5 ; UART Data Register Empty
		231	.equ TXC = 6 ; UART Transmit Complete
		232	.equ RXC = 7 ; UART Receive Complete
		233
		234	; UCR - UART Control Register
		235	.equ TXB8 = 0 ; Transmit Data Bit 8
		236	.equ RXB8 = 1 ; Receive Data Bit 8
		237	.equ CHR9 = 2 ; 9-bit Characters
		238	.equ TXEN = 3 ; Transmitter Enable
		239	.equ RXEN = 4 ; Receiver Enable
		240	.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
		241	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		242	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		243
		244	; UBRR - UART BAUD Rate Register
		245	.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
		246	.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
		247	.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
		248	.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
		249	.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
		250	.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
		251	.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
		252	.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
		253
		254
		255	; *** SPI ************************
		256	; SPDR - SPI Data Register
		257	.equ SPDR0 = 0 ; SPI Data Register bit 0
		258	.equ SPDR1 = 1 ; SPI Data Register bit 1
		259	.equ SPDR2 = 2 ; SPI Data Register bit 2
		260	.equ SPDR3 = 3 ; SPI Data Register bit 3
		261	.equ SPDR4 = 4 ; SPI Data Register bit 4
		262	.equ SPDR5 = 5 ; SPI Data Register bit 5
		263	.equ SPDR6 = 6 ; SPI Data Register bit 6
		264	.equ SPDR7 = 7 ; SPI Data Register bit 7
		265
		266	; SPSR - SPI Status Register
		267	.equ WCOL = 6 ; Write Collision Flag
		268	.equ SPIF = 7 ; SPI Interrupt Flag
		269
		270	; SPCR - SPI Control Register
		271	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		272	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		273	.equ CPHA = 2 ; Clock Phase
		274	.equ CPOL = 3 ; Clock polarity
		275	.equ MSTR = 4 ; Master/Slave Select
		276	.equ DORD = 5 ; Data Order
		277	.equ SPE = 6 ; SPI Enable
		278	.equ SPIE = 7 ; SPI Interrupt Enable
		279
		280
		281	; *** PORTA **********************
		282	; PORTA - Port A Data Register
		283	.equ PORTA0 = 0 ; Port A Data Register bit 0
		284	.equ PA0 = 0 ; For compatibility
		285	.equ PORTA1 = 1 ; Port A Data Register bit 1
		286	.equ PA1 = 1 ; For compatibility
		287	.equ PORTA2 = 2 ; Port A Data Register bit 2
		288	.equ PA2 = 2 ; For compatibility
		289	.equ PORTA3 = 3 ; Port A Data Register bit 3
		290	.equ PA3 = 3 ; For compatibility
		291	.equ PORTA4 = 4 ; Port A Data Register bit 4
		292	.equ PA4 = 4 ; For compatibility
		293	.equ PORTA5 = 5 ; Port A Data Register bit 5
		294	.equ PA5 = 5 ; For compatibility
		295	.equ PORTA6 = 6 ; Port A Data Register bit 6
		296	.equ PA6 = 6 ; For compatibility
		297	.equ PORTA7 = 7 ; Port A Data Register bit 7
		298	.equ PA7 = 7 ; For compatibility
		299
		300	; DDRA - Port A Data Direction Register
		301	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		302	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		303	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		304	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		305	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		306	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		307	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		308	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		309
		310	; PINA - Port A Input Pins
		311	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		312	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		313	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		314	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		315	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		316	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		317	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		318	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		319
		320
		321	; *** PORTB **********************
		322	; PORTB - Port B Data Register
		323	.equ PORTB0 = 0 ; Port B Data Register bit 0
		324	.equ PB0 = 0 ; For compatibility
		325	.equ PORTB1 = 1 ; Port B Data Register bit 1
		326	.equ PB1 = 1 ; For compatibility
		327	.equ PORTB2 = 2 ; Port B Data Register bit 2
		328	.equ PB2 = 2 ; For compatibility
		329	.equ PORTB3 = 3 ; Port B Data Register bit 3
		330	.equ PB3 = 3 ; For compatibility
		331	.equ PORTB4 = 4 ; Port B Data Register bit 4
		332	.equ PB4 = 4 ; For compatibility
		333	.equ PORTB5 = 5 ; Port B Data Register bit 5
		334	.equ PB5 = 5 ; For compatibility
		335	.equ PORTB6 = 6 ; Port B Data Register bit 6
		336	.equ PB6 = 6 ; For compatibility
		337	.equ PORTB7 = 7 ; Port B Data Register bit 7
		338	.equ PB7 = 7 ; For compatibility
		339
		340	; DDRB - Port B Data Direction Register
		341	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		342	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		343	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		344	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		345	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		346	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		347	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		348	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		349
		350	; PINB - Port B Input Pins
		351	.equ PINB0 = 0 ; Port B Input Pins bit 0
		352	.equ PINB1 = 1 ; Port B Input Pins bit 1
		353	.equ PINB2 = 2 ; Port B Input Pins bit 2
		354	.equ PINB3 = 3 ; Port B Input Pins bit 3
		355	.equ PINB4 = 4 ; Port B Input Pins bit 4
		356	.equ PINB5 = 5 ; Port B Input Pins bit 5
		357	.equ PINB6 = 6 ; Port B Input Pins bit 6
		358	.equ PINB7 = 7 ; Port B Input Pins bit 7
		359
		360
		361	; *** PORTC **********************
		362	; PORTC - Port C Data Register
		363	.equ PORTC0 = 0 ; Port C Data Register bit 0
		364	.equ PC0 = 0 ; For compatibility
		365	.equ PORTC1 = 1 ; Port C Data Register bit 1
		366	.equ PC1 = 1 ; For compatibility
		367	.equ PORTC2 = 2 ; Port C Data Register bit 2
		368	.equ PC2 = 2 ; For compatibility
		369	.equ PORTC3 = 3 ; Port C Data Register bit 3
		370	.equ PC3 = 3 ; For compatibility
		371	.equ PORTC4 = 4 ; Port C Data Register bit 4
		372	.equ PC4 = 4 ; For compatibility
		373	.equ PORTC5 = 5 ; Port C Data Register bit 5
		374	.equ PC5 = 5 ; For compatibility
		375	.equ PORTC6 = 6 ; Port C Data Register bit 6
		376	.equ PC6 = 6 ; For compatibility
		377	.equ PORTC7 = 7 ; Port C Data Register bit 7
		378	.equ PC7 = 7 ; For compatibility
		379
		380	; DDRC - Port C Data Direction Register
		381	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		382	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		383	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		384	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		385	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		386	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		387	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		388	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		389
		390	; PINC - Port C Input Pins
		391	.equ PINC0 = 0 ; Port C Input Pins bit 0
		392	.equ PINC1 = 1 ; Port C Input Pins bit 1
		393	.equ PINC2 = 2 ; Port C Input Pins bit 2
		394	.equ PINC3 = 3 ; Port C Input Pins bit 3
		395	.equ PINC4 = 4 ; Port C Input Pins bit 4
		396	.equ PINC5 = 5 ; Port C Input Pins bit 5
		397	.equ PINC6 = 6 ; Port C Input Pins bit 6
		398	.equ PINC7 = 7 ; Port C Input Pins bit 7
		399
		400
		401	; *** PORTD **********************
		402	; PORTD - Port D Data Register
		403	.equ PORTD0 = 0 ; Port D Data Register bit 0
		404	.equ PD0 = 0 ; For compatibility
		405	.equ PORTD1 = 1 ; Port D Data Register bit 1
		406	.equ PD1 = 1 ; For compatibility
		407	.equ PORTD2 = 2 ; Port D Data Register bit 2
		408	.equ PD2 = 2 ; For compatibility
		409	.equ PORTD3 = 3 ; Port D Data Register bit 3
		410	.equ PD3 = 3 ; For compatibility
		411	.equ PORTD4 = 4 ; Port D Data Register bit 4
		412	.equ PD4 = 4 ; For compatibility
		413	.equ PORTD5 = 5 ; Port D Data Register bit 5
		414	.equ PD5 = 5 ; For compatibility
		415	.equ PORTD6 = 6 ; Port D Data Register bit 6
		416	.equ PD6 = 6 ; For compatibility
		417	.equ PORTD7 = 7 ; Port D Data Register bit 7
		418	.equ PD7 = 7 ; For compatibility
		419
		420	; DDRD - Port D Data Direction Register
		421	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		422	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		423	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		424	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		425	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		426	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		427	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		428	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		429
		430	; PIND - Port D Input Pins
		431	.equ PIND0 = 0 ; Port D Input Pins bit 0
		432	.equ PIND1 = 1 ; Port D Input Pins bit 1
		433	.equ PIND2 = 2 ; Port D Input Pins bit 2
		434	.equ PIND3 = 3 ; Port D Input Pins bit 3
		435	.equ PIND4 = 4 ; Port D Input Pins bit 4
		436	.equ PIND5 = 5 ; Port D Input Pins bit 5
		437	.equ PIND6 = 6 ; Port D Input Pins bit 6
		438	.equ PIND7 = 7 ; Port D Input Pins bit 7
		439
		440
		441	; *** ANALOG_COMPARATOR **********
		442	; ACSR - Analog Comparator Control And Status Register
		443	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		444	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		445	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		446	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		447	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		448	.equ ACO = 5 ; Analog Comparator Output
		449	.equ ACD = 7 ; Analog Comparator Disable
		450
		451
		452	; *** AD_CONVERTER ***************
		453	; ADMUX - The ADC multiplexer Selection Register
		454	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		455	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		456	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		457
		458	; ADCSR - The ADC Control and Status register
		459	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		460	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		461	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		462	.equ ADIE = 3 ; ADC Interrupt Enable
		463	.equ ADIF = 4 ; ADC Interrupt Flag
		464	.equ ADFR = 5 ; ADC Free Running Select
		465	.equ ADSC = 6 ; ADC Start Conversion
		466	.equ ADEN = 7 ; ADC Enable
		467
		468	; ADCH - ADC Data Register High Byte
		469	.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
		470	.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
		471
		472	; ADCL - ADC Data Register Low Byte
		473	.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
		474	.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
		475	.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
		476	.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
		477	.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
		478	.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
		479	.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
		480	.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
		481
		482
		483	; *** WATCHDOG *******************
		484	; WDTCR - Watchdog Timer Control Register
		485	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		486	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		487	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		488	.equ WDE = 3 ; Watch Dog Enable
		489	.equ WDTOE = 4 ; RW
		490	.equ WDDE = WDTOE ; For compatibility
		491
		492
		493	; *** EEPROM *********************
		494	; EEDR - EEPROM Data Register
		495	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		496	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		497	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		498	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		499	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		500	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		501	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		502	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		503
		504	; EECR - EEPROM Control Register
		505	.equ EERE = 0 ; EEPROM Read Enable
		506	.equ EEWE = 1 ; EEPROM Write Enable
		507	.equ EEMWE = 2 ; EEPROM Master Write Enable
		508	.equ EEWEE = EEMWE ; For compatibility
		509	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		510
		511
		512	; *** CPU ************************
		513	; SREG - Status Register
		514	.equ SREG_C = 0 ; Carry Flag
		515	.equ SREG_Z = 1 ; Zero Flag
		516	.equ SREG_N = 2 ; Negative Flag
		517	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		518	.equ SREG_S = 4 ; Sign Bit
		519	.equ SREG_H = 5 ; Half Carry Flag
		520	.equ SREG_T = 6 ; Bit Copy Storage
		521	.equ SREG_I = 7 ; Global Interrupt Enable
		522
		523	; MCUCR - MCU Control Register
		524	.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
		525	.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
		526	.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
		527	.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
		528	.equ SM0 = 4 ; Sleep Mode Select 0
		529	.equ SM1 = 5 ; Sleep Mode Select 1
		530	.equ SE = 6 ; Sleep Enable
		531
		532	; MCUSR -
		533	.equ PORF = 0 ; Power-on Reset Flag
		534	.equ EXTRF = 1 ; External Reset Flag
		535
		536
		537	; *** EXTERNAL_INTERRUPT *********
		538	; GIMSK - General Interrupt Mask Register
		539	.equ INT0 = 6 ; External Interrupt Request 0 Enable
		540	.equ INT1 = 7 ; External Interrupt Request 1 Enable
		541
		542	; GIFR - General Interrupt Flag register
		543	.equ INTF0 = 6 ; External Interrupt Flag 0
		544	.equ INTF1 = 7 ; External Interrupt Flag 1
		545
		546
		547
		548	; *** LOCKSBITS ******************************************************
		549	.equ LB1 = 0 ; Lockbit
		550	.equ LB2 = 1 ; Lockbit
		551
		552
		553	; *** FUSES **********************************************************
		554	; LOW fuse bits
		555	.equ SPIEN = 1 ; Serial Program Downloading Enabled
		556	.equ FSTRT = 2 ; Short Start-up time selected
		557
		558
		559
		560	; *** CPU REGISTER DEFINITIONS ***************************************
		561	.def XH = r27
		562	.def XL = r26
		563	.def YH = r29
		564	.def YL = r28
		565	.def ZH = r31
		566	.def ZL = r30
		567
		568
		569
		570	; *** DATA MEMORY DECLARATIONS ***************************************
		571	.equ FLASHEND = 0x0fff ; Note: Word address
		572	.equ IOEND = 0x003f
		573	.equ SRAM_START = 0x0060
		574	.equ SRAM_SIZE = 512
		575	.equ RAMEND = 0x025f
		576	.equ XRAMEND = 0x0000
		577	.equ E2END = 0x01ff
		578	.equ EEPROMEND = 0x01ff
		579	.equ EEADRBITS = 9
		580	#pragma AVRPART MEMORY PROG_FLASH 8192
		581	#pragma AVRPART MEMORY EEPROM 512
		582	#pragma AVRPART MEMORY INT_SRAM SIZE 512
		583	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
		584
		585
		586
		587
		588
		589	; *** INTERRUPT VECTORS **********************************************
		590	.equ INT0addr = 0x0001 ; External Interrupt 0
		591	.equ INT1addr = 0x0002 ; External Interrupt 1
		592	.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match
		593	.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow
		594	.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event
		595	.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A
		596	.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B
		597	.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow
		598	.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow
		599	.equ SPIaddr = 0x000a ; SPI Serial Transfer Complete
		600	.equ URXCaddr = 0x000b ; UART, RX Complete
		601	.equ UDREaddr = 0x000c ; UART Data Register Empty
		602	.equ UTXCaddr = 0x000d ; UART, TX Complete
		603	.equ ADCCaddr = 0x000e ; ADC Conversion Complete
		604	.equ ERDYaddr = 0x000f ; EEPROM Ready
		605	.equ ACIaddr = 0x0010 ; Analog Comparator
		606
		607	.equ INT_VECTORS_SIZE = 17 ; size in words
		608
		609	#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
		610
		611	#endif /* _8535DEF_INC_ */
		612
		613	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/8535def.inc – Rev 6400