Details | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
6400 | punk_joker | 1 | .NOLIST |
2 | |||
3 | ;*************************************************************************** |
||
4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
||
5 | ;* |
||
6 | ;* Number :AVR000 |
||
7 | ;* File Name :"tn15def.inc" |
||
8 | ;* Title :Register/Bit Definitions for the ATtiny15 |
||
9 | ;* Date :99.07.05 |
||
10 | ;* Version :1.00 |
||
11 | ;* Support telephone :+47 72 88 87 20 (ATMEL Norway) |
||
12 | ;* Support fax :+47 72 88 87 18 (ATMEL Norway) |
||
13 | ;* Support E-mail :avr@atmel.com |
||
14 | ;* Target MCU :ATtiny15 |
||
15 | ;* |
||
16 | ;* DESCRIPTION |
||
17 | ;* When including this file in the assembly program file, all I/O register |
||
18 | ;* names and I/O register bit names appearing in the data book can be used. |
||
19 | ;* In addition, the six registers forming the three data pointers X, Y and |
||
20 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
||
21 | ;* SRAM is also defined |
||
22 | ;* |
||
23 | ;* The Register names are represented by their hexadecimal address. |
||
24 | ;* |
||
25 | ;* The Register Bit names are represented by their bit number (0-7). |
||
26 | ;* |
||
27 | ;* Please observe the difference in using the bit names with instructions |
||
28 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
||
29 | ;* (skip if bit in register set/cleared). The following example illustrates |
||
30 | ;* this: |
||
31 | ;* |
||
32 | ;* in r16,PORTB ;read PORTB latch |
||
33 | ;* sbr r16,(1< |
||
34 | ;* out PORTB,r16 ;output to PORTB |
||
35 | ;* |
||
36 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register |
||
37 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
||
38 | ;* rjmp TOV0_is_set ;jump if set |
||
39 | ;* ... ;otherwise do something else |
||
40 | ;*************************************************************************** |
||
41 | |||
42 | ;***** Specify Device |
||
43 | .device ATtiny15 |
||
44 | |||
45 | ;***** I/O Register Definitions |
||
46 | .equ SREG =$3f |
||
47 | .equ GIMSK =$3b |
||
48 | .equ GIFR =$3a |
||
49 | .equ TIMSK =$39 |
||
50 | .equ TIFR =$38 |
||
51 | .equ MCUCR =$35 |
||
52 | .equ MCUSR =$34 |
||
53 | .equ TCCR0 =$33 |
||
54 | .equ TCNT0 =$32 |
||
55 | .equ OSCCAL =$31 |
||
56 | .equ TCCR1 =$30 |
||
57 | .equ TCNT1 =$2f |
||
58 | .equ OCR1A =$2e |
||
59 | .equ OCR1B =$2d |
||
60 | .equ SFIOR =$2c |
||
61 | .equ WDTCR =$21 |
||
62 | .equ EEAR =$1e |
||
63 | .equ EEDR =$1d |
||
64 | .equ EECR =$1c |
||
65 | .equ PORTB =$18 |
||
66 | .equ DDRB =$17 |
||
67 | .equ PINB =$16 |
||
68 | .equ ACSR =$08 |
||
69 | .equ ADMUX =$07 |
||
70 | .equ ADCSR =$06 |
||
71 | .equ ADCH =$05 |
||
72 | .equ ADCL =$04 |
||
73 | |||
74 | |||
75 | ;***** Bit Definitions |
||
76 | .equ INT0 =6 |
||
77 | .equ PCIE =5 |
||
78 | |||
79 | .equ INTF0 =6 |
||
80 | .equ PCIF =5 |
||
81 | |||
82 | .equ OCIE1 =6 |
||
83 | .equ TOIE1 =2 |
||
84 | .equ TOIE0 =1 |
||
85 | |||
86 | .equ OCF1A =6 |
||
87 | .equ TOV1 =2 |
||
88 | .equ TOV0 =1 |
||
89 | |||
90 | .equ PUD =6 |
||
91 | .equ SE =5 |
||
92 | .equ SM =4 |
||
93 | .equ SM1 =4 |
||
94 | .equ SM0 =3 |
||
95 | .equ ISC01 =1 |
||
96 | .equ ISC00 =0 |
||
97 | |||
98 | .equ WDRF =3 |
||
99 | .equ BORF =2 |
||
100 | .equ EXTRF =1 |
||
101 | .equ PORF =0 |
||
102 | |||
103 | .equ CS02 =2 |
||
104 | .equ CS01 =1 |
||
105 | .equ CS00 =0 |
||
106 | |||
107 | .equ CAL7 =7 |
||
108 | .equ CAL6 =6 |
||
109 | .equ CAL5 =5 |
||
110 | .equ CAL4 =4 |
||
111 | .equ CAL3 =3 |
||
112 | .equ CAL2 =2 |
||
113 | .equ CAL1 =1 |
||
114 | .equ CAL0 =0 |
||
115 | |||
116 | .equ CTC1 =7 |
||
117 | .equ PWM1 =6 |
||
118 | .equ COM11 =5 |
||
119 | .equ COM10 =4 |
||
120 | .equ CS13 =3 |
||
121 | .equ CS12 =2 |
||
122 | .equ CS11 =1 |
||
123 | .equ CS10 =0 |
||
124 | |||
125 | .equ FOCM =2 |
||
126 | .equ PSR1 =1 |
||
127 | .equ PSR0 =0 |
||
128 | |||
129 | .equ WDTOE =4 |
||
130 | .equ WDE =3 |
||
131 | .equ WDP2 =2 |
||
132 | .equ WDP1 =1 |
||
133 | .equ WDP0 =0 |
||
134 | |||
135 | .equ EERIE =3 |
||
136 | .equ EEMWE =2 |
||
137 | .equ EEWE =1 |
||
138 | .equ EERE =0 |
||
139 | |||
140 | .equ PB4 =4 |
||
141 | .equ PB3 =3 |
||
142 | .equ PB2 =2 |
||
143 | .equ PB1 =1 |
||
144 | .equ PB0 =0 |
||
145 | |||
146 | .equ DDB5 =5 |
||
147 | .equ DDB4 =4 |
||
148 | .equ DDB3 =3 |
||
149 | .equ DDB2 =2 |
||
150 | .equ DDB1 =1 |
||
151 | .equ DDB0 =0 |
||
152 | |||
153 | .equ PINB5 =5 |
||
154 | .equ PINB4 =4 |
||
155 | .equ PINB3 =3 |
||
156 | .equ PINB2 =2 |
||
157 | .equ PINB1 =1 |
||
158 | .equ PINB0 =0 |
||
159 | |||
160 | .equ ACD =7 |
||
161 | .equ ACO =5 |
||
162 | .equ ACI =4 |
||
163 | .equ ACIE =3 |
||
164 | .equ ACIS1 =1 |
||
165 | .equ ACIS0 =0 |
||
166 | |||
167 | .equ REFS1 =7 |
||
168 | .equ REFS0 =6 |
||
169 | .equ ADLAR =5 |
||
170 | .equ MUX2 =2 |
||
171 | .equ MUX1 =1 |
||
172 | .equ MUX0 =0 |
||
173 | |||
174 | .equ ADEN =7 |
||
175 | .equ ADSC =6 |
||
176 | .equ ADFR =5 |
||
177 | .equ ADIF =4 |
||
178 | .equ ADIE =3 |
||
179 | .equ ADPS2 =2 |
||
180 | .equ ADPS1 =1 |
||
181 | .equ ADPS0 =0 |
||
182 | |||
183 | .def ZL =r30 |
||
184 | .def ZH =r31 |
||
185 | |||
186 | .equ INT0addr=$001 ;External Interrupt0 Vector Address |
||
187 | .equ PCINTaddr=$002 ;Pin change Interrupt Vector Address |
||
188 | .equ T1COMPaddr=$003 ;Timer1 Compare match interrupt vector address |
||
189 | .equ OVF1addr=$004 ;Overflow 1 Interrupt Vector Address |
||
190 | .equ OVF0addr=$005 ;Overflow 1 Interrupt Vector Address |
||
191 | .equ EERDYaddr =$006 ;EEPROM Interrupt Vector Address |
||
192 | .equ ACIaddr =$007 ;Analog Comparator Interrupt Vector Address |
||
193 | .equ ADCCaddr =$008 ;ADC Interrupt Vector Address |
||
194 | |||
195 | .LIST |