WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/examples/throttle_dev_set.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;throttle_dev_set.inc
		2
		3	.NOLIST
		4
		5	; ***************************************************************************************
		6	; * PWM MODEL RAILROAD THROTTLE *
		7	; * *
		8	; * WRITTEN BY: PHILIP DEVRIES *
		9	; * *
		10	; * Copyright (C) 2003 Philip DeVries *
		11	; * *
		12	; * This program is free software; you can redistribute it and/or modify *
		13	; * it under the terms of the GNU General Public License as published by *
		14	; * the Free Software Foundation; either version 2 of the License, or *
		15	; * (at your option) any later version. *
		16	; * *
		17	; * This program is distributed in the hope that it will be useful, *
		18	; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
		19	; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
		20	; * GNU General Public License for more details. *
		21	; * *
		22	; * You should have received a copy of the GNU General Public License *
		23	; * along with this program; if not, write to the Free Software *
		24	; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
		25	; * *
		26	; ***************************************************************************************
		27
		28	;*********************************************************
		29	;* Hardware Settings *
		30	;*********************************************************
		31
		32	;
		33	; REGISTER ASSGINMENTS
		34	; Note that registes 16 - 31 are acessed by a larger instruction
		35	; set than registers 0 - 15.
		36	;
		37
		38
		39	;*********************************************************
		40	; REGISTER ASSIGNMENTS
		41	; GLOBAL VISIBILITY ;all functions have access to this NAME of the register
		42	; GLOBAL DURATION ;the register always MEANS the same thing.
		43	;*********************************************************
		44	.DEF Flags_1= r16 ; Global. Status flags
		45	.DEF Cycle_count= r17 ; Global. Count PWM cycles
		46	.DEF throttle_set= r18 ; Global. Current Throttle Setting
		47
		48	.ifdef SWITCH_LOWPASS ENABLED
		49	.DEF Flags_2= r19 ; Global. Switch "status" flags
		50	.endif SWITCH_LOWPASS_ENABLED
		51
		52	.ifdef MOMENTUM_ENABLED
		53	.DEF momentum_set= r4 ; Global. Input control
		54	.endif ;MOMENTUM_ENABLED
		55
		56	.ifdef TRADITIONAL_ENABLED
		57	.ifdef WALKAROUND_ENABLED
		58	.DEF throttle_hold= r14 ; Global. Previous throttle setting
		59	.DEF Flags_2= r19 ; Global. Switch "status" flags
		60	.endif ;WALKAROUND_ENABLED
		61	.endif ;TRADITIONAL_ENABLED
		62
		63	;*********************************************************
		64	; REGISTER ASSIGNMENTS
		65	; LOCAL VISIBILITY ;only the translation unit has (should have)
		66	; access to any NAME of the register
		67	; GLOBAL DURATION ;the register always MEANS the same thing.
		68	;*********************************************************
		69	.ifdef MOMENTUM_ENABLED
		70	.ifdef LOWPASS_ENABLED
		71	.DEF error_hi_prev= r2 ; Global. History of error
		72	.DEF error_lo_prev= r3 ; Global. History of error
		73	.endif ;LOWPASS_ENABLED
		74	.endif ;MOMENTUM_ENABLED
		75
		76	.ifdef TRADITIONAL_ENABLED
		77
		78	.ifdef THROTTLE_LOWPASS_ENABLED
		79	.DEF throttle_hi_prev= r9 ; Global. History of throttle handle
		80	.DEF throttle_lo_prev= r10 ; Global. History of throttle handle
		81	.endif ;THROTTLE_LOWPASS_ENABLED
		82
		83	.ifdef MOMENTUM_LOWPASS_ENABLED
		84	.DEF momentum_hi_prev= r11 ; Global. History of momentum handle
		85	.DEF momentum_lo_prev= r12 ; Global. History of momentum handle
		86	.endif ;THROTTLE_LOWPASS_ENABLED
		87
		88	.endif ;TRADITIONAL_ENABLED
		89
		90	.ifdef MOMENTUM_ENABLED
		91	.DEF speed_hi_prev= r5 ; Global. Speed at last sample time
		92	.DEF speed_lo_prev= r6 ; Global. Speed at last sample time
		93	.endif ;MOMENTUM_ENABLED
		94
		95
		96	;*********************************************************
		97	; REGISTER ASSIGNMENTS
		98	; LOCAL VISIBILITY ;only the translation unit has (should have)
		99	; access to any NAME of the register
		100	; LOCAL DURATION ;the register has different meanings in different contexts
		101	;*********************************************************
		102	.DEF Implicit= r0 ; Local. Used for implicit lpm
		103	.DEF Sreg_stack= r1 ; Local. "stack" for SREG during interrupts
		104
		105	; .DEF ZL= r30 ; Local. Used for Z pointer (low byte)
		106	; .DEF ZH= r31 ; Local. Used for Z pointer (high byte)
		107
		108	.MACRO LOWLOCAL1
		109	.DEF @0 = r7 ; Local. General Use
		110	.ENDMACRO
		111
		112	.MACRO LOWLOCAL2
		113	.DEF @0 = r8 ; Local. General Use
		114	.ENDMACRO
		115
		116	.MACRO HILOCAL1
		117	.DEF @0 = r26 ; Local. General Use
		118	.ENDMACRO
		119
		120	.MACRO HILOCAL2
		121	.DEF @0 = r27 ; Local. General Use
		122	.ENDMACRO
		123
		124	;*********************************************************
		125	; REGISTER ASSIGNMENTS
		126	; GLOBAL VISIBILITY ;all functions have access to this NAME of the register
		127	; LOCAL DURATION ;the register has different meanings in different contexts
		128	;*********************************************************
		129	.MACRO B_TEMPLOCAL
		130	.DEF @0 = r23 ; Local. Second Level Routine Safe
		131	.ENDMACRO
		132
		133	.MACRO B_TEMPLOCAL1
		134	.DEF @0 = r24 ; Local. Second Level Routine Safe
		135	.ENDMACRO
		136
		137	.MACRO B_TEMPLOCAL2
		138	.DEF @0 = r25 ; Local. Second Level Routine Safe
		139	.ENDMACRO
		140
		141	B_TEMPLOCAL B_Temp ; General use names
		142	B_TEMPLOCAL1 B_Temp1
		143	B_TEMPLOCAL2 b_Temp2
		144
		145	;ISR LOCALS
		146
		147	; UNUSED
		148
		149	;.DEF Not_used= r29
		150
		151	; GLOBALS
		152
		153
		154	;FLAGS_1 flag data
		155
		156	;.SET F_Flags_1= 0b11111111 ; All flags
		157
		158	.SET F_accel= 0b00000001 ; Accelerating if 1, decel if 0
		159	.SET BF_accel= 0x00 ; Flag bit location
		160	.SET F_brake= 0b00000010 ; Brake set if 1
		161	.SET BF_brake= 0x01 ;
		162	.SET F_stop= 0b00000100
		163	.SET BF_stop= 0x02
		164	.SET F_reverse= 0b00001000
		165	.SET BF_reverse= 0x03
		166	.SET F_negative_err= 0b00010000
		167	.SET BF_negative_err= 0x04
		168	.SET F_use_backemf= 0b00100000
		169	.SET BF_use_backemf= 0x05
		170	;.SET F_= 0b01000000
		171	;.SET BF_= 0x06
		172	;.SET F_= 0b10000000
		173	;.SET BF_= 0x07
		174
		175	.ifdef SWITCH_LOWPASS_ENABLED
		176	;FLAGS_2 flag data - count and status for forward/reverse/brake/stop
		177
		178	.SET F_Flags_2= 0b00001111 ; All flags
		179
		180	.SET F_stop_count= 0b00010000
		181	.SET BF_stop_count= 0x04
		182	.SET F_brake_count= 0b00100000
		183	.SET BF_brake_count= 0x05
		184	.SET F_reverse_count= 0b01000000
		185	.SET BF_reverse_count= 0x06
		186	.SET F_foreward_count= 0b10000000
		187	.SET BF_foreward_count= 0x07
		188
		189	;bits 0-3 the count- from 0-16
		190
		191	.endif SWITCH_LOWPASS_ENABLED
		192
		193	;PORT SETUP STUFF
		194	.SET emf_port= 0x05 ;PB5 - INPUT -- Back EMF input
		195	.SET emf_port_bit= 0b00100000 ;PIN1 ADC0
		196
		197	.SET momentum_port= 0x04 ;PB4 - INPUT -- Momentum Level input
		198	.SET momentum_port_bit= 0b00010000 ;PIN2 ADC3 Acceleration-indicator output
		199
		200	.SET dir_in_port= 0x03 ;PB3 - INPUT -- Direction/Brake
		201	.SET dir_in_port_bit= 0b00001000 ;PIN3 ADC2 Deceleration-indicator output
		202
		203	.SET throttle_port= 0x02 ;PB2 - INPUT -- Throttle Handle MAY USE INT0
		204	.SET throttle_port_bit= 0b00000100 ;PIN7 ADC1 (Could also use INTO
		205	; INT0 as DCC input.)
		206
		207	.SET pwm_port= 0x01 ;PB1 - OUTPUT -- PWM (off L)
		208	.SET pwm_port_bit= 0b00000010 ;PIN6 NO ADC
		209	; ONLY PWM PIN.
		210
		211	.SET dir_out_port= 0x00 ;PB0 - OUTPUT -- '1' = forward
		212	.SET dir_out_port_bit= 0b00000001 ;PIN5 NO ADC '0' = reverse
		213
		214
		215
		216
		217	.SET acsr_val= 0b10000000 ; bit 7 --AC0 1 --comparator disabled
		218
		219	.SET eecr_read_enable= 0b00000001 ; bit 4,5,6,7 --unused
		220	; bit 3 --EERIE 0 --interrupt disabled
		221	; bit 2 --EEMWE 0 --master write disabled
		222	; bit 1 --EEWE 0 --write disabled
		223	; bit 0 --EERE 1 --read ENABLED
		224
		225	.SET eecr_mwrite_enable= 0b00000100 ; bit 4,5,6,7 --unused
		226	; bit 3 --EERIE 0 --interrupt disabled
		227	; bit 2 --EEMWE 1 --master write ENABLED
		228	; bit 1 --EEWE 0 --write disabled
		229	; bit 0 --EERE 0 --read disabled
		230
		231	.SET eecr_write_enable= 0b00000110 ; bit 4,5,6,7 --unused
		232	; bit 3 --EERIE 0 --interrupt disabled
		233	; bit 2 --EEMWE 1 --master write ENABLED
		234	; bit 1 --EEWE 1 --write ENABLED
		235	; bit 0 --EERE 0 --read disabled
		236
		237	.SET admux_emf= 0b00100000 ; bit 4,3 --unused
		238	; bit 7 --REFS1 0 Two bits:
		239	; bit 6 --REFS0 0 Select VCC volt reference
		240	; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
		241	; bit 2 --MUX2 0 Three bits:
		242	; bit 1 --MUX1 0
		243	; bit 0 --MUX0 0 Select ADC0 from PB5
		244
		245	.SET admux_throttle= 0b00100001 ; bit 4,3 --unused
		246	; bit 7 --REFS1 0 Two bits:
		247	; bit 6 --REFS0 0 Select VCC volt reference
		248	; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
		249	; bit 2 --MUX2 0 Three bits:
		250	; bit 1 --MUX1 0
		251	; bit 0 --MUX0 1 Select ADC1 from PB2
		252
		253	.SET admux_direction= 0b00100010 ; bit 4,3 --unused
		254	; bit 7 --REFS1 0 Two bits:
		255	; bit 6 --REFS0 0 Select VCC volt reference
		256	; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
		257	; bit 2 --MUX2 0 Three bits:
		258	; bit 1 --MUX1 1
		259	; bit 0 --MUX0 0 Select ADC2 from PB3
		260
		261	.SET admux_momentum= 0b00100011 ; bit 4,3 --unused
		262	; bit 7 --REFS1 0 Two bits:
		263	; bit 6 --REFS0 0 Select VCC volt reference
		264	; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
		265	; bit 2 --MUX2 0 Three bits:
		266	; bit 1 --MUX1 1
		267	; bit 0 --MUX0 1 Select ADC3 from PB4
		268
		269	.SET admux_off= 0b00000000 ; bit 4,3 --unused
		270	; bit 7 --REFS1 0 Two bits:
		271	; bit 6 --REFS0 0 Select VCC volt reference
		272	; bit 5 --ADLAR 0 right adjust
		273	; bit 2 --MUX2 0 Three bits:
		274	; bit 1 --MUX1 0
		275	; bit 0 --MUX0 0 Select ADC0 from PB5
		276
		277	.SET adcsr_off= 0b00010011 ; bit 7 --ADCEN 0 ADC enable disable
		278	; bit 6 --ADSC 0 Start conversion no
		279	; bit 5 --ADFR 0 Free running mode disable
		280	; bit 4 --ADIF 1 Interrupt flag clear
		281	; bit 3 --ADIE 0 Interrupt enable disabled
		282	; bit 2 --ADPS2 0 Three bits:
		283	; bit 1 --ADPS1 1
		284	; bit 0 --ADPS0 1 Prescaler div 8 (200kHz)
		285
		286	.SET adcsr_enable= 0b11110011 ; bit 7 --ADCEN 1 ADC enable ENABLED
		287	; bit 6 --ADSC 1 Start conversion yes
		288	; bit 5 --ADFR 1 Free running mode ENABLED
		289	; bit 4 --ADIF 1 Interrupt flag clear
		290	; bit 3 --ADIE 0 Interrupt enable disabled
		291	; bit 2 --ADPS2 0 Three bits:
		292	; bit 1 --ADPS1 1
		293	; bit 0 --ADPS0 1 Prescaler div 8 (200kHz)
		294
		295	.SET mcucr_power_down_mode= 0b00110000
		296	; bit 7 --unused
		297	; bit 6 --PUD 0 pullups ENABLED
		298	; bit 5 --SE 1 sleep ENABLED
		299	; bit 4 --SM1 1 Two bits:
		300	; bit 3 --SM0 0 Sleep in power down mode
		301	; bit 2 --unused
		302	; bit 1 --ISC01 0 Two bits:
		303	; bit 0 --ISC00 0 INTO interrupt on logic
		304	; low input
		305
		306
		307	.SET wdtcr_off_enable= 0b00011000 ; enable watchdog turn off
		308	.SET wdtcr_off= 0b00010000 ; watchdog turn off
		309
		310	.SET gimsk_val_off= 0b00000000 ; bit 7,4,3,2,1,0 --unused
		311	; bit 6 --INTO 0 INTO interrupt disabled
		312	; bit 5 --PCIE 0 pin change interrupt disabled
		313
		314	.SET gimsk_val_pcie= 0b00100000 ; bit 7,4,3,2,1,0 --unused
		315	; bit 6 --INTO 0 INTO interrupt disabled
		316	; bit 5 --PCIE 1 pin change interrupt ENABLED
		317
		318	.SET gifr_clear= 0b01100000 ; bit 7,4,3,2,1,0 --unused
		319	; bit 6 --INTF0 1 INTO interrupt flag cleared
		320	; bit 5 --PCIF 1 pin ch. interrupt flag cleared
		321
		322	.SET timsk_val_off= 0b00000000 ; bit 7,5,4,3,0 --unused
		323	; bit 6 --OCIE1A 0 TC1 compare interrupt disabled
		324	; bit 2 --TOIE1 0 TC1 overflow interrupt disabled
		325	; bit 1 --TOIE0 0 TC0 overflow interrupt disabled
		326
		327	.SET timsk_enable_t1= 0b01000000 ; bit 7,5,4,3,0 --unused
		328	; bit 6 --OCIE1A 0 TC1 compare interrupt disabled
		329	; bit 2 --TOIE1 0 TC1 overflow interrupt disabled
		330	; bit 1 --TOIE0 0 TC0 overflow interrupt disabled
		331
		332	.SET tifr_clear_tov0= 0b00000010 ; bit 7,5,4,3,0 --unused
		333	; bit 6 --OCF1A 0 OCF1A flag not cleared
		334	; bit 2 --TOV1 0 TOV1 flag not cleared
		335	; bit 1 --TOV0 1 TOV0 flag CLEARED
		336
		337	.SET tccr1_enable_t1= 0b01100011
		338	; bit 7 --CTC1 0 Clear on compare match no
		339	; bit 6 --PWM1 1 PWM mode ENABLED
		340	; bit 5 --COM1A1 1 Two bits:
		341	; bit 4 --COM1A0 0 Clear output on OCR1A match
		342	; Set output when TCNT1 = 0
		343	; bit 3 --CS13 0 Four bits:
		344	; bit 2 --CS12 0
		345	; bit 3 --CS11 1
		346	; bit 4 --CS10 1 CK*4: 156.25nS
		347	; 256cnt = 25kHz
		348	.LIST

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(root)/contrib/toolchain/avra/examples/throttle_dev_set.inc – Rev 6400