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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 6146 | serge | 1 | /* |
| 2 | * Copyright © <2010>, Intel Corporation. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the |
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| 6 | * "Software"), to deal in the Software without restriction, including |
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| 7 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 8 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 9 | * permit persons to whom the Software is furnished to do so, subject to |
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| 10 | * the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice (including the |
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| 13 | * next paragraph) shall be included in all copies or substantial portions |
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| 14 | * of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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| 19 | * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
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| 20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | */ |
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| 25 | // Modual name: ME_header.inc for Gen8 |
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| 26 | // |
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| 27 | // Global symbols define |
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| 28 | // |
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| 29 | |||
| 30 | /* |
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| 31 | * Constant |
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| 32 | */ |
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| 33 | define(`VME_MESSAGE_TYPE_INTER', `1') |
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| 34 | define(`VME_MESSAGE_TYPE_INTRA', `2') |
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| 35 | define(`VME_MESSAGE_TYPE_MIXED', `3') |
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| 36 | |||
| 37 | define(`VME_SIC_MESSAGE_TYPE', `1') |
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| 38 | define(`VME_IME_MESSAGE_TYPE', `2') |
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| 39 | define(`VME_FBR_MESSAGE_TYPE', `3') |
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| 40 | |||
| 41 | define(`BLOCK_32X1', `0x0000001F') |
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| 42 | define(`BLOCK_4X16', `0x000F0003') |
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| 43 | define(`BLOCK_8X4', `0x00070003') |
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| 44 | |||
| 45 | define(`LUMA_INTRA_16x16_DISABLE', `0x1') |
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| 46 | define(`LUMA_INTRA_8x8_DISABLE', `0x2') |
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| 47 | define(`LUMA_INTRA_4x4_DISABLE', `0x4') |
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| 48 | |||
| 49 | define(`SUB_PART_8x4_DISABLE', `0x10') |
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| 50 | define(`SUB_PART_4x8_DISABLE', `0x20') |
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| 51 | |||
| 52 | define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') |
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| 53 | define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') |
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| 54 | define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') |
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| 55 | define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') |
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| 56 | |||
| 57 | define(`BIND_IDX_VME', `0') |
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| 58 | define(`BIND_IDX_VME_REF0', `1') |
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| 59 | define(`BIND_IDX_VME_REF1', `2') |
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| 60 | define(`BIND_IDX_OUTPUT', `3') |
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| 61 | define(`BIND_IDX_INEP', `4') |
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| 62 | |||
| 63 | define(`SUB_PEL_MODE_INTEGER', `0x00000000') |
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| 64 | define(`SUB_PEL_MODE_HALF', `0x00001000') |
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| 65 | define(`SUB_PEL_MODE_QUARTER', `0x00003000') |
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| 66 | |||
| 67 | define(`INTER_SAD_NONE', `0x00000000') |
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| 68 | define(`INTER_SAD_HAAR', `0x00200000') |
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| 69 | |||
| 70 | define(`INTRA_SAD_NONE', `0x00000000') |
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| 71 | define(`INTRA_SAD_HAAR', `0x00800000') |
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| 72 | |||
| 73 | define(`INTER_PART_MASK', `0x00000000') |
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| 74 | define(`VP8_INTER_PART_MASK', `0x7e000000') |
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| 75 | |||
| 76 | define(`SEARCH_CTRL_SINGLE', `0x00000000') |
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| 77 | define(`SEARCH_CTRL_DUAL_START', `0x00000100') |
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| 78 | define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') |
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| 79 | define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') |
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| 80 | |||
| 81 | define(`REF_REGION_SIZE', `0x2830:UW') |
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| 82 | define(`MIN_REF_REGION_SIZE', `0x2020:UW') |
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| 83 | define(`DREF_REGION_SIZE', `0x2020:UW') |
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| 84 | |||
| 85 | define(`BI_SUB_MB_PART_MASK', `0x0c000000') |
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| 86 | define(`MAX_NUM_MV', `0x00000020') |
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| 87 | define(`FB_PRUNING_ENABLE', `0x40000000') |
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| 88 | |||
| 89 | define(`SEARCH_PATH_LEN', `0x00003030') |
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| 90 | define(`START_CENTER', `0x30000000') |
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| 91 | |||
| 92 | define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') |
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| 93 | define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') |
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| 94 | |||
| 95 | define(`INTRA_PLANAR_MODE_MASK', `0x10001000:UD') |
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| 96 | |||
| 97 | define(`INTER_VME_OUTPUT_IN_OWS', `10') |
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| 98 | define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') |
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| 99 | |||
| 100 | define(`INTRAMBFLAG_MASK', `0x00002000') |
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| 101 | define(`MVSIZE_UW_BASE', `0x0040') |
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| 102 | define(`MFC_MV32_BIT_SHIFT', `5') |
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| 103 | define(`CBP_DC_YUV_UW', `0x000E') |
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| 104 | |||
| 105 | define(`DC_HARR_ENABLE', `0x0000') |
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| 106 | define(`DC_HARR_DISABLE', `0x0020') |
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| 107 | |||
| 108 | define(`MV32_BIT_MASK', `0x0020') |
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| 109 | define(`MV32_BIT_SHIFT', `5') |
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| 110 | |||
| 111 | define(`OBW_CACHE_TYPE', `10') |
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| 112 | |||
| 113 | |||
| 114 | define(`OBW_MESSAGE_TYPE', `8') |
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| 115 | |||
| 116 | define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') |
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| 117 | |||
| 118 | define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ |
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| 119 | define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ |
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| 120 | define(`OBW_CONTROL_2', `2') /* 2 OWords */ |
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| 121 | define(`OBW_CONTROL_3', `3') /* 4 OWords */ |
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| 122 | define(`OBW_CONTROL_8', `4') /* 8 OWords */ |
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| 123 | |||
| 124 | define(`FBR_BME_ENABLE', `0x00000000') |
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| 125 | define(`FBR_BME_DISABLE', `0x00040000') |
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| 126 | |||
| 127 | define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ |
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| 128 | |||
| 129 | |||
| 130 | define(`OBW_HEADER_PRESENT', `1') |
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| 131 | |||
| 132 | /* GRF registers |
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| 133 | * r0 header |
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| 134 | * r1~r4 constant buffer (reserved) |
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| 135 | * r5 inline data |
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| 136 | * r6~r11 reserved |
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| 137 | * r12 write back of VME message |
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| 138 | * r13 write back of Oword Block Write |
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| 139 | */ |
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| 140 | /* |
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| 141 | * GRF 0 -- header |
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| 142 | */ |
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| 143 | define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ |
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| 144 | |||
| 145 | /* |
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| 146 | * GRF 1~4 -- Constant Buffer (reserved) |
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| 147 | */ |
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| 148 | |||
| 149 | /* |
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| 150 | * GRF 5 -- inline data |
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| 151 | */ |
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| 152 | define(`inline_reg0', `r5') |
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| 153 | define(`w_in_mb_uw', `inline_reg0.2') |
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| 154 | define(`orig_xy_ub', `inline_reg0.0') |
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| 155 | define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ |
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| 156 | define(`orig_y_ub', `inline_reg0.1') |
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| 157 | define(`transform_8x8_ub', `inline_reg0.4') |
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| 158 | define(`input_mb_intra_ub', `inline_reg0.5') |
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| 159 | define(`num_macroblocks', `inline_reg0.6') |
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| 160 | define(`quality_level_ub', `inline_reg0.7') |
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| 161 | |||
| 162 | /* |
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| 163 | * GRF 6~11 -- reserved |
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| 164 | */ |
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| 165 | |||
| 166 | /* |
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| 167 | * GRF 12~15 -- write back for VME message |
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| 168 | */ |
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| 169 | define(`vme_wb', `r12') |
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| 170 | define(`vme_wb0', `r12') |
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| 171 | define(`vme_wb1', `r13') |
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| 172 | define(`vme_wb2', `r14') |
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| 173 | define(`vme_wb3', `r15') |
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| 174 | define(`vme_wb4', `r16') |
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| 175 | define(`vme_wb5', `r17') |
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| 176 | define(`vme_wb6', `r18') |
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| 177 | define(`vme_ime_wb7', `r19') |
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| 178 | define(`vme_ime_wb8', `r20') |
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| 179 | define(`vme_ime_wb9', `r21') |
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| 180 | define(`vme_ime_wb10', `r22') |
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| 181 | |||
| 182 | |||
| 183 | /* |
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| 184 | * GRF 24 -- write for VME output message |
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| 185 | */ |
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| 186 | define(`obw_wb', `null<1>:W') |
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| 187 | define(`obw_wb_length', `0') |
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| 188 | |||
| 189 | |||
| 190 | /* |
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| 191 | * GRF 28~30 -- Intra Neighbor Edge Pixels |
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| 192 | */ |
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| 193 | define(`INEP_ROW', `r28') |
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| 194 | define(`INEP_COL0', `r29') |
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| 195 | define(`INEP_COL1', `r30') |
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| 196 | |||
| 197 | /* |
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| 198 | * GRF 48~50 -- Chroma Neighbor Edge Pixels |
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| 199 | */ |
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| 200 | define(`CHROMA_ROW', `r48') |
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| 201 | define(`CHROMA_COL', `r49') |
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| 202 | |||
| 203 | /* |
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| 204 | * temporary registers |
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| 205 | */ |
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| 206 | define(`tmp_reg0', `r32') |
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| 207 | define(`read0_header', `tmp_reg0') |
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| 208 | define(`tmp_reg1', `r33') |
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| 209 | define(`read1_header', `tmp_reg1') |
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| 210 | define(`tmp_reg2', `r34') |
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| 211 | define(`vme_m0', `tmp_reg2') |
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| 212 | define(`tmp_reg3', `r35') |
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| 213 | define(`vme_m1', `tmp_reg3') |
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| 214 | define(`intra_flag', `vme_m1.28') |
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| 215 | define(`intra_part_mask_ub', `vme_m1.28') |
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| 216 | define(`mb_intra_struct_ub', `vme_m1.29') |
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| 217 | define(`tmp_reg4', `r36') |
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| 218 | define(`obw_m0', `tmp_reg4') |
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| 219 | define(`tmp_reg5', `r37') |
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| 220 | define(`obw_m1', `tmp_reg5') |
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| 221 | define(`tmp_reg6', `r38') |
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| 222 | define(`obw_m2', `tmp_reg6') |
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| 223 | define(`tmp_reg7', `r39') |
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| 224 | define(`obw_m3', `tmp_reg7') |
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| 225 | define(`tmp_reg8', `r40') |
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| 226 | define(`obw_m4', `tmp_reg8') |
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| 227 | define(`tmp_reg9', `r41') |
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| 228 | define(`tmp_x_w', `tmp_reg9.0') |
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| 229 | define(`tmp_rega', `r42') |
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| 230 | define(`tmp_ud0', `tmp_rega.0') |
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| 231 | define(`tmp_ud1', `tmp_rega.4') |
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| 232 | define(`tmp_ud2', `tmp_rega.8') |
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| 233 | define(`tmp_ud3', `tmp_rega.12') |
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| 234 | define(`tmp_uw0', `tmp_rega.0') |
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| 235 | define(`tmp_uw1', `tmp_rega.2') |
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| 236 | define(`tmp_uw2', `tmp_rega.4') |
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| 237 | define(`tmp_uw3', `tmp_rega.6') |
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| 238 | define(`tmp_uw4', `tmp_rega.8') |
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| 239 | define(`tmp_uw5', `tmp_rega.10') |
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| 240 | define(`tmp_uw6', `tmp_rega.12') |
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| 241 | define(`tmp_uw7', `tmp_rega.14') |
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| 242 | |||
| 243 | define(`vme_m2', `r43') |
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| 244 | define(`vme_m3', `r44') |
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| 245 | /* |
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| 246 | * MRF registers |
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| 247 | */ |
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| 248 | |||
| 249 | define(`msg_ind', `64') |
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| 250 | define(`msg_reg0', `r64') |
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| 251 | define(`msg_reg1', `r65') |
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| 252 | define(`msg_reg2', `r66') |
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| 253 | define(`msg_reg3', `r67') |
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| 254 | define(`msg_reg4', `r68') |
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| 255 | define(`msg_reg5', `r69') |
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| 256 | define(`msg_reg6', `r70') |
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| 257 | define(`msg_reg7', `r71') |
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| 258 | define(`msg_reg8', `r72') |
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| 259 | define(`msg_reg9', `r73') |
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| 260 | |||
| 261 | define(`ts_msg_ind', `112') |
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| 262 | define(`ts_msg_reg0', `r112') |
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| 263 | /* |
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| 264 | * VME message payload |
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| 265 | */ |
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| 266 | |||
| 267 | define(`vme_intra_wb_length', `1') |
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| 268 | define(`vme_wb_length', `7') |
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| 269 | define(`sic_vme_msg_length', `8') |
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| 270 | define(`fbr_vme_msg_length', `8') |
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| 271 | define(`ime_vme_msg_length', `6') |
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| 272 | |||
| 273 | define(`vme_msg_ind', `msg_ind') |
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| 274 | define(`vme_msg_0', `msg_reg0') |
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| 275 | define(`vme_msg_1', `msg_reg1') |
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| 276 | define(`vme_msg_2', `msg_reg2') |
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| 277 | |||
| 278 | define(`vme_msg_3', `msg_reg3') |
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| 279 | define(`vme_msg_4', `msg_reg4') |
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| 280 | |||
| 281 | |||
| 282 | define(`vme_msg_5', `msg_reg5') |
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| 283 | define(`vme_msg_6', `msg_reg6') |
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| 284 | define(`vme_msg_7', `msg_reg7') |
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| 285 | define(`vme_msg_8', `msg_reg8') |
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| 286 | define(`vme_msg_9', `msg_reg9') |
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| 287 | |||
| 288 | define(`BIND_IDX_CBCR', `6') |
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| 289 | |||
| 290 | |||
| 291 | define(`LUMA_CHROMA_MODE', `0x0') |
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| 292 | define(`LUMA_INTRA_MODE', `0x1') |
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| 293 | define(`LUMA_INTRA_DISABLE', `0x2') |
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| 294 | |||
| 295 | define(`RETURN_REG', `r127.0') |
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| 296 | define(`RET_ARG', `r127.4') |
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| 297 | |||
| 298 | /* Now at most two registers are used for input parameter */ |
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| 299 | define(`INPUT_ARG0', `r125') |
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| 300 | define(`INPUT_ARG1', `r126') |
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| 301 | |||
| 302 | /* Two temporal registers are used in the function */ |
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| 303 | define(`TEMP_VAR0', `r123') |
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| 304 | define(`TEMP_VAR1', `r124') |
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| 305 | |||
| 306 | |||
| 307 | define(`OBR_MESSAGE_TYPE', `0') |
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| 308 | define(`OBR_CACHE_TYPE', `10') |
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| 309 | define(`OBR_BIND_IDX', `BIND_IDX_OUTPUT') |
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| 310 | |||
| 311 | define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ |
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| 312 | define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ |
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| 313 | define(`OBR_CONTROL_2', `2') /* 2 OWords */ |
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| 314 | define(`OBR_CONTROL_4', `3') /* 4 OWords */ |
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| 315 | define(`OBR_CONTROL_8', `4') /* 8 OWords */ |
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| 316 | define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on SNB+ for Data port */ |
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| 317 | define(`OBR_HEADER_PRESENT', `1') |
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| 318 | |||
| 319 | define(`mb_hwdep', `r5.6') |
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| 320 | define(`MB_AVAIL', `1:d') |
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| 321 | define(`MB_PRED_FLAG', `1:w') |
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| 322 | |||
| 323 | define(`mb_pred_mode', `r85') |
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| 324 | define(`mb_mvp_ref', `r86') |
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| 325 | define(`mba_result', `r87') |
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| 326 | define(`mbb_result', `r88') |
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| 327 | define(`mbc_result', `r89') |
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| 328 | define(`mb_ind', `90') |
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| 329 | define(`mb_msg0', `r90') |
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| 330 | define(`mb_wb', `r91') |
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| 331 | define(`mb_intra_wb', `r91') |
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| 332 | define(`mb_inter_wb', `r92') |
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| 333 | define(`mb_mv0', `r93') |
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| 334 | define(`mb_mv1', `r94') |
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| 335 | define(`mb_mv2', `r95') |
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| 336 | define(`mb_mv3', `r96') |
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| 337 | define(`mb_ref', `r97') |
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| 338 | define(`mb_ref_win', `r84') |
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| 339 | |||
| 340 | define(`PRED_L0', `0x0':uw) |
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| 341 | define(`PRED_L1', `0x1':uw) |
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| 342 | define(`PRED_BI', `0x2':uw) |
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| 343 | define(`PRED_DIRECT', `0x3':uw) |
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| 344 | define(`PRED_MASK', `0x3':uw) |
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| 345 | |||
| 346 | /* The MAX search len per reference is 16 */ |
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| 347 | define(`DSEARCH_PATH_LEN', `0x00001212') |
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| 348 | define(`BI_WEIGHT', `0x20':uw) |
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| 349 | define(`DSTART_CENTER', `0x00000000') |
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| 350 | define(`INTER_MASK', `0x03') |
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| 351 | define(`INTER_16X16MODE', `0x0') |
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| 352 | define(`INTER_16X8MODE', `0x01') |
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| 353 | define(`INTER_8X16MODE', `0x02') |
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| 354 | define(`INTER_8X8MODE', `0x03') |
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| 355 | define(`INTER_BLOCK0', `0x0') |
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| 356 | define(`INTER_BLOCK1', `0x1') |
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| 357 | define(`INTER_BLOCK2', `0x2') |
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| 358 | define(`INTER_BLOCK3', `0x3') |
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| 359 | define(`INTER_16X8MODE', `0x01') |
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| 360 | define(`INTER_8X16MODE', `0x02') |
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| 361 | |||
| 362 | |||
| 363 | define(`OBR_MESSAGE_FENCE', `7') |
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| 364 | define(`OBR_MF_NOCOMMIT', `0') |
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| 365 | define(`OBR_MF_COMMIT', `0x20') |
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| 366 | |||
| 367 | define(`DEFAULT_QUALITY_LEVEL', `0x01') |
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| 368 | define(`HIGH_QUALITY_LEVEL', `DEFAULT_QUALITY_LEVEL') |
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| 369 | define(`LOW_QUALITY_LEVEL', `0x02') |