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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 6146 | serge | 1 | /* |
| 2 | * Copyright 2000-2013 Intel Corporation All Rights Reserved |
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| 3 | * |
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
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| 5 | * you may not use this file except in compliance with the License. |
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| 6 | * You may obtain a copy of the License at |
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| 7 | * |
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
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| 9 | * |
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| 10 | * Unless required by applicable law or agreed to in writing, software |
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 13 | * See the License for the specific language governing permissions and |
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| 14 | * limitations under the License. |
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| 15 | * Authors: Zhao Yakui |
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| 16 | */ |
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| 17 | // 174 // Total instruction count |
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| 18 | // 1 // Total kernel count |
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| 19 | |||
| 20 | |||
| 21 | |||
| 22 | // Module name: common.inc |
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| 23 | // |
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| 24 | // Common header file for all Video-Processing kernels |
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| 25 | // |
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| 26 | |||
| 27 | .default_execution_size (16) |
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| 28 | .default_register_type :ub |
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| 29 | |||
| 30 | .reg_count_total 128 |
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| 31 | .reg_count_payload 7 |
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| 32 | |||
| 33 | //========== Common constants ========== |
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| 34 | |||
| 35 | |||
| 36 | //========== Macros ========== |
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| 37 | |||
| 38 | |||
| 39 | //Fast Jump, For more details see "Set_Layer_N.asm" |
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| 40 | |||
| 41 | |||
| 42 | //========== Defines ==================== |
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| 43 | |||
| 44 | //========== Static Parameters (Common To All) ========== |
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| 45 | //r1 |
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| 46 | |||
| 47 | |||
| 48 | //r2 |
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| 49 | |||
| 50 | // e.g. byte0 byte1 byte2 |
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| 51 | // YUYV 0 1 3 |
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| 52 | // YVYU 0 3 1 |
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| 53 | |||
| 54 | //Color Pipe (IECP) parameters |
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| 55 | |||
| 56 | |||
| 57 | //ByteCopy |
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| 58 | |||
| 59 | |||
| 60 | //r4 |
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| 61 | |||
| 62 | // e.g. byte0 byte1 byte2 |
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| 63 | // YUYV 0 1 3 |
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| 64 | // YVYU 0 3 1 |
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| 65 | |||
| 66 | |||
| 67 | //========== Inline parameters (Common To All) =========== |
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| 68 | |||
| 69 | |||
| 70 | //============== Binding Index Table=========== |
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| 71 | //Common between DNDI and DNUV |
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| 72 | |||
| 73 | |||
| 74 | //================= Common Message Descriptor ===== |
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| 75 | // Message descriptor for thread spawning |
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| 76 | // Message Descriptors |
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| 77 | // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) |
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| 78 | // 0000,0000,0000 |
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| 79 | // 0001(Spawn a root thread),0001 (Root thread spawn thread) |
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| 80 | // = 0x02000011 |
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| 81 | // Thread Spawner Message Descriptor |
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| 82 | |||
| 83 | |||
| 84 | // Message descriptor for atomic operation add |
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| 85 | // Message Descriptors |
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| 86 | // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) |
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| 87 | // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) |
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| 88 | // 0000,0000 (Binding table index, added later) |
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| 89 | // = 0x02000011 |
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| 90 | |||
| 91 | // Atomic Operation Add Message Descriptor |
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| 92 | |||
| 93 | |||
| 94 | // Message descriptor for dataport media write |
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| 95 | // Message Descriptors |
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| 96 | // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) |
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| 97 | // 1 (header present 1) 0 1010 (media block write) 000000 |
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| 98 | // 00000000 (binding table index - set later) |
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| 99 | // = 0x020A8000 |
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| 100 | |||
| 101 | |||
| 102 | // Message Length defines |
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| 103 | |||
| 104 | |||
| 105 | // Response Length defines |
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| 106 | |||
| 107 | |||
| 108 | // Block Width and Height Size defines |
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| 109 | |||
| 110 | |||
| 111 | // Extended Message Descriptors |
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| 112 | |||
| 113 | |||
| 114 | // Common message descriptors: |
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| 115 | |||
| 116 | |||
| 117 | //===================== Math Function Control =================================== |
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| 118 | |||
| 119 | |||
| 120 | //============ Message Registers =============== |
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| 121 | // buf4 starts from r28 |
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| 122 | |||
| 123 | |||
| 124 | //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT |
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| 125 | |||
| 126 | |||
| 127 | .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 128 | .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 129 | .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 130 | .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f |
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| 131 | |||
| 132 | //=================== End of thread instruction =========================== |
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| 133 | |||
| 134 | |||
| 135 | //=====================Pointers Used===================================== |
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| 136 | |||
| 137 | |||
| 138 | //======================================================================= |
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| 139 | |||
| 140 | |||
| 141 | //r11-r17 |
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| 142 | // Define temp space for any usages |
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| 143 | |||
| 144 | |||
| 145 | // Common Buffers |
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| 146 | |||
| 147 | |||
| 148 | // temp space for rotation |
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| 149 | |||
| 150 | .declare fROBUF Base=r11.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 151 | |||
| 152 | .declare udROBUF Base=r11.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 153 | |||
| 154 | .declare uwROBUF Base=r11.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 155 | |||
| 156 | .declare ubROBUF Base=r11.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 157 | |||
| 158 | .declare ub4ROBUF Base=r11.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 159 | |||
| 160 | |||
| 161 | // End of common.inc |
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| 162 | |||
| 163 | |||
| 164 | // Module name: Save_AVS_PA.asm |
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| 165 | // |
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| 166 | // Save PA 422 frame data block of size 16x16 |
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| 167 | // |
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| 168 | // To save 16x16 block (32x16 bytes of YUYV) we need 2 send instructions with of size 16x16 each. |
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| 169 | // ------------------------------- |
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| 170 | // | 16x16 | 16x16 | |
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| 171 | // | YUYV | YUYV | |
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| 172 | // ------------------------------- |
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| 173 | // these 2 sends are replaced by 8 32x2 sends to improve performance |
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| 174 | |||
| 175 | |||
| 176 | |||
| 177 | // Module name: Save.inc |
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| 178 | |||
| 179 | |||
| 180 | |||
| 181 | |||
| 182 | // Description: Includes all definitions explicit to Fast Composite. |
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| 183 | |||
| 184 | |||
| 185 | |||
| 186 | |||
| 187 | // End of common.inc |
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| 188 | |||
| 189 | |||
| 190 | //========== GRF partition ========== |
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| 191 | // r0 header : r0 (1 GRF) |
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| 192 | // Static parameters : r1 - r6 (6 GRFS) |
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| 193 | // Inline parameters : r7 - r8 (2 GRFs) |
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| 194 | // MSGSRC : r27 (1 GRF) |
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| 195 | //=================================== |
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| 196 | |||
| 197 | //Interface: |
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| 198 | //========== Static Parameters (Explicit To Fast Composite) ========== |
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| 199 | //r1 |
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| 200 | //CSC Set 0 |
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| 201 | |||
| 202 | |||
| 203 | .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud |
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| 204 | |||
| 205 | //Constant alpha |
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| 206 | |||
| 207 | |||
| 208 | //r2 |
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| 209 | |||
| 210 | |||
| 211 | // Gen7 AVS WA |
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| 212 | |||
| 213 | |||
| 214 | // WiDi Definitions |
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| 215 | |||
| 216 | |||
| 217 | //Colorfill |
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| 218 | |||
| 219 | |||
| 220 | // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. |
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| 221 | |||
| 222 | .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub |
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| 223 | |||
| 224 | //r3 |
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| 225 | //Normalised Ratio of Horizontal step size with main video for all layers |
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| 226 | |||
| 227 | |||
| 228 | //Normalised Ratio of Horizontal step size with main video for all layers becomes |
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| 229 | //Normalised Horizontal step size for all layers in VP_Setup.asm |
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| 230 | |||
| 231 | |||
| 232 | //r4 |
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| 233 | //Normalised Vertical step size for all layers |
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| 234 | |||
| 235 | |||
| 236 | //r5 |
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| 237 | //Normalised Vertical Frame Origin for all layers |
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| 238 | |||
| 239 | |||
| 240 | //r6 |
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| 241 | //Normalised Horizontal Frame Origin for all layers |
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| 242 | |||
| 243 | |||
| 244 | //========== Inline Parameters (Explicit To Fast Composite) ========== |
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| 245 | |||
| 246 | |||
| 247 | //Main video Step X |
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| 248 | |||
| 249 | |||
| 250 | //====================== Binding table (Explicit To Fast Composite)========================================= |
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| 251 | |||
| 252 | |||
| 253 | //Used by Interlaced Scaling Kernels |
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| 254 | |||
| 255 | |||
| 256 | //========== Sampler State Table Index (Explicit To Fast Composite)========== |
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| 257 | //Sampler Index for AVS/IEF messages |
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| 258 | |||
| 259 | |||
| 260 | //Sampler Index for SIMD16 sampler messages |
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| 261 | |||
| 262 | |||
| 263 | //============================================================================= |
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| 264 | |||
| 265 | .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 266 | .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 267 | .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 268 | .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 269 | .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 270 | .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 271 | |||
| 272 | .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 273 | .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 274 | .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 275 | .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 276 | .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 277 | .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 278 | |||
| 279 | .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 280 | .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 281 | .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 282 | .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 283 | .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 284 | .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 285 | |||
| 286 | .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 287 | .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 288 | .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 289 | .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 290 | .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 291 | .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 292 | |||
| 293 | .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 294 | .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 295 | .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 296 | .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 297 | .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 298 | .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 299 | |||
| 300 | //Pointer to mask reg |
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| 301 | |||
| 302 | |||
| 303 | //r18 |
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| 304 | |||
| 305 | |||
| 306 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 307 | // NODDCLR, NODDCHK flags. -rT |
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| 308 | |||
| 309 | |||
| 310 | .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF |
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| 311 | |||
| 312 | //r19 |
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| 313 | |||
| 314 | |||
| 315 | .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF |
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| 316 | |||
| 317 | |||
| 318 | //r20 |
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| 319 | |||
| 320 | .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 321 | |||
| 322 | //r21 |
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| 323 | |||
| 324 | .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 325 | |||
| 326 | //r22 |
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| 327 | |||
| 328 | |||
| 329 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 330 | // NODDCLR, NODDCHK flags. -rT |
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| 331 | |||
| 332 | |||
| 333 | //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as |
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| 334 | //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT |
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| 335 | |||
| 336 | //r23 |
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| 337 | |||
| 338 | |||
| 339 | //Lumakey |
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| 340 | |||
| 341 | |||
| 342 | //r24 |
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| 343 | |||
| 344 | |||
| 345 | //r25 |
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| 346 | |||
| 347 | |||
| 348 | //r26 |
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| 349 | |||
| 350 | |||
| 351 | //defines to generate LABELS during compile time. |
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| 352 | |||
| 353 | |||
| 354 | //Msg payload buffers; upto 4 full-size messages can be written |
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| 355 | |||
| 356 | |||
| 357 | .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 358 | .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 359 | .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 360 | .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 361 | |||
| 362 | .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 363 | .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 364 | .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 365 | .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 366 | |||
| 367 | .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 368 | .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 369 | .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 370 | .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 371 | .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 372 | .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 373 | .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 374 | .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 375 | |||
| 376 | |||
| 377 | // the r17 register (nTEMP0) is originally defined from "Common.inc" |
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| 378 | // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming |
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| 379 | |||
| 380 | .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw |
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| 381 | |||
| 382 | |||
| 383 | //_SAVE_INC_ |
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| 384 | |||
| 385 | |||
| 386 | //wBUFF_CHNL_PTR points to buffer 0. |
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| 387 | //Add appropriate offsets to get pointers for all buffers (1,2,3). |
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| 388 | //Offset is zero for buffer 0. |
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| 389 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw |
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| 390 | |||
| 391 | //Set DEST pointers according to output packing i.e. YUYV, YVYU, UYVY, VYUY |
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| 392 | add (4) a0.4<1>:w r2.28<4;4,1>:ub 928:uw |
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| 393 | |||
| 394 | /* X block origin. YUY2 or UYUV */ |
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| 395 | shl (1) r27.0<1>:d r9.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be 2 times |
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| 396 | mov (1) r27.1<1>:d r9.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) |
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| 397 | mov (1) r27.2<1>:ud 0x1001F:ud { NoDDChk } // Block width and height (32x2) |
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| 398 | |||
| 399 | // Rounding |
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| 400 | // left |
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| 401 | add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw |
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| 402 | add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw |
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| 403 | add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw |
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| 404 | add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw |
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| 405 | |||
| 406 | add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw |
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| 407 | add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw |
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| 408 | add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw |
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| 409 | add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw |
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| 410 | |||
| 411 | add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw |
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| 412 | add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw |
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| 413 | add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw |
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| 414 | add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw |
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| 415 | |||
| 416 | // right |
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| 417 | add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw |
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| 418 | add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw |
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| 419 | add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw |
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| 420 | add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw |
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| 421 | |||
| 422 | add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw |
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| 423 | add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw |
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| 424 | add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw |
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| 425 | add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw |
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| 426 | |||
| 427 | add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw |
||
| 428 | add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw |
||
| 429 | add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw |
||
| 430 | add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw |
||
| 431 | |||
| 432 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 512:uw |
||
| 433 | // left |
||
| 434 | add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw |
||
| 435 | add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw |
||
| 436 | add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw |
||
| 437 | add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw |
||
| 438 | |||
| 439 | add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw |
||
| 440 | add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw |
||
| 441 | add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw |
||
| 442 | add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw |
||
| 443 | |||
| 444 | add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw |
||
| 445 | add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw |
||
| 446 | add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw |
||
| 447 | add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw |
||
| 448 | |||
| 449 | // right |
||
| 450 | add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw |
||
| 451 | add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw |
||
| 452 | add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw |
||
| 453 | add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw |
||
| 454 | |||
| 455 | add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw |
||
| 456 | add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw |
||
| 457 | add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw |
||
| 458 | add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw |
||
| 459 | |||
| 460 | add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw |
||
| 461 | add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw |
||
| 462 | add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw |
||
| 463 | add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw |
||
| 464 | |||
| 465 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw |
||
| 466 | // left |
||
| 467 | add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw |
||
| 468 | add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw |
||
| 469 | add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw |
||
| 470 | add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw |
||
| 471 | |||
| 472 | add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw |
||
| 473 | add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw |
||
| 474 | add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw |
||
| 475 | add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw |
||
| 476 | |||
| 477 | add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw |
||
| 478 | add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw |
||
| 479 | add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw |
||
| 480 | add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw |
||
| 481 | |||
| 482 | // right |
||
| 483 | add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw |
||
| 484 | add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw |
||
| 485 | add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw |
||
| 486 | add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw |
||
| 487 | |||
| 488 | add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw |
||
| 489 | add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw |
||
| 490 | add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw |
||
| 491 | add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw |
||
| 492 | |||
| 493 | add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw |
||
| 494 | add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw |
||
| 495 | add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw |
||
| 496 | add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw |
||
| 497 | |||
| 498 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 1536:uw |
||
| 499 | // left |
||
| 500 | add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw |
||
| 501 | add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw |
||
| 502 | add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw |
||
| 503 | add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw |
||
| 504 | |||
| 505 | add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw |
||
| 506 | add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw |
||
| 507 | add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw |
||
| 508 | add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw |
||
| 509 | |||
| 510 | add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw |
||
| 511 | add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw |
||
| 512 | add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw |
||
| 513 | add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw |
||
| 514 | |||
| 515 | // right |
||
| 516 | add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw |
||
| 517 | add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw |
||
| 518 | add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw |
||
| 519 | add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw |
||
| 520 | |||
| 521 | add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw |
||
| 522 | add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw |
||
| 523 | add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw |
||
| 524 | add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw |
||
| 525 | |||
| 526 | add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw |
||
| 527 | add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw |
||
| 528 | add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw |
||
| 529 | add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw |
||
| 530 | |||
| 531 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 2048:uw |
||
| 532 | // restore pointer |
||
| 533 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw |
||
| 534 | |||
| 535 | mov (8) r28<1>:ud r27<8;8,1>:ud |
||
| 536 | mov (8) r37<1>:ud r27<8;8,1>:ud |
||
| 537 | add (1) r37.1<1>:d r27.1<0;1,0>:d 2:d // Point to 2nd part |
||
| 538 | |||
| 539 | /* a0.2 U, a0.1 Y, a0.0 V */ |
||
| 540 | |||
| 541 | mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } |
||
| 542 | mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } |
||
| 543 | mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 544 | mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 545 | mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } |
||
| 546 | mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } |
||
| 547 | |||
| 548 | /* a0.4 + 288 = r38 */ |
||
| 549 | mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } |
||
| 550 | mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } |
||
| 551 | mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 552 | mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 553 | mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } |
||
| 554 | mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } |
||
| 555 | |||
| 556 | send (1) null<1>:d r28 0xc 0x60A8018:ud |
||
| 557 | send (1) null<1>:d r37 0xc 0x60A8018:ud |
||
| 558 | |||
| 559 | // restore pointer |
||
| 560 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 512:uw |
||
| 561 | |||
| 562 | add (1) r28.1<1>:d r27.1<0;1,0>:d 4:d // Point to 2nd part |
||
| 563 | add (1) r37.1<1>:d r27.1<0;1,0>:d 6:d // Point to 2nd part |
||
| 564 | |||
| 565 | |||
| 566 | mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } |
||
| 567 | mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } |
||
| 568 | mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 569 | mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 570 | mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } |
||
| 571 | mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } |
||
| 572 | |||
| 573 | mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } |
||
| 574 | mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } |
||
| 575 | mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 576 | mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 577 | mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } |
||
| 578 | mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } |
||
| 579 | |||
| 580 | send (1) null<1>:d r28 0xc 0x60A8018:ud |
||
| 581 | send (1) null<1>:d r37 0xc 0x60A8018:ud |
||
| 582 | |||
| 583 | // restore pointer |
||
| 584 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw |
||
| 585 | |||
| 586 | add (1) r28.1<1>:d r27.1<0;1,0>:d 8:d // Point to 2nd part |
||
| 587 | add (1) r37.1<1>:d r27.1<0;1,0>:d 10:d // Point to 2nd part |
||
| 588 | |||
| 589 | |||
| 590 | mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } |
||
| 591 | mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } |
||
| 592 | mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 593 | mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 594 | mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } |
||
| 595 | mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } |
||
| 596 | |||
| 597 | mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } |
||
| 598 | mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } |
||
| 599 | mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 600 | mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 601 | mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } |
||
| 602 | mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } |
||
| 603 | |||
| 604 | send (1) null<1>:d r28 0xc 0x60A8018:ud |
||
| 605 | send (1) null<1>:d r37 0xc 0x60A8018:ud |
||
| 606 | |||
| 607 | // restore pointer |
||
| 608 | add (4) a0.0<1>:uw r22.0<4;4,1>:w 1536:uw |
||
| 609 | |||
| 610 | add (1) r28.1<1>:d r27.1<0;1,0>:d 12:d // Point to 2nd part |
||
| 611 | add (1) r37.1<1>:d r27.1<0;1,0>:d 14:d // Point to 2nd part |
||
| 612 | |||
| 613 | mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } |
||
| 614 | mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } |
||
| 615 | mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 616 | mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 617 | mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } |
||
| 618 | mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } |
||
| 619 | |||
| 620 | mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } |
||
| 621 | mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } |
||
| 622 | mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 623 | mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } |
||
| 624 | mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } |
||
| 625 | mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } |
||
| 626 | |||
| 627 | send (1) null<1>:d r28 0xc 0x60A8018:ud |
||
| 628 | send (1) null<1>:d r37 0xc 0x60A8018:ud |
||
| 629 |