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| 6146 | serge | 1 | /* |
| 2 | * Copyright 2000-2011 Intel Corporation All Rights Reserved |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the |
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| 6 | * "Software"), to deal in the Software without restriction, including |
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| 7 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 8 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 9 | * permit persons to whom the Software is furnished to do so, subject to |
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| 10 | * the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice (including the |
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| 13 | * next paragraph) shall be included in all copies or substantial portions |
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| 14 | * of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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| 19 | * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
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| 20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * This file was originally licensed under the following license |
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| 25 | * |
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| 26 | * Licensed under the Apache License, Version 2.0 (the "License"); |
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| 27 | * you may not use this file except in compliance with the License. |
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| 28 | * You may obtain a copy of the License at |
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| 29 | * |
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| 30 | * http://www.apache.org/licenses/LICENSE-2.0 |
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| 31 | * |
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| 32 | * Unless required by applicable law or agreed to in writing, software |
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| 33 | * distributed under the License is distributed on an "AS IS" BASIS, |
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| 34 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 35 | * See the License for the specific language governing permissions and |
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| 36 | * limitations under the License. |
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| 37 | */ |
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| 38 | // 7 // Total instruction count |
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| 39 | // 1 // Total kernel count |
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| 40 | |||
| 41 | |||
| 42 | |||
| 43 | // Module name: common.inc |
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| 44 | // |
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| 45 | // Common header file for all Video-Processing kernels |
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| 46 | // |
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| 47 | |||
| 48 | .default_execution_size (16) |
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| 49 | .default_register_type :ub |
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| 50 | |||
| 51 | .reg_count_total 128 |
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| 52 | .reg_count_payload 7 |
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| 53 | |||
| 54 | //========== Common constants ========== |
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| 55 | |||
| 56 | |||
| 57 | //========== Macros ========== |
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| 58 | |||
| 59 | |||
| 60 | //Fast Jump, For more details see "Set_Layer_N.asm" |
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| 61 | |||
| 62 | |||
| 63 | //========== Defines ==================== |
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| 64 | |||
| 65 | //========== Static Parameters (Common To All) ========== |
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| 66 | //r1 |
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| 67 | |||
| 68 | |||
| 69 | //r2 |
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| 70 | |||
| 71 | // e.g. byte0 byte1 byte2 |
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| 72 | // YUYV 0 1 3 |
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| 73 | // YVYU 0 3 1 |
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| 74 | |||
| 75 | //Color Pipe (IECP) parameters |
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| 76 | |||
| 77 | |||
| 78 | //ByteCopy |
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| 79 | |||
| 80 | |||
| 81 | //r4 |
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| 82 | |||
| 83 | // e.g. byte0 byte1 byte2 |
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| 84 | // YUYV 0 1 3 |
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| 85 | // YVYU 0 3 1 |
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| 86 | |||
| 87 | |||
| 88 | //========== Inline parameters (Common To All) =========== |
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| 89 | |||
| 90 | |||
| 91 | //============== Binding Index Table=========== |
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| 92 | //Common between DNDI and DNUV |
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| 93 | |||
| 94 | |||
| 95 | //================= Common Message Descriptor ===== |
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| 96 | // Message descriptor for thread spawning |
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| 97 | // Message Descriptors |
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| 98 | // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) |
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| 99 | // 0000,0000,0000 |
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| 100 | // 0001(Spawn a root thread),0001 (Root thread spawn thread) |
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| 101 | // = 0x02000011 |
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| 102 | // Thread Spawner Message Descriptor |
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| 103 | |||
| 104 | |||
| 105 | // Message descriptor for atomic operation add |
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| 106 | // Message Descriptors |
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| 107 | // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) |
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| 108 | // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) |
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| 109 | // 0000,0000 (Binding table index, added later) |
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| 110 | // = 0x02000011 |
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| 111 | |||
| 112 | // Atomic Operation Add Message Descriptor |
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| 113 | |||
| 114 | |||
| 115 | // Message descriptor for dataport media write |
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| 116 | // Message Descriptors |
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| 117 | // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) |
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| 118 | // 1 (header present 1) 0 1010 (media block write) 000000 |
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| 119 | // 00000000 (binding table index - set later) |
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| 120 | // = 0x020A8000 |
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| 121 | |||
| 122 | |||
| 123 | // Message Length defines |
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| 124 | |||
| 125 | |||
| 126 | // Response Length defines |
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| 127 | |||
| 128 | |||
| 129 | // Block Width and Height Size defines |
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| 130 | |||
| 131 | |||
| 132 | // Extended Message Descriptors |
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| 133 | |||
| 134 | |||
| 135 | // Common message descriptors: |
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| 136 | |||
| 137 | |||
| 138 | //===================== Math Function Control =================================== |
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| 139 | |||
| 140 | |||
| 141 | //============ Message Registers =============== |
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| 142 | // buf4 starts from r28 |
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| 143 | |||
| 144 | |||
| 145 | //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT |
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| 146 | |||
| 147 | |||
| 148 | .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 149 | .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 150 | .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 151 | .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f |
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| 152 | |||
| 153 | //=================== End of thread instruction =========================== |
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| 154 | |||
| 155 | |||
| 156 | //=====================Pointers Used===================================== |
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| 157 | |||
| 158 | |||
| 159 | //======================================================================= |
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| 160 | |||
| 161 | |||
| 162 | //r11-r17 |
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| 163 | // Define temp space for any usages |
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| 164 | |||
| 165 | |||
| 166 | // Common Buffers |
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| 167 | |||
| 168 | |||
| 169 | // temp space for rotation |
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| 170 | |||
| 171 | .declare fROBUF Base=r11.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 172 | |||
| 173 | .declare udROBUF Base=r11.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 174 | |||
| 175 | .declare uwROBUF Base=r11.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 176 | |||
| 177 | .declare ubROBUF Base=r11.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 178 | |||
| 179 | .declare ub4ROBUF Base=r11.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 180 | |||
| 181 | |||
| 182 | // End of common.inc |
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| 183 | |||
| 184 | |||
| 185 | //Module Name: Set_AVS_Buf_0123_YUVA.asm |
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| 186 | |||
| 187 | |||
| 188 | |||
| 189 | // Module Name : Set_Buf_0123_VUYA |
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| 190 | |||
| 191 | |||
| 192 | |||
| 193 | |||
| 194 | // Description: Includes all definitions explicit to Fast Composite. |
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| 195 | |||
| 196 | |||
| 197 | |||
| 198 | |||
| 199 | // End of common.inc |
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| 200 | |||
| 201 | |||
| 202 | //========== GRF partition ========== |
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| 203 | // r0 header : r0 (1 GRF) |
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| 204 | // Static parameters : r1 - r6 (6 GRFS) |
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| 205 | // Inline parameters : r7 - r8 (2 GRFs) |
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| 206 | // MSGSRC : r27 (1 GRF) |
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| 207 | //=================================== |
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| 208 | |||
| 209 | //Interface: |
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| 210 | //========== Static Parameters (Explicit To Fast Composite) ========== |
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| 211 | //r1 |
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| 212 | //CSC Set 0 |
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| 213 | |||
| 214 | |||
| 215 | .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud |
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| 216 | |||
| 217 | //Constant alpha |
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| 218 | |||
| 219 | |||
| 220 | //r2 |
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| 221 | |||
| 222 | |||
| 223 | // Gen7 AVS WA |
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| 224 | |||
| 225 | |||
| 226 | // WiDi Definitions |
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| 227 | |||
| 228 | |||
| 229 | //Colorfill |
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| 230 | |||
| 231 | |||
| 232 | // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. |
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| 233 | |||
| 234 | .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub |
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| 235 | |||
| 236 | //r3 |
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| 237 | //Normalised Ratio of Horizontal step size with main video for all layers |
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| 238 | |||
| 239 | |||
| 240 | //Normalised Ratio of Horizontal step size with main video for all layers becomes |
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| 241 | //Normalised Horizontal step size for all layers in VP_Setup.asm |
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| 242 | |||
| 243 | |||
| 244 | //r4 |
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| 245 | //Normalised Vertical step size for all layers |
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| 246 | |||
| 247 | |||
| 248 | //r5 |
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| 249 | //Normalised Vertical Frame Origin for all layers |
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| 250 | |||
| 251 | |||
| 252 | //r6 |
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| 253 | //Normalised Horizontal Frame Origin for all layers |
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| 254 | |||
| 255 | |||
| 256 | //========== Inline Parameters (Explicit To Fast Composite) ========== |
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| 257 | |||
| 258 | |||
| 259 | //Main video Step X |
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| 260 | |||
| 261 | |||
| 262 | //====================== Binding table (Explicit To Fast Composite)========================================= |
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| 263 | |||
| 264 | |||
| 265 | //Used by Interlaced Scaling Kernels |
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| 266 | |||
| 267 | |||
| 268 | //========== Sampler State Table Index (Explicit To Fast Composite)========== |
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| 269 | //Sampler Index for AVS/IEF messages |
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| 270 | |||
| 271 | |||
| 272 | //Sampler Index for SIMD16 sampler messages |
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| 273 | |||
| 274 | |||
| 275 | //============================================================================= |
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| 276 | |||
| 277 | .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 278 | .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 279 | .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 280 | .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 281 | .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 282 | .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 283 | |||
| 284 | .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 285 | .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 286 | .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 287 | .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 288 | .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 289 | .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 290 | |||
| 291 | .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 292 | .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 293 | .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 294 | .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 295 | .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 296 | .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 297 | |||
| 298 | .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 299 | .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 300 | .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 301 | .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 302 | .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 303 | .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 304 | |||
| 305 | .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 306 | .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 307 | .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 308 | .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 309 | .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 310 | .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 311 | |||
| 312 | //Pointer to mask reg |
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| 313 | |||
| 314 | |||
| 315 | //r18 |
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| 316 | |||
| 317 | |||
| 318 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 319 | // NODDCLR, NODDCHK flags. -rT |
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| 320 | |||
| 321 | |||
| 322 | .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF |
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| 323 | |||
| 324 | //r19 |
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| 325 | |||
| 326 | |||
| 327 | .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF |
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| 328 | |||
| 329 | |||
| 330 | //r20 |
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| 331 | |||
| 332 | .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 333 | |||
| 334 | //r21 |
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| 335 | |||
| 336 | .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 337 | |||
| 338 | //r22 |
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| 339 | |||
| 340 | |||
| 341 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 342 | // NODDCLR, NODDCHK flags. -rT |
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| 343 | |||
| 344 | |||
| 345 | //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as |
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| 346 | //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT |
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| 347 | |||
| 348 | //r23 |
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| 349 | |||
| 350 | |||
| 351 | //Lumakey |
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| 352 | |||
| 353 | |||
| 354 | //r24 |
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| 355 | |||
| 356 | |||
| 357 | //r25 |
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| 358 | |||
| 359 | |||
| 360 | //r26 |
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| 361 | |||
| 362 | |||
| 363 | //defines to generate LABELS during compile time. |
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| 364 | |||
| 365 | |||
| 366 | //For AVS: We use surface state as R8G8B8A8_UNORM and hence set pointers to VUYA. |
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| 367 | //AVS LAYOUT:(VVUUYYAA) |
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| 368 | //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V |
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| 369 | //V = 0, Y= 8, U = 4, A = 12. |
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| 370 | mov (4) acc0.0<1>:w 0x6E2A:v |
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| 371 | add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw |
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| 372 | shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw |
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| 373 | |||
| 374 | //Used by Shuffle. |
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| 375 | //SU LAYOUT:(VUYAVUYA) |
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| 376 | //V = 0, Y = 4, U = 2, A = 6 |
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| 377 | mov (4) acc0.0<1>:w 0x6240:v |
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| 378 | add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw |
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| 379 | shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. |
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| 380 | |||
| 381 | //OFFSET: |
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| 382 | mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } |
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| 383 |