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| 6146 | serge | 1 | /* |
| 2 | * All Video Processing kernels |
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| 3 | * Copyright © <2010>, Intel Corporation. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice (including the |
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| 14 | * next paragraph) shall be included in all copies or substantial portions |
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| 15 | * of the Software. |
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| 16 | * |
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| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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| 20 | * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
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| 21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 24 | * |
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| 25 | * This file was originally licensed under the following license |
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| 26 | * |
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| 27 | * Licensed under the Apache License, Version 2.0 (the "License"); |
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| 28 | * you may not use this file except in compliance with the License. |
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| 29 | * You may obtain a copy of the License at |
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| 30 | * |
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| 31 | * http://www.apache.org/licenses/LICENSE-2.0 |
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| 32 | * |
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| 33 | * Unless required by applicable law or agreed to in writing, software |
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| 34 | * distributed under the License is distributed on an "AS IS" BASIS, |
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| 35 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 36 | * See the License for the specific language governing permissions and |
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| 37 | * limitations under the License. |
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| 38 | * |
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| 39 | */ |
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| 40 | |||
| 41 | // Module name: IMC3_Load_9x5.asm |
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| 42 | // |
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| 43 | //---------------------------------------------------------------- |
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| 44 | // This module loads 16x8 Y, 9x5 U and 9x5 V planar data blocks for CSC module |
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| 45 | // and stores it in byte-aligned format. |
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| 46 | //---------------------------------------------------------------- |
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| 47 | |||
| 48 | #define IMC3_LOAD_9x5 |
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| 49 | #include "PL3_Load.inc" |
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| 50 | |||
| 51 | // Load 16x8 planar Y ---------------------------------------------------------- |
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| 52 | add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin |
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| 53 | #if !defined(LOAD_UV_ONLY) |
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| 54 | mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Block width and height (16x8) |
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| 55 | |||
| 56 | mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud |
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| 57 | send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud |
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| 58 | #endif |
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| 59 | |||
| 60 | // Load 9x5 planar U and V ----------------------------------------------------- |
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| 61 | asr (2) rMSGSRC.0<1>:d rMSGSRC.0<2;2,1>:d 1:w // U/V block origin should be half of Y's |
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| 62 | mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (12x5) |
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| 63 | |||
| 64 | mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud |
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| 65 | send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_U:ud |
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| 66 | mov (8) mMSGHDRV<1>:ud rMSGSRC<8;8,1>:ud |
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| 67 | send (8) udSRC_V(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_V:ud |
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| 68 | |||
| 69 | // Convert to word-aligned format ---------------------------------------------- |
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| 70 | #if !defined(LOAD_UV_ONLY) |
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| 71 | $for (nY_NUM_OF_ROWS-1; >-1; -1) { |
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| 72 | mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) |
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| 73 | } |
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| 74 | #endif |
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| 75 | $for(nUV_NUM_OF_ROWS-2; >-1; -1) { |
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| 76 | mov (16) uwDEST_U(0, %1*16)<1> ubSRC_U(0, %1*16) |
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| 77 | mov (16) uwDEST_V(0, %1*16)<1> ubSRC_V(0, %1*16) |
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| 78 | } |
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| 79 | |||
| 80 | // End of IMC3_Load_9x5 |