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5361 serge 1
/*
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 * Copyright © <2010>, Intel Corporation.
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 *
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 * This program is licensed under the terms and conditions of the
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 * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
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 * http://www.opensource.org/licenses/eclipse-1.0.php.
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 *
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 */
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//=============== Spawn a child thread for Luma or Chroma ===============
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	//----- Create child thread R0 header -----
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#if defined(_DEBUG)
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	mov		(1)		EntrySignature:w			0xAAAA:w
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#endif
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	//***** Set CT_R0Hdr fields that change for every thread
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	// Restore CT_R0Hdr.4:ud to r0.4:ud
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	mov (1) CT_R0Hdr.4:ud		r0.4:ud
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	// R0.2: Interface Discriptor Ptr.  Add a child offset for child kernel
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//	add (1) CT_R0Hdr.2:ud 		r0.2:ud 		CHILD_OFFSET:w
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	// Assign a new Thread Count for this child
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	mov (1) CT_R0Hdr.6:ud 		ChildThreadsID:uw
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	//----- Prepare URB for launching a child thread -----
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	mov (16) m2.0:w		ChildParam<16;16,1>:w
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	shr (1)	 MRF0.0:uw	URBOffset:uw	1:w
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	add	(1)	ChildThreadsID:uw		ChildThreadsID:uw	2:uw	// Luma child=even, chroma child=odd
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	//--------------------------------------------------
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//	#include "writeURB.asm"
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	send  null:uw 	MRF0	 null:ud	URBWRITE	URBWriteMsgDesc:ud		// URB write
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	//--------------------------------------------------
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	// Set URB handle for child thread launching:
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	// URB handle Length	 	(bit 15:10) - 0000 0000 0000 0000  yyyy yy00 0000 0000
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	// URB handle offset  		(bit 9:0) 	- 0000 0000 0000 0000  0000 00xx xxxx xxxx
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	or  (1) CT_R0Hdr.4:ud		URB_EntriesPerMB_2:w	URBOffset:uw
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	// 2 URB entries:
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	// Entry 0 - CT_R0Hdr
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	// Entry 1 - input parameter to child kernel
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	//----- Spawn a child now -----
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	send (8) null:ud 	CT_R0Hdr	  null:ud    TS	TSMSGDSC
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//	send (8) null:ud 	CT_Spawn_Reg	null:ud    0x07100001
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	// Restore CT_R0Hdr.4:ud to r0.4:ud for next use
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//	mov (1) CT_R0Hdr.4:ud		r0.4:ud