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4363 | Serge | 1 | /* |
2 | * |
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3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | */ |
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27 | |||
28 | #ifndef _INTEL_CHIPSET_H |
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29 | #define _INTEL_CHIPSET_H |
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30 | |||
31 | #define PCI_CHIP_I810 0x7121 |
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32 | #define PCI_CHIP_I810_DC100 0x7123 |
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33 | #define PCI_CHIP_I810_E 0x7125 |
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34 | #define PCI_CHIP_I815 0x1132 |
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35 | |||
36 | #define PCI_CHIP_I830_M 0x3577 |
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37 | #define PCI_CHIP_845_G 0x2562 |
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38 | #define PCI_CHIP_I855_GM 0x3582 |
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39 | #define PCI_CHIP_I865_G 0x2572 |
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40 | |||
41 | #define PCI_CHIP_I915_G 0x2582 |
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42 | #define PCI_CHIP_E7221_G 0x258A |
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43 | #define PCI_CHIP_I915_GM 0x2592 |
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44 | #define PCI_CHIP_I945_G 0x2772 |
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45 | #define PCI_CHIP_I945_GM 0x27A2 |
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46 | #define PCI_CHIP_I945_GME 0x27AE |
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47 | |||
48 | #define PCI_CHIP_Q35_G 0x29B2 |
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49 | #define PCI_CHIP_G33_G 0x29C2 |
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50 | #define PCI_CHIP_Q33_G 0x29D2 |
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51 | |||
52 | #define PCI_CHIP_IGD_GM 0xA011 |
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53 | #define PCI_CHIP_IGD_G 0xA001 |
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54 | |||
55 | #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) |
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56 | #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) |
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57 | #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) |
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58 | |||
59 | #define PCI_CHIP_I965_G 0x29A2 |
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60 | #define PCI_CHIP_I965_Q 0x2992 |
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61 | #define PCI_CHIP_I965_G_1 0x2982 |
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62 | #define PCI_CHIP_I946_GZ 0x2972 |
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63 | #define PCI_CHIP_I965_GM 0x2A02 |
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64 | #define PCI_CHIP_I965_GME 0x2A12 |
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65 | |||
66 | #define PCI_CHIP_GM45_GM 0x2A42 |
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67 | |||
68 | #define PCI_CHIP_IGD_E_G 0x2E02 |
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69 | #define PCI_CHIP_Q45_G 0x2E12 |
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70 | #define PCI_CHIP_G45_G 0x2E22 |
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71 | #define PCI_CHIP_G41_G 0x2E32 |
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72 | |||
73 | #define PCI_CHIP_ILD_G 0x0042 |
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74 | #define PCI_CHIP_ILM_G 0x0046 |
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75 | |||
76 | #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ |
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77 | #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 |
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78 | #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 |
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79 | #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ |
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80 | #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 |
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81 | #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 |
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82 | #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ |
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83 | |||
84 | #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ |
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85 | #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 |
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86 | #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ |
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87 | #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 |
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88 | #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ |
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89 | #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ |
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90 | |||
91 | #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ |
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92 | #define PCI_CHIP_HASWELL_GT2 0x0412 |
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93 | #define PCI_CHIP_HASWELL_GT3 0x0422 |
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94 | #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ |
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95 | #define PCI_CHIP_HASWELL_M_GT2 0x0416 |
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96 | #define PCI_CHIP_HASWELL_M_GT3 0x0426 |
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97 | #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ |
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98 | #define PCI_CHIP_HASWELL_S_GT2 0x041A |
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99 | #define PCI_CHIP_HASWELL_S_GT3 0x042A |
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100 | #define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ |
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101 | #define PCI_CHIP_HASWELL_B_GT2 0x041B |
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102 | #define PCI_CHIP_HASWELL_B_GT3 0x042B |
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103 | #define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ |
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104 | #define PCI_CHIP_HASWELL_E_GT2 0x041E |
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105 | #define PCI_CHIP_HASWELL_E_GT3 0x042E |
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106 | #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ |
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107 | #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 |
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108 | #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 |
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109 | #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ |
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110 | #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 |
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111 | #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 |
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112 | #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ |
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113 | #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A |
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114 | #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A |
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115 | #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ |
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116 | #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B |
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117 | #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B |
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118 | #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ |
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119 | #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E |
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120 | #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E |
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121 | #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ |
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122 | #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 |
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123 | #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 |
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124 | #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ |
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125 | #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 |
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126 | #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 |
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127 | #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ |
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128 | #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A |
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129 | #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A |
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130 | #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ |
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131 | #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B |
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132 | #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B |
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133 | #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ |
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134 | #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E |
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135 | #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E |
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136 | #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ |
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137 | #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 |
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138 | #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 |
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139 | #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ |
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140 | #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 |
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141 | #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 |
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142 | #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ |
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143 | #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A |
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144 | #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A |
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145 | #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ |
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146 | #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B |
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147 | #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B |
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148 | #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ |
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149 | #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E |
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150 | #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E |
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151 | #define BDW_SPARE 0x2 |
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152 | #define BDW_ULT 0x6 |
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153 | #define BDW_SERVER 0xa |
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154 | #define BDW_IRIS 0xb |
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155 | #define BDW_WORKSTATION 0xd |
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156 | #define BDW_ULX 0xe |
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157 | |||
158 | #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ |
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159 | #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |
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160 | #define PCI_CHIP_VALLEYVIEW_2 0x0f32 |
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161 | #define PCI_CHIP_VALLEYVIEW_3 0x0f33 |
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162 | |||
5068 | serge | 163 | #define PCI_CHIP_CHERRYVIEW_0 0x22b0 |
164 | #define PCI_CHIP_CHERRYVIEW_1 0x22b1 |
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165 | #define PCI_CHIP_CHERRYVIEW_2 0x22b2 |
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166 | #define PCI_CHIP_CHERRYVIEW_3 0x22b3 |
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167 | |||
4363 | Serge | 168 | #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ |
169 | (devid) == PCI_CHIP_I915_GM || \ |
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170 | (devid) == PCI_CHIP_I945_GM || \ |
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171 | (devid) == PCI_CHIP_I945_GME || \ |
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172 | (devid) == PCI_CHIP_I965_GM || \ |
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173 | (devid) == PCI_CHIP_I965_GME || \ |
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174 | (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ |
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175 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ |
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176 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT2) |
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177 | |||
178 | #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ |
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179 | (devid) == PCI_CHIP_Q45_G || \ |
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180 | (devid) == PCI_CHIP_G45_G || \ |
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181 | (devid) == PCI_CHIP_G41_G) |
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182 | #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) |
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183 | #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) |
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184 | |||
185 | #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) |
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186 | #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) |
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187 | |||
188 | #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ |
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189 | (devid) == PCI_CHIP_E7221_G || \ |
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190 | (devid) == PCI_CHIP_I915_GM) |
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191 | |||
192 | #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ |
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193 | (devid) == PCI_CHIP_I945_GME) |
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194 | |||
195 | #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ |
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196 | (devid) == PCI_CHIP_I945_GM || \ |
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197 | (devid) == PCI_CHIP_I945_GME || \ |
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198 | IS_G33(devid)) |
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199 | |||
200 | #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ |
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201 | (devid) == PCI_CHIP_Q33_G || \ |
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202 | (devid) == PCI_CHIP_Q35_G || IS_IGD(devid)) |
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203 | |||
204 | #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ |
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205 | (devid) == PCI_CHIP_845_G || \ |
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206 | (devid) == PCI_CHIP_I855_GM || \ |
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207 | (devid) == PCI_CHIP_I865_G) |
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208 | |||
209 | #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) |
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210 | |||
211 | #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ |
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212 | (devid) == PCI_CHIP_I965_Q || \ |
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213 | (devid) == PCI_CHIP_I965_G_1 || \ |
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214 | (devid) == PCI_CHIP_I965_GM || \ |
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215 | (devid) == PCI_CHIP_I965_GME || \ |
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216 | (devid) == PCI_CHIP_I946_GZ || \ |
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217 | IS_G4X(devid)) |
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218 | |||
219 | #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) |
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220 | |||
221 | #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ |
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222 | (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \ |
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223 | (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ |
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224 | (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ |
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225 | (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ |
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226 | (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ |
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227 | (devid) == PCI_CHIP_SANDYBRIDGE_S) |
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228 | |||
229 | #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ |
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230 | IS_HASWELL(devid) || \ |
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231 | IS_VALLEYVIEW(devid)) |
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232 | |||
233 | #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ |
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234 | (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ |
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235 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ |
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236 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ |
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237 | (devid) == PCI_CHIP_IVYBRIDGE_S || \ |
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238 | (devid) == PCI_CHIP_IVYBRIDGE_S_GT2) |
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239 | |||
240 | #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ |
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241 | (devid) == PCI_CHIP_VALLEYVIEW_1 || \ |
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242 | (devid) == PCI_CHIP_VALLEYVIEW_2 || \ |
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243 | (devid) == PCI_CHIP_VALLEYVIEW_3) |
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244 | |||
245 | #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ |
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246 | (devid) == PCI_CHIP_HASWELL_M_GT1 || \ |
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247 | (devid) == PCI_CHIP_HASWELL_S_GT1 || \ |
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248 | (devid) == PCI_CHIP_HASWELL_B_GT1 || \ |
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249 | (devid) == PCI_CHIP_HASWELL_E_GT1 || \ |
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250 | (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ |
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251 | (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ |
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252 | (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ |
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253 | (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ |
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254 | (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ |
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255 | (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ |
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256 | (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ |
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257 | (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ |
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258 | (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ |
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259 | (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ |
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260 | (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ |
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261 | (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ |
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262 | (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ |
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263 | (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ |
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264 | (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) |
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265 | #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ |
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266 | (devid) == PCI_CHIP_HASWELL_M_GT2 || \ |
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267 | (devid) == PCI_CHIP_HASWELL_S_GT2 || \ |
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268 | (devid) == PCI_CHIP_HASWELL_B_GT2 || \ |
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269 | (devid) == PCI_CHIP_HASWELL_E_GT2 || \ |
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270 | (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ |
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271 | (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ |
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272 | (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ |
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273 | (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ |
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274 | (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ |
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275 | (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ |
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276 | (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ |
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277 | (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ |
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278 | (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ |
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279 | (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ |
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280 | (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ |
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281 | (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ |
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282 | (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ |
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283 | (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ |
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284 | (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) |
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285 | #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ |
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286 | (devid) == PCI_CHIP_HASWELL_M_GT3 || \ |
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287 | (devid) == PCI_CHIP_HASWELL_S_GT3 || \ |
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288 | (devid) == PCI_CHIP_HASWELL_B_GT3 || \ |
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289 | (devid) == PCI_CHIP_HASWELL_E_GT3 || \ |
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290 | (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ |
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291 | (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ |
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292 | (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ |
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293 | (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ |
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294 | (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ |
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295 | (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ |
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296 | (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ |
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297 | (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ |
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298 | (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ |
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299 | (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ |
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300 | (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ |
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301 | (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ |
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302 | (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ |
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303 | (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ |
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304 | (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) |
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305 | |||
306 | #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ |
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307 | IS_HSW_GT2(devid) || \ |
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308 | IS_HSW_GT3(devid)) |
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309 | |||
310 | #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ |
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311 | (((devid & 0x00f0) >> 4) > 3) ? 0 : \ |
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312 | ((devid & 0x000f) == BDW_SPARE) ? 1 : \ |
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313 | ((devid & 0x000f) == BDW_ULT) ? 1 : \ |
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314 | ((devid & 0x000f) == BDW_IRIS) ? 1 : \ |
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315 | ((devid & 0x000f) == BDW_SERVER) ? 1 : \ |
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316 | ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \ |
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317 | ((devid & 0x000f) == BDW_ULX) ? 1 : 0) |
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318 | |||
5068 | serge | 319 | #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ |
320 | (devid) == PCI_CHIP_CHERRYVIEW_1 || \ |
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321 | (devid) == PCI_CHIP_CHERRYVIEW_2 || \ |
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322 | (devid) == PCI_CHIP_CHERRYVIEW_3) |
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4363 | Serge | 323 | |
5068 | serge | 324 | #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ |
325 | IS_CHERRYVIEW(devid)) |
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4363 | Serge | 326 | |
327 | #define IS_9XX(dev) (IS_GEN3(dev) || \ |
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328 | IS_GEN4(dev) || \ |
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329 | IS_GEN5(dev) || \ |
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330 | IS_GEN6(dev) || \ |
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331 | IS_GEN7(dev) || \ |
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332 | IS_GEN8(dev)) |
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333 | |||
334 | |||
335 | #endif /* _INTEL_CHIPSET_H */ |