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4363 Serge 1
/*
2
 * Copyright © 2008-2012 Intel Corporation
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
11
 * The above copyright notice and this permission notice (including the next
12
 * paragraph) shall be included in all copies or substantial portions of the
13
 * Software.
14
 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
 * IN THE SOFTWARE.
22
 *
23
 * Authors:
24
 *    Eric Anholt 
25
 *
26
 */
27
 
28
/**
29
 * @file intel_bufmgr.h
30
 *
31
 * Public definitions of Intel-specific bufmgr functions.
32
 */
33
 
34
#ifndef INTEL_BUFMGR_H
35
#define INTEL_BUFMGR_H
36
 
37
#include 
38
#include 
39
#include 
40
 
6110 serge 41
#if defined(__cplusplus)
42
extern "C" {
43
#endif
44
 
4363 Serge 45
struct drm_clip_rect;
46
 
47
typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
48
typedef struct _drm_intel_context drm_intel_context;
49
typedef struct _drm_intel_bo drm_intel_bo;
50
 
51
struct _drm_intel_bo {
52
	/**
53
	 * Size in bytes of the buffer object.
54
	 *
55
	 * The size may be larger than the size originally requested for the
56
	 * allocation, such as being aligned to page size.
57
	 */
58
	unsigned long size;
59
 
60
	/**
61
	 * Alignment requirement for object
62
	 *
63
	 * Used for GTT mapping & pinning the object.
64
	 */
65
	unsigned long align;
66
 
67
	/**
5068 serge 68
	 * Deprecated field containing (possibly the low 32-bits of) the last
69
	 * seen virtual card address.  Use offset64 instead.
4363 Serge 70
	 */
71
	unsigned long offset;
72
 
73
	/**
74
	 * Virtual address for accessing the buffer data.  Only valid while
75
	 * mapped.
76
	 */
77
#ifdef __cplusplus
78
	void *virt;
79
#else
80
	void *virtual;
81
#endif
82
 
83
	/** Buffer manager context associated with this buffer object */
84
	drm_intel_bufmgr *bufmgr;
85
 
86
	/**
87
	 * MM-specific handle for accessing object
88
	 */
89
	int handle;
5068 serge 90
 
91
	/**
92
	 * Last seen card virtual address (offset from the beginning of the
93
	 * aperture) for the object.  This should be used to fill relocation
94
	 * entries when calling drm_intel_bo_emit_reloc()
95
	 */
96
	uint64_t offset64;
4363 Serge 97
};
98
 
99
enum aub_dump_bmp_format {
100
	AUB_DUMP_BMP_FORMAT_8BIT = 1,
101
	AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
102
	AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
103
	AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
104
};
105
 
106
typedef struct _drm_intel_aub_annotation {
107
	uint32_t type;
108
	uint32_t subtype;
109
	uint32_t ending_offset;
110
} drm_intel_aub_annotation;
111
 
112
#define BO_ALLOC_FOR_RENDER (1<<0)
113
 
114
drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
115
				 unsigned long size, unsigned int alignment);
116
drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
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					    const char *name,
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					    unsigned long size,
119
					    unsigned int alignment);
6110 serge 120
drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
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					const char *name,
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					void *addr, uint32_t tiling_mode,
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					uint32_t stride, unsigned long size,
124
					unsigned long flags);
4363 Serge 125
drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
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				       const char *name,
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				       int x, int y, int cpp,
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				       uint32_t *tiling_mode,
129
				       unsigned long *pitch,
130
				       unsigned long flags);
131
void drm_intel_bo_reference(drm_intel_bo *bo);
132
void drm_intel_bo_unreference(drm_intel_bo *bo);
133
int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
134
int drm_intel_bo_unmap(drm_intel_bo *bo);
135
 
136
int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
137
			 unsigned long size, const void *data);
138
int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
139
			     unsigned long size, void *data);
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void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
141
 
142
void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
143
void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
144
int drm_intel_bo_exec(drm_intel_bo *bo, int used,
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		      struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
146
int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
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			struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
148
			unsigned int flags);
149
int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
150
 
151
int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
152
			    drm_intel_bo *target_bo, uint32_t target_offset,
153
			    uint32_t read_domains, uint32_t write_domain);
154
int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
155
				  drm_intel_bo *target_bo,
156
				  uint32_t target_offset,
157
				  uint32_t read_domains, uint32_t write_domain);
158
int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
159
int drm_intel_bo_unpin(drm_intel_bo *bo);
160
int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
161
			    uint32_t stride);
162
int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
163
			    uint32_t * swizzle_mode);
164
int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
165
int drm_intel_bo_busy(drm_intel_bo *bo);
166
int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
6110 serge 167
int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
168
int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
4363 Serge 169
 
170
int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
171
int drm_intel_bo_is_reusable(drm_intel_bo *bo);
172
int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
173
 
174
/* drm_intel_bufmgr_gem.c */
175
drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
176
drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
177
						const char *name,
178
						unsigned int handle);
179
drm_intel_bo *
180
bo_create_from_gem_handle(drm_intel_bufmgr *bufmgr,
181
                          unsigned int size, unsigned int handle);
182
 
183
void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
184
void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
185
void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
186
					     int limit);
187
int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
188
int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
189
int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
190
 
191
int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
192
void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
193
void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
194
 
195
void
196
drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
197
				      const char *filename);
198
void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
199
void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
200
				   int x1, int y1, int width, int height,
201
				   enum aub_dump_bmp_format format,
202
				   int pitch, int offset);
203
void
204
drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
205
					 drm_intel_aub_annotation *annotations,
206
					 unsigned count);
207
 
208
int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
209
 
210
int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
211
int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
212
int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
213
 
214
drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
215
void drm_intel_gem_context_destroy(drm_intel_context *ctx);
216
int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
217
				  int used, unsigned int flags);
218
 
219
int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
220
drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
221
						int prime_fd, int size);
222
 
223
/* drm_intel_bufmgr_fake.c */
224
drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
225
					     unsigned long low_offset,
226
					     void *low_virtual,
227
					     unsigned long size,
228
					     volatile unsigned int
229
					     *last_dispatch);
230
void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
231
					     volatile unsigned int
232
					     *last_dispatch);
233
void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
234
					     int (*exec) (drm_intel_bo *bo,
235
							  unsigned int used,
236
							  void *priv),
237
					     void *priv);
238
void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
239
					      unsigned int (*emit) (void *priv),
240
					      void (*wait) (unsigned int fence,
241
							    void *priv),
242
					      void *priv);
243
drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
244
					     const char *name,
245
					     unsigned long offset,
246
					     unsigned long size, void *virt);
247
void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
248
					     void (*invalidate_cb) (drm_intel_bo
249
								    * bo,
250
								    void *ptr),
251
					     void *ptr);
252
 
253
void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
254
void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
255
 
256
struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
257
void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
258
void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
259
					void *data, uint32_t hw_offset,
260
					int count);
261
void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
262
					int dump_past_end);
263
void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
264
				    uint32_t head, uint32_t tail);
265
void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
266
void drm_intel_decode(struct drm_intel_decode *ctx);
267
 
268
int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
269
		       uint32_t offset,
270
		       uint64_t *result);
271
 
272
int drm_intel_get_reset_stats(drm_intel_context *ctx,
273
			      uint32_t *reset_count,
274
			      uint32_t *active,
275
			      uint32_t *pending);
276
 
6110 serge 277
int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
278
int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
279
 
4363 Serge 280
/** @{ Compatibility defines to keep old code building despite the symbol rename
281
 * from dri_* to drm_intel_*
282
 */
283
#define dri_bo drm_intel_bo
284
#define dri_bufmgr drm_intel_bufmgr
285
#define dri_bo_alloc drm_intel_bo_alloc
286
#define dri_bo_reference drm_intel_bo_reference
287
#define dri_bo_unreference drm_intel_bo_unreference
288
#define dri_bo_map drm_intel_bo_map
289
#define dri_bo_unmap drm_intel_bo_unmap
290
#define dri_bo_subdata drm_intel_bo_subdata
291
#define dri_bo_get_subdata drm_intel_bo_get_subdata
292
#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
293
#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
294
#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
295
#define dri_bo_exec drm_intel_bo_exec
296
#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
297
#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset,		\
298
			  reloc_offset, target_bo)			\
299
	drm_intel_bo_emit_reloc(reloc_bo, reloc_offset,			\
300
				target_bo, target_offset,		\
301
				read, write);
302
#define dri_bo_pin drm_intel_bo_pin
303
#define dri_bo_unpin drm_intel_bo_unpin
304
#define dri_bo_get_tiling drm_intel_bo_get_tiling
305
#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
306
#define dri_bo_flink drm_intel_bo_flink
307
#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
308
#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
309
#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
310
#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
311
#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
312
#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
313
#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
314
#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
315
#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
316
#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
317
#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
318
 
319
/** @{ */
320
 
6110 serge 321
#if defined(__cplusplus)
322
}
323
#endif
324
 
4363 Serge 325
#endif /* INTEL_BUFMGR_H */