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Rev | Author | Line No. | Line |
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4363 | Serge | 1 | /* |
2 | * Copyright © 2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #ifdef HAVE_CONFIG_H |
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29 | #include "config.h" |
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30 | #endif |
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31 | |||
32 | #include |
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33 | #include |
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34 | #include |
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35 | #include |
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36 | #include |
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37 | #include |
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38 | #include |
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39 | //#include |
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6110 | serge | 40 | #include "libdrm_macros.h" |
4363 | Serge | 41 | #include "intel_bufmgr.h" |
42 | #include "intel_bufmgr_priv.h" |
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43 | #include "xf86drm.h" |
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44 | |||
45 | /** @file intel_bufmgr.c |
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46 | * |
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47 | * Convenience functions for buffer management methods. |
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48 | */ |
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49 | |||
6110 | serge | 50 | drm_intel_bo * |
51 | drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, |
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52 | unsigned long size, unsigned int alignment) |
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4363 | Serge | 53 | { |
54 | return bufmgr->bo_alloc(bufmgr, name, size, alignment); |
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55 | } |
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56 | |||
6110 | serge | 57 | drm_intel_bo * |
58 | drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name, |
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59 | unsigned long size, unsigned int alignment) |
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4363 | Serge | 60 | { |
61 | return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); |
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62 | } |
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63 | |||
64 | drm_intel_bo * |
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6110 | serge | 65 | drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr, |
66 | const char *name, void *addr, |
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67 | uint32_t tiling_mode, |
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68 | uint32_t stride, |
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69 | unsigned long size, |
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70 | unsigned long flags) |
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71 | { |
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72 | if (bufmgr->bo_alloc_userptr) |
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73 | return bufmgr->bo_alloc_userptr(bufmgr, name, addr, tiling_mode, |
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74 | stride, size, flags); |
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75 | return NULL; |
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76 | } |
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77 | |||
78 | drm_intel_bo * |
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4363 | Serge | 79 | drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, |
80 | int x, int y, int cpp, uint32_t *tiling_mode, |
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81 | unsigned long *pitch, unsigned long flags) |
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82 | { |
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83 | return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp, |
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84 | tiling_mode, pitch, flags); |
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85 | } |
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86 | |||
6110 | serge | 87 | void |
88 | drm_intel_bo_reference(drm_intel_bo *bo) |
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4363 | Serge | 89 | { |
90 | bo->bufmgr->bo_reference(bo); |
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91 | } |
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92 | |||
6110 | serge | 93 | void |
94 | drm_intel_bo_unreference(drm_intel_bo *bo) |
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4363 | Serge | 95 | { |
96 | if (bo == NULL) |
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97 | return; |
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98 | |||
99 | bo->bufmgr->bo_unreference(bo); |
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100 | } |
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101 | |||
6110 | serge | 102 | int |
103 | drm_intel_bo_map(drm_intel_bo *buf, int write_enable) |
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4363 | Serge | 104 | { |
105 | return buf->bufmgr->bo_map(buf, write_enable); |
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106 | } |
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107 | |||
6110 | serge | 108 | int |
109 | drm_intel_bo_unmap(drm_intel_bo *buf) |
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4363 | Serge | 110 | { |
111 | return buf->bufmgr->bo_unmap(buf); |
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112 | } |
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113 | |||
114 | int |
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115 | drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, |
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116 | unsigned long size, const void *data) |
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117 | { |
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118 | return bo->bufmgr->bo_subdata(bo, offset, size, data); |
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119 | } |
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120 | |||
121 | int |
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122 | drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, |
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123 | unsigned long size, void *data) |
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124 | { |
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125 | int ret; |
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6110 | serge | 126 | if (bo->bufmgr->bo_get_subdata) |
127 | return bo->bufmgr->bo_get_subdata(bo, offset, size, data); |
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4363 | Serge | 128 | |
129 | if (size == 0 || data == NULL) |
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130 | return 0; |
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131 | |||
132 | ret = drm_intel_bo_map(bo, 0); |
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133 | if (ret) |
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134 | return ret; |
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135 | memcpy(data, (unsigned char *)bo->virtual + offset, size); |
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136 | drm_intel_bo_unmap(bo); |
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137 | return 0; |
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138 | } |
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139 | |||
6110 | serge | 140 | void |
141 | drm_intel_bo_wait_rendering(drm_intel_bo *bo) |
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4363 | Serge | 142 | { |
143 | bo->bufmgr->bo_wait_rendering(bo); |
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144 | } |
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145 | |||
6110 | serge | 146 | void |
147 | drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr) |
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4363 | Serge | 148 | { |
149 | bufmgr->destroy(bufmgr); |
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150 | } |
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151 | |||
152 | int |
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153 | drm_intel_bo_exec(drm_intel_bo *bo, int used, |
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154 | drm_clip_rect_t * cliprects, int num_cliprects, int DR4) |
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155 | { |
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156 | return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); |
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157 | } |
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158 | |||
159 | int |
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160 | drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, |
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161 | drm_clip_rect_t *cliprects, int num_cliprects, int DR4, |
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162 | unsigned int rings) |
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163 | { |
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164 | if (bo->bufmgr->bo_mrb_exec) |
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165 | return bo->bufmgr->bo_mrb_exec(bo, used, |
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166 | cliprects, num_cliprects, DR4, |
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167 | rings); |
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168 | |||
169 | switch (rings) { |
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170 | case I915_EXEC_DEFAULT: |
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171 | case I915_EXEC_RENDER: |
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172 | return bo->bufmgr->bo_exec(bo, used, |
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173 | cliprects, num_cliprects, DR4); |
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174 | default: |
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175 | return -ENODEV; |
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176 | } |
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177 | } |
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178 | |||
6110 | serge | 179 | void |
180 | drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug) |
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4363 | Serge | 181 | { |
182 | bufmgr->debug = enable_debug; |
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183 | } |
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184 | |||
6110 | serge | 185 | int |
186 | drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count) |
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4363 | Serge | 187 | { |
188 | return bo_array[0]->bufmgr->check_aperture_space(bo_array, count); |
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189 | } |
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190 | |||
6110 | serge | 191 | int |
192 | drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name) |
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4363 | Serge | 193 | { |
194 | if (bo->bufmgr->bo_flink) |
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195 | return bo->bufmgr->bo_flink(bo, name); |
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196 | |||
197 | return -ENODEV; |
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198 | } |
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199 | |||
200 | int |
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201 | drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, |
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202 | drm_intel_bo *target_bo, uint32_t target_offset, |
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203 | uint32_t read_domains, uint32_t write_domain) |
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204 | { |
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205 | return bo->bufmgr->bo_emit_reloc(bo, offset, |
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206 | target_bo, target_offset, |
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207 | read_domains, write_domain); |
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208 | } |
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209 | |||
210 | /* For fence registers, not GL fences */ |
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211 | int |
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212 | drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, |
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213 | drm_intel_bo *target_bo, uint32_t target_offset, |
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214 | uint32_t read_domains, uint32_t write_domain) |
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215 | { |
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216 | return bo->bufmgr->bo_emit_reloc_fence(bo, offset, |
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217 | target_bo, target_offset, |
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218 | read_domains, write_domain); |
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219 | } |
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220 | |||
221 | |||
6110 | serge | 222 | int |
223 | drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment) |
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4363 | Serge | 224 | { |
225 | if (bo->bufmgr->bo_pin) |
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226 | return bo->bufmgr->bo_pin(bo, alignment); |
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227 | |||
228 | return -ENODEV; |
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229 | } |
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230 | |||
6110 | serge | 231 | int |
232 | drm_intel_bo_unpin(drm_intel_bo *bo) |
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4363 | Serge | 233 | { |
234 | if (bo->bufmgr->bo_unpin) |
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235 | return bo->bufmgr->bo_unpin(bo); |
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236 | |||
237 | return -ENODEV; |
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238 | } |
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239 | |||
6110 | serge | 240 | int |
241 | drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
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242 | uint32_t stride) |
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4363 | Serge | 243 | { |
244 | if (bo->bufmgr->bo_set_tiling) |
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245 | return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); |
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246 | |||
247 | *tiling_mode = I915_TILING_NONE; |
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248 | return 0; |
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249 | } |
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250 | |||
6110 | serge | 251 | int |
252 | drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
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253 | uint32_t * swizzle_mode) |
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4363 | Serge | 254 | { |
255 | if (bo->bufmgr->bo_get_tiling) |
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256 | return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); |
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257 | |||
258 | *tiling_mode = I915_TILING_NONE; |
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259 | *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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260 | return 0; |
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261 | } |
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262 | |||
6110 | serge | 263 | int |
264 | drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset) |
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4363 | Serge | 265 | { |
6110 | serge | 266 | if (bo->bufmgr->bo_set_softpin_offset) |
267 | return bo->bufmgr->bo_set_softpin_offset(bo, offset); |
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268 | |||
269 | return -ENODEV; |
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270 | } |
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271 | |||
272 | int |
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273 | drm_intel_bo_disable_reuse(drm_intel_bo *bo) |
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274 | { |
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4363 | Serge | 275 | if (bo->bufmgr->bo_disable_reuse) |
276 | return bo->bufmgr->bo_disable_reuse(bo); |
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277 | return 0; |
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278 | } |
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279 | |||
6110 | serge | 280 | int |
281 | drm_intel_bo_is_reusable(drm_intel_bo *bo) |
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4363 | Serge | 282 | { |
283 | if (bo->bufmgr->bo_is_reusable) |
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284 | return bo->bufmgr->bo_is_reusable(bo); |
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285 | return 0; |
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286 | } |
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287 | |||
6110 | serge | 288 | int |
289 | drm_intel_bo_busy(drm_intel_bo *bo) |
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4363 | Serge | 290 | { |
291 | if (bo->bufmgr->bo_busy) |
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292 | return bo->bufmgr->bo_busy(bo); |
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293 | return 0; |
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294 | } |
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295 | |||
6110 | serge | 296 | int |
297 | drm_intel_bo_madvise(drm_intel_bo *bo, int madv) |
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4363 | Serge | 298 | { |
299 | if (bo->bufmgr->bo_madvise) |
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300 | return bo->bufmgr->bo_madvise(bo, madv); |
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301 | return -1; |
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302 | } |
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303 | |||
6110 | serge | 304 | int |
305 | drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable) |
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4363 | Serge | 306 | { |
6110 | serge | 307 | if (bo->bufmgr->bo_use_48b_address_range) { |
308 | bo->bufmgr->bo_use_48b_address_range(bo, enable); |
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309 | return 0; |
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310 | } |
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311 | |||
312 | return -ENODEV; |
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313 | } |
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314 | |||
315 | int |
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316 | drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) |
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317 | { |
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4363 | Serge | 318 | return bo->bufmgr->bo_references(bo, target_bo); |
319 | } |
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320 | |||
321 | |||
322 | |||
323 | #if 0 |
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324 | static size_t |
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325 | drm_intel_probe_agp_aperture_size(int fd) |
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326 | { |
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327 | struct pci_device *pci_dev; |
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328 | size_t size = 0; |
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329 | int ret; |
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330 | |||
331 | ret = pci_system_init(); |
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332 | if (ret) |
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333 | goto err; |
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334 | |||
335 | /* XXX handle multiple adaptors? */ |
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336 | pci_dev = pci_device_find_by_slot(0, 0, 2, 0); |
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337 | if (pci_dev == NULL) |
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338 | goto err; |
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339 | |||
340 | ret = pci_device_probe(pci_dev); |
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341 | if (ret) |
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342 | goto err; |
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343 | |||
344 | size = pci_dev->regions[2].size; |
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345 | err: |
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346 | pci_system_cleanup (); |
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347 | return size; |
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348 | } |
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349 | #endif |
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350 | |||
6110 | serge | 351 | int |
352 | drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total) |
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4363 | Serge | 353 | { |
354 | |||
355 | struct drm_i915_gem_get_aperture aperture; |
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356 | int ret; |
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357 | |||
358 | ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); |
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359 | if (ret) |
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360 | return ret; |
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361 | |||
362 | /* XXX add a query for the kernel value? */ |
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363 | *mappable = 512 * 1024 * 1024; /* minimum possible value */ |
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364 | *total = aperture.aper_size; |
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365 | return 0; |
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366 | } |