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Rev | Author | Line No. | Line |
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4363 | Serge | 1 | /* |
2 | * Copyright (c) 2007 Dave Airlie |
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3 | * Copyright (c) 2007 Jakob Bornecrantz |
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4 | * Copyright (c) 2008 Red Hat Inc. |
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5 | * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA |
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6 | * Copyright (c) 2007-2008 Intel Corporation |
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7 | * |
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8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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9 | * copy of this software and associated documentation files (the "Software"), |
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10 | * to deal in the Software without restriction, including without limitation |
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11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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12 | * and/or sell copies of the Software, and to permit persons to whom the |
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13 | * Software is furnished to do so, subject to the following conditions: |
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14 | * |
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15 | * The above copyright notice and this permission notice shall be included in |
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16 | * all copies or substantial portions of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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24 | * IN THE SOFTWARE. |
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25 | */ |
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26 | |||
27 | #ifndef _DRM_MODE_H |
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28 | #define _DRM_MODE_H |
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29 | |||
30 | #define DRM_DISPLAY_INFO_LEN 32 |
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31 | #define DRM_CONNECTOR_NAME_LEN 32 |
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32 | #define DRM_DISPLAY_MODE_LEN 32 |
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33 | #define DRM_PROP_NAME_LEN 32 |
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34 | |||
35 | #define DRM_MODE_TYPE_BUILTIN (1<<0) |
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36 | #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) |
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37 | #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) |
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38 | #define DRM_MODE_TYPE_PREFERRED (1<<3) |
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39 | #define DRM_MODE_TYPE_DEFAULT (1<<4) |
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40 | #define DRM_MODE_TYPE_USERDEF (1<<5) |
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41 | #define DRM_MODE_TYPE_DRIVER (1<<6) |
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42 | |||
43 | /* Video mode flags */ |
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44 | /* bit compatible with the xorg definitions. */ |
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45 | #define DRM_MODE_FLAG_PHSYNC (1<<0) |
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46 | #define DRM_MODE_FLAG_NHSYNC (1<<1) |
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47 | #define DRM_MODE_FLAG_PVSYNC (1<<2) |
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48 | #define DRM_MODE_FLAG_NVSYNC (1<<3) |
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49 | #define DRM_MODE_FLAG_INTERLACE (1<<4) |
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50 | #define DRM_MODE_FLAG_DBLSCAN (1<<5) |
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51 | #define DRM_MODE_FLAG_CSYNC (1<<6) |
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52 | #define DRM_MODE_FLAG_PCSYNC (1<<7) |
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53 | #define DRM_MODE_FLAG_NCSYNC (1<<8) |
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54 | #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ |
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55 | #define DRM_MODE_FLAG_BCAST (1<<10) |
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56 | #define DRM_MODE_FLAG_PIXMUX (1<<11) |
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57 | #define DRM_MODE_FLAG_DBLCLK (1<<12) |
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58 | #define DRM_MODE_FLAG_CLKDIV2 (1<<13) |
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59 | #define DRM_MODE_FLAG_3D_MASK (0x1f<<14) |
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60 | #define DRM_MODE_FLAG_3D_NONE (0<<14) |
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61 | #define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) |
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62 | #define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) |
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63 | #define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) |
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64 | #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) |
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65 | #define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) |
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66 | #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) |
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67 | #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) |
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68 | #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) |
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69 | |||
70 | |||
71 | /* DPMS flags */ |
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72 | /* bit compatible with the xorg definitions. */ |
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73 | #define DRM_MODE_DPMS_ON 0 |
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74 | #define DRM_MODE_DPMS_STANDBY 1 |
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75 | #define DRM_MODE_DPMS_SUSPEND 2 |
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76 | #define DRM_MODE_DPMS_OFF 3 |
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77 | |||
78 | /* Scaling mode options */ |
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79 | #define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or |
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80 | software can still scale) */ |
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81 | #define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ |
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82 | #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ |
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83 | #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ |
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84 | |||
85 | /* Dithering mode options */ |
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86 | #define DRM_MODE_DITHERING_OFF 0 |
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87 | #define DRM_MODE_DITHERING_ON 1 |
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88 | #define DRM_MODE_DITHERING_AUTO 2 |
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89 | |||
90 | /* Dirty info options */ |
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91 | #define DRM_MODE_DIRTY_OFF 0 |
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92 | #define DRM_MODE_DIRTY_ON 1 |
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93 | #define DRM_MODE_DIRTY_ANNOTATE 2 |
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94 | |||
95 | struct drm_mode_modeinfo { |
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96 | __u32 clock; |
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97 | __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; |
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98 | __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; |
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99 | |||
100 | __u32 vrefresh; |
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101 | |||
102 | __u32 flags; |
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103 | __u32 type; |
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104 | char name[DRM_DISPLAY_MODE_LEN]; |
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105 | }; |
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106 | |||
107 | struct drm_mode_card_res { |
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108 | __u64 fb_id_ptr; |
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109 | __u64 crtc_id_ptr; |
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110 | __u64 connector_id_ptr; |
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111 | __u64 encoder_id_ptr; |
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112 | __u32 count_fbs; |
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113 | __u32 count_crtcs; |
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114 | __u32 count_connectors; |
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115 | __u32 count_encoders; |
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116 | __u32 min_width, max_width; |
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117 | __u32 min_height, max_height; |
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118 | }; |
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119 | |||
120 | struct drm_mode_crtc { |
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121 | __u64 set_connectors_ptr; |
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122 | __u32 count_connectors; |
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123 | |||
124 | __u32 crtc_id; /**< Id */ |
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125 | __u32 fb_id; /**< Id of framebuffer */ |
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126 | |||
127 | __u32 x, y; /**< Position on the frameuffer */ |
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128 | |||
129 | __u32 gamma_size; |
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130 | __u32 mode_valid; |
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131 | struct drm_mode_modeinfo mode; |
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132 | }; |
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133 | |||
134 | #define DRM_MODE_PRESENT_TOP_FIELD (1<<0) |
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135 | #define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) |
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136 | |||
137 | /* Planes blend with or override other bits on the CRTC */ |
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138 | struct drm_mode_set_plane { |
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139 | __u32 plane_id; |
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140 | __u32 crtc_id; |
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141 | __u32 fb_id; /* fb object contains surface format type */ |
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142 | __u32 flags; |
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143 | |||
144 | /* Signed dest location allows it to be partially off screen */ |
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145 | __s32 crtc_x, crtc_y; |
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146 | __u32 crtc_w, crtc_h; |
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147 | |||
148 | /* Source values are 16.16 fixed point */ |
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149 | __u32 src_x, src_y; |
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150 | __u32 src_h, src_w; |
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151 | }; |
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152 | |||
153 | struct drm_mode_get_plane { |
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154 | __u32 plane_id; |
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155 | |||
156 | __u32 crtc_id; |
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157 | __u32 fb_id; |
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158 | |||
159 | __u32 possible_crtcs; |
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160 | __u32 gamma_size; |
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161 | |||
162 | __u32 count_format_types; |
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163 | __u64 format_type_ptr; |
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164 | }; |
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165 | |||
166 | struct drm_mode_get_plane_res { |
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167 | __u64 plane_id_ptr; |
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168 | __u32 count_planes; |
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169 | }; |
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170 | |||
171 | #define DRM_MODE_ENCODER_NONE 0 |
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172 | #define DRM_MODE_ENCODER_DAC 1 |
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173 | #define DRM_MODE_ENCODER_TMDS 2 |
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174 | #define DRM_MODE_ENCODER_LVDS 3 |
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175 | #define DRM_MODE_ENCODER_TVDAC 4 |
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176 | |||
177 | struct drm_mode_get_encoder { |
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178 | __u32 encoder_id; |
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179 | __u32 encoder_type; |
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180 | |||
181 | __u32 crtc_id; /**< Id of crtc */ |
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182 | |||
183 | __u32 possible_crtcs; |
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184 | __u32 possible_clones; |
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185 | }; |
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186 | |||
187 | /* This is for connectors with multiple signal types. */ |
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188 | /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ |
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189 | #define DRM_MODE_SUBCONNECTOR_Automatic 0 |
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190 | #define DRM_MODE_SUBCONNECTOR_Unknown 0 |
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191 | #define DRM_MODE_SUBCONNECTOR_DVID 3 |
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192 | #define DRM_MODE_SUBCONNECTOR_DVIA 4 |
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193 | #define DRM_MODE_SUBCONNECTOR_Composite 5 |
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194 | #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 |
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195 | #define DRM_MODE_SUBCONNECTOR_Component 8 |
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196 | #define DRM_MODE_SUBCONNECTOR_SCART 9 |
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197 | |||
198 | #define DRM_MODE_CONNECTOR_Unknown 0 |
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199 | #define DRM_MODE_CONNECTOR_VGA 1 |
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200 | #define DRM_MODE_CONNECTOR_DVII 2 |
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201 | #define DRM_MODE_CONNECTOR_DVID 3 |
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202 | #define DRM_MODE_CONNECTOR_DVIA 4 |
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203 | #define DRM_MODE_CONNECTOR_Composite 5 |
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204 | #define DRM_MODE_CONNECTOR_SVIDEO 6 |
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205 | #define DRM_MODE_CONNECTOR_LVDS 7 |
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206 | #define DRM_MODE_CONNECTOR_Component 8 |
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207 | #define DRM_MODE_CONNECTOR_9PinDIN 9 |
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208 | #define DRM_MODE_CONNECTOR_DisplayPort 10 |
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209 | #define DRM_MODE_CONNECTOR_HDMIA 11 |
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210 | #define DRM_MODE_CONNECTOR_HDMIB 12 |
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211 | #define DRM_MODE_CONNECTOR_TV 13 |
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212 | #define DRM_MODE_CONNECTOR_eDP 14 |
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213 | |||
214 | struct drm_mode_get_connector { |
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215 | |||
216 | __u64 encoders_ptr; |
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217 | __u64 modes_ptr; |
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218 | __u64 props_ptr; |
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219 | __u64 prop_values_ptr; |
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220 | |||
221 | __u32 count_modes; |
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222 | __u32 count_props; |
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223 | __u32 count_encoders; |
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224 | |||
225 | __u32 encoder_id; /**< Current Encoder */ |
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226 | __u32 connector_id; /**< Id */ |
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227 | __u32 connector_type; |
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228 | __u32 connector_type_id; |
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229 | |||
230 | __u32 connection; |
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231 | __u32 mm_width, mm_height; /**< HxW in millimeters */ |
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232 | __u32 subpixel; |
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233 | }; |
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234 | |||
235 | #define DRM_MODE_PROP_PENDING (1<<0) |
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236 | #define DRM_MODE_PROP_RANGE (1<<1) |
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237 | #define DRM_MODE_PROP_IMMUTABLE (1<<2) |
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238 | #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ |
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239 | #define DRM_MODE_PROP_BLOB (1<<4) |
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240 | #define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ |
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241 | |||
242 | struct drm_mode_property_enum { |
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243 | __u64 value; |
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244 | char name[DRM_PROP_NAME_LEN]; |
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245 | }; |
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246 | |||
247 | struct drm_mode_get_property { |
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248 | __u64 values_ptr; /* values and blob lengths */ |
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249 | __u64 enum_blob_ptr; /* enum and blob id ptrs */ |
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250 | |||
251 | __u32 prop_id; |
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252 | __u32 flags; |
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253 | char name[DRM_PROP_NAME_LEN]; |
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254 | |||
255 | __u32 count_values; |
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256 | __u32 count_enum_blobs; |
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257 | }; |
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258 | |||
259 | struct drm_mode_connector_set_property { |
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260 | __u64 value; |
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261 | __u32 prop_id; |
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262 | __u32 connector_id; |
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263 | }; |
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264 | |||
5068 | serge | 265 | #define DRM_MODE_OBJECT_CRTC 0xcccccccc |
266 | #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0 |
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267 | #define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0 |
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268 | #define DRM_MODE_OBJECT_MODE 0xdededede |
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269 | #define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 |
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270 | #define DRM_MODE_OBJECT_FB 0xfbfbfbfb |
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271 | #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb |
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272 | #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee |
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273 | |||
4363 | Serge | 274 | struct drm_mode_obj_get_properties { |
275 | __u64 props_ptr; |
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276 | __u64 prop_values_ptr; |
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277 | __u32 count_props; |
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278 | __u32 obj_id; |
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279 | __u32 obj_type; |
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280 | }; |
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281 | |||
282 | struct drm_mode_obj_set_property { |
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283 | __u64 value; |
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284 | __u32 prop_id; |
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285 | __u32 obj_id; |
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286 | __u32 obj_type; |
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287 | }; |
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288 | |||
289 | struct drm_mode_get_blob { |
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290 | __u32 blob_id; |
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291 | __u32 length; |
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292 | __u64 data; |
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293 | }; |
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294 | |||
295 | struct drm_mode_fb_cmd { |
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296 | __u32 fb_id; |
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297 | __u32 width, height; |
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298 | __u32 pitch; |
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299 | __u32 bpp; |
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300 | __u32 depth; |
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301 | /* driver specific handle */ |
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302 | __u32 handle; |
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303 | }; |
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304 | |||
305 | #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ |
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306 | |||
307 | struct drm_mode_fb_cmd2 { |
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308 | __u32 fb_id; |
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309 | __u32 width, height; |
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310 | __u32 pixel_format; /* fourcc code from drm_fourcc.h */ |
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311 | __u32 flags; |
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312 | |||
313 | /* |
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314 | * In case of planar formats, this ioctl allows up to 4 |
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315 | * buffer objects with offsets and pitches per plane. |
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316 | * The pitch and offset order is dictated by the fourcc, |
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317 | * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: |
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318 | * |
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319 | * YUV 4:2:0 image with a plane of 8 bit Y samples |
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320 | * followed by an interleaved U/V plane containing |
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321 | * 8 bit 2x2 subsampled colour difference samples. |
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322 | * |
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323 | * So it would consist of Y as offset[0] and UV as |
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324 | * offset[1]. Note that offset[0] will generally |
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325 | * be 0. |
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326 | */ |
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327 | __u32 handles[4]; |
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328 | __u32 pitches[4]; /* pitch for each plane */ |
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329 | __u32 offsets[4]; /* offset of each plane */ |
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330 | }; |
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331 | |||
332 | #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 |
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333 | #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 |
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334 | #define DRM_MODE_FB_DIRTY_FLAGS 0x03 |
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335 | |||
336 | /* |
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337 | * Mark a region of a framebuffer as dirty. |
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338 | * |
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339 | * Some hardware does not automatically update display contents |
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340 | * as a hardware or software draw to a framebuffer. This ioctl |
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341 | * allows userspace to tell the kernel and the hardware what |
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342 | * regions of the framebuffer have changed. |
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343 | * |
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344 | * The kernel or hardware is free to update more then just the |
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345 | * region specified by the clip rects. The kernel or hardware |
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346 | * may also delay and/or coalesce several calls to dirty into a |
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347 | * single update. |
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348 | * |
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349 | * Userspace may annotate the updates, the annotates are a |
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350 | * promise made by the caller that the change is either a copy |
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351 | * of pixels or a fill of a single color in the region specified. |
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352 | * |
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353 | * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then |
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354 | * the number of updated regions are half of num_clips given, |
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355 | * where the clip rects are paired in src and dst. The width and |
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356 | * height of each one of the pairs must match. |
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357 | * |
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358 | * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller |
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359 | * promises that the region specified of the clip rects is filled |
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360 | * completely with a single color as given in the color argument. |
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361 | */ |
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362 | |||
363 | struct drm_mode_fb_dirty_cmd { |
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364 | __u32 fb_id; |
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365 | __u32 flags; |
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366 | __u32 color; |
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367 | __u32 num_clips; |
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368 | __u64 clips_ptr; |
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369 | }; |
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370 | |||
371 | struct drm_mode_mode_cmd { |
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372 | __u32 connector_id; |
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373 | struct drm_mode_modeinfo mode; |
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374 | }; |
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375 | |||
5068 | serge | 376 | #define DRM_MODE_CURSOR_BO (1<<0) |
377 | #define DRM_MODE_CURSOR_MOVE (1<<1) |
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4363 | Serge | 378 | |
379 | /* |
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5068 | serge | 380 | * depending on the value in flags diffrent members are used. |
4363 | Serge | 381 | * |
382 | * CURSOR_BO uses |
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5068 | serge | 383 | * crtc |
4363 | Serge | 384 | * width |
385 | * height |
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5068 | serge | 386 | * handle - if 0 turns the cursor of |
4363 | Serge | 387 | * |
388 | * CURSOR_MOVE uses |
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5068 | serge | 389 | * crtc |
4363 | Serge | 390 | * x |
391 | * y |
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392 | */ |
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393 | struct drm_mode_cursor { |
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394 | __u32 flags; |
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395 | __u32 crtc_id; |
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396 | __s32 x; |
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397 | __s32 y; |
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398 | __u32 width; |
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399 | __u32 height; |
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400 | /* driver specific handle */ |
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401 | __u32 handle; |
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402 | }; |
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403 | |||
404 | struct drm_mode_cursor2 { |
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405 | __u32 flags; |
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406 | __u32 crtc_id; |
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407 | __s32 x; |
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408 | __s32 y; |
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409 | __u32 width; |
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410 | __u32 height; |
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411 | /* driver specific handle */ |
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412 | __u32 handle; |
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413 | __s32 hot_x; |
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414 | __s32 hot_y; |
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415 | }; |
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416 | |||
417 | struct drm_mode_crtc_lut { |
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418 | __u32 crtc_id; |
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419 | __u32 gamma_size; |
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420 | |||
421 | /* pointers to arrays */ |
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422 | __u64 red; |
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423 | __u64 green; |
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424 | __u64 blue; |
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425 | }; |
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426 | |||
427 | #define DRM_MODE_PAGE_FLIP_EVENT 0x01 |
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428 | #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 |
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429 | #define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) |
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430 | |||
431 | /* |
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432 | * Request a page flip on the specified crtc. |
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433 | * |
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434 | * This ioctl will ask KMS to schedule a page flip for the specified |
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435 | * crtc. Once any pending rendering targeting the specified fb (as of |
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436 | * ioctl time) has completed, the crtc will be reprogrammed to display |
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437 | * that fb after the next vertical refresh. The ioctl returns |
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438 | * immediately, but subsequent rendering to the current fb will block |
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439 | * in the execbuffer ioctl until the page flip happens. If a page |
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440 | * flip is already pending as the ioctl is called, EBUSY will be |
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441 | * returned. |
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442 | * |
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443 | * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will |
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444 | * request that drm sends back a vblank event (see drm.h: struct |
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445 | * drm_event_vblank) when the page flip is done. The user_data field |
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446 | * passed in with this ioctl will be returned as the user_data field |
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447 | * in the vblank event struct. |
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448 | * |
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449 | * The reserved field must be zero until we figure out something |
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450 | * clever to use it for. |
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451 | */ |
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452 | |||
453 | struct drm_mode_crtc_page_flip { |
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454 | __u32 crtc_id; |
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455 | __u32 fb_id; |
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456 | __u32 flags; |
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457 | __u32 reserved; |
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458 | __u64 user_data; |
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459 | }; |
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460 | |||
461 | /* create a dumb scanout buffer */ |
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462 | struct drm_mode_create_dumb { |
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463 | __u32 height; |
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464 | __u32 width; |
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465 | __u32 bpp; |
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466 | __u32 flags; |
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467 | /* handle, pitch, size will be returned */ |
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468 | __u32 handle; |
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469 | __u32 pitch; |
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470 | __u64 size; |
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471 | }; |
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472 | |||
473 | /* set up for mmap of a dumb scanout buffer */ |
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474 | struct drm_mode_map_dumb { |
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475 | /** Handle for the object being mapped. */ |
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476 | __u32 handle; |
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477 | __u32 pad; |
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478 | /** |
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479 | * Fake offset to use for subsequent mmap call |
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480 | * |
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481 | * This is a fixed-size type for 32/64 compatibility. |
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482 | */ |
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483 | __u64 offset; |
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484 | }; |
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485 | |||
486 | struct drm_mode_destroy_dumb { |
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487 | __u32 handle; |
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488 | }; |
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489 | |||
490 | #endif1) |