WebSVN – Kolibri OS – Blame – /contrib/sdk/sources/libdrm/include/drm/drm.h

Rev	Author	Line No.	Line
4363	Serge	1	/**
		2	* \file drm.h
		3	* Header for the Direct Rendering Manager
		4	*
		5	* \author Rickard E. (Rik) Faith
		6	*
		7	* \par Acknowledgments:
		8	* Dec 1999, Richard Henderson , move to generic \c cmpxchg.
		9	*/
		10
		11	/*
		12	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
		13	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
		14	* All rights reserved.
		15	*
		16	* Permission is hereby granted, free of charge, to any person obtaining a
		17	* copy of this software and associated documentation files (the "Software"),
		18	* to deal in the Software without restriction, including without limitation
		19	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		20	* and/or sell copies of the Software, and to permit persons to whom the
		21	* Software is furnished to do so, subject to the following conditions:
		22	*
		23	* The above copyright notice and this permission notice (including the next
		24	* paragraph) shall be included in all copies or substantial portions of the
		25	* Software.
		26	*
		27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		28	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		29	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		30	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
		31	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		32	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		33	* OTHER DEALINGS IN THE SOFTWARE.
		34	*/
		35
		36	#ifndef _DRM_H_
		37	#define _DRM_H_
		38
		39	#include
		40
		41	typedef int8_t __s8;
		42	typedef uint8_t __u8;
		43	typedef int16_t __s16;
		44	typedef uint16_t __u16;
		45	typedef int32_t __s32;
		46	typedef uint32_t __u32;
		47	typedef int64_t __s64;
		48	typedef uint64_t __u64;
		49	typedef unsigned long drm_handle_t;
		50
		51
		52
		53	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /
		54	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /
		55	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /
		56	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /
		57
		58	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /
		59	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /
		60	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
		61	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
		62	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))
		63
		64	typedef unsigned int drm_context_t;
		65	typedef unsigned int drm_drawable_t;
		66	typedef unsigned int drm_magic_t;
		67
		68	/**
		69	* Cliprect.
		70	*
		71	* \warning: If you change this structure, make sure you change
		72	* XF86DRIClipRectRec in the server as well
		73	*
		74	* \note KW: Actually it's illegal to change either for
		75	* backwards-compatibility reasons.
		76	*/
		77	struct drm_clip_rect {
		78	unsigned short x1;
		79	unsigned short y1;
		80	unsigned short x2;
		81	unsigned short y2;
		82	};
		83
		84	/**
		85	* Drawable information.
		86	*/
		87	struct drm_drawable_info {
		88	unsigned int num_rects;
		89	struct drm_clip_rect *rects;
		90	};
		91
		92	/**
		93	* Texture region,
		94	*/
		95	struct drm_tex_region {
		96	unsigned char next;
		97	unsigned char prev;
		98	unsigned char in_use;
		99	unsigned char padding;
		100	unsigned int age;
		101	};
		102
		103	/**
		104	* Hardware lock.
		105	*
		106	* The lock structure is a simple cache-line aligned integer. To avoid
		107	* processor bus contention on a multiprocessor system, there should not be any
		108	* other data stored in the same cache line.
		109	*/
		110	struct drm_hw_lock {
		111	__volatile__ unsigned int lock; /*< lock variable /
		112	char padding[60]; /*< Pad to cache line /
		113	};
		114
		115	/**
		116	* DRM_IOCTL_VERSION ioctl argument type.
		117	*
		118	* \sa drmGetVersion().
		119	*/
		120	struct drm_version {
		121	int version_major; /*< Major version /
		122	int version_minor; /*< Minor version /
		123	int version_patchlevel; /*< Patch level /
		124	size_t name_len; /*< Length of name buffer /
		125	char name; /< Name of driver /
		126	size_t date_len; /*< Length of date buffer /
		127	char date; /< User-space buffer to hold date /
		128	size_t desc_len; /*< Length of desc buffer /
		129	char desc; /< User-space buffer to hold desc /
		130	};
		131
		132	/**
		133	* DRM_IOCTL_GET_UNIQUE ioctl argument type.
		134	*
		135	* \sa drmGetBusid() and drmSetBusId().
		136	*/
		137	struct drm_unique {
		138	size_t unique_len; /*< Length of unique /
		139	char unique; /< Unique name for driver instantiation /
		140	};
		141
		142	struct drm_list {
		143	int count; /*< Length of user-space structures /
		144	struct drm_version *version;
		145	};
		146
		147	struct drm_block {
		148	int unused;
		149	};
		150
		151	/**
		152	* DRM_IOCTL_CONTROL ioctl argument type.
		153	*
		154	* \sa drmCtlInstHandler() and drmCtlUninstHandler().
		155	*/
		156	struct drm_control {
		157	enum {
		158	DRM_ADD_COMMAND,
		159	DRM_RM_COMMAND,
		160	DRM_INST_HANDLER,
		161	DRM_UNINST_HANDLER
		162	} func;
		163	int irq;
		164	};
		165
		166	/**
		167	* Type of memory to map.
		168	*/
		169	enum drm_map_type {
		170	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /
		171	_DRM_REGISTERS = 1, /*< no caching, no core dump /
		172	_DRM_SHM = 2, /*< shared, cached /
		173	_DRM_AGP = 3, /*< AGP/GART /
		174	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /
		175	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /
		176	_DRM_GEM = 6 /*< GEM object /
		177	};
		178
		179	/**
		180	* Memory mapping flags.
		181	*/
		182	enum drm_map_flags {
		183	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /
		184	_DRM_READ_ONLY = 0x02,
		185	_DRM_LOCKED = 0x04, /*< shared, cached, locked /
		186	_DRM_KERNEL = 0x08, /*< kernel requires access /
		187	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /
		188	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /
		189	_DRM_REMOVABLE = 0x40, /*< Removable mapping /
		190	_DRM_DRIVER = 0x80 /*< Managed by driver /
		191	};
		192
		193	struct drm_ctx_priv_map {
		194	unsigned int ctx_id; /*< Context requesting private mapping /
		195	void handle; /< Handle of map /
		196	};
		197
		198	/**
		199	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
		200	* argument type.
		201	*
		202	* \sa drmAddMap().
		203	*/
		204	struct drm_map {
		205	unsigned long offset; /*< Requested physical address (0 for SAREA)/
		206	unsigned long size; /*< Requested physical size (bytes) /
		207	enum drm_map_type type; /*< Type of memory to map /
		208	enum drm_map_flags flags; /*< Flags /
		209	void handle; /< User-space: "Handle" to pass to mmap() /
		210	/*< Kernel-space: kernel-virtual address /
		211	int mtrr; /*< MTRR slot used /
		212	/* Private data */
		213	};
		214
		215	/**
		216	* DRM_IOCTL_GET_CLIENT ioctl argument type.
		217	*/
		218	struct drm_client {
		219	int idx; /*< Which client desired? /
		220	int auth; /*< Is client authenticated? /
		221	unsigned long pid; /*< Process ID /
		222	unsigned long uid; /*< User ID /
		223	unsigned long magic; /*< Magic /
		224	unsigned long iocs; /*< Ioctl count /
		225	};
		226
		227	enum drm_stat_type {
		228	_DRM_STAT_LOCK,
		229	_DRM_STAT_OPENS,
		230	_DRM_STAT_CLOSES,
		231	_DRM_STAT_IOCTLS,
		232	_DRM_STAT_LOCKS,
		233	_DRM_STAT_UNLOCKS,
		234	_DRM_STAT_VALUE, /*< Generic value /
		235	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /
		236	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /
		237
		238	_DRM_STAT_IRQ, /*< IRQ /
		239	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /
		240	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /
		241	_DRM_STAT_DMA, /*< DMA /
		242	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /
		243	_DRM_STAT_MISSED /*< Missed DMA opportunity /
		244	/* Add to the END of the list */
		245	};
		246
		247	/**
		248	* DRM_IOCTL_GET_STATS ioctl argument type.
		249	*/
		250	struct drm_stats {
		251	unsigned long count;
		252	struct {
		253	unsigned long value;
		254	enum drm_stat_type type;
		255	} data[15];
		256	};
		257
		258	/**
		259	* Hardware locking flags.
		260	*/
		261	enum drm_lock_flags {
		262	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /
		263	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /
		264	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /
		265	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /
		266	/* These HALT flags aren't supported yet
		267	-- they will be used to support the
		268	full-screen DGA-like mode. */
		269	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /
		270	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /
		271	};
		272
		273	/**
		274	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
		275	*
		276	* \sa drmGetLock() and drmUnlock().
		277	*/
		278	struct drm_lock {
		279	int context;
		280	enum drm_lock_flags flags;
		281	};
		282
		283	/**
		284	* DMA flags
		285	*
		286	* \warning
		287	* These values \e must match xf86drm.h.
		288	*
		289	* \sa drm_dma.
		290	*/
		291	enum drm_dma_flags {
		292	/* Flags for DMA buffer dispatch */
		293	_DRM_DMA_BLOCK = 0x01, /**<
		294	* Block until buffer dispatched.
		295	*
		296	* \note The buffer may not yet have
		297	* been processed by the hardware --
		298	* getting a hardware lock with the
		299	* hardware quiescent will ensure
		300	* that the buffer has been
		301	* processed.
		302	*/
		303	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /
		304	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /
		305
		306	/* Flags for DMA buffer request */
		307	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /
		308	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /
		309	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /
		310	};
		311
		312	/**
		313	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
		314	*
		315	* \sa drmAddBufs().
		316	*/
		317	struct drm_buf_desc {
		318	int count; /*< Number of buffers of this size /
		319	int size; /*< Size in bytes /
		320	int low_mark; /*< Low water mark /
		321	int high_mark; /*< High water mark /
		322	enum {
		323	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /
		324	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /
		325	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /
		326	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /
		327	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /
		328	} flags;
		329	unsigned long agp_start; /**<
		330	* Start address of where the AGP buffers are
		331	* in the AGP aperture
		332	*/
		333	};
		334
		335	/**
		336	* DRM_IOCTL_INFO_BUFS ioctl argument type.
		337	*/
		338	struct drm_buf_info {
		339	int count; /*< Entries in list /
		340	struct drm_buf_desc *list;
		341	};
		342
		343	/**
		344	* DRM_IOCTL_FREE_BUFS ioctl argument type.
		345	*/
		346	struct drm_buf_free {
		347	int count;
		348	int *list;
		349	};
		350
		351	/**
		352	* Buffer information
		353	*
		354	* \sa drm_buf_map.
		355	*/
		356	struct drm_buf_pub {
		357	int idx; /*< Index into the master buffer list /
		358	int total; /*< Buffer size /
		359	int used; /*< Amount of buffer in use (for DMA) /
		360	void address; /< Address of buffer /
		361	};
		362
		363	/**
		364	* DRM_IOCTL_MAP_BUFS ioctl argument type.
		365	*/
		366	struct drm_buf_map {
		367	int count; /*< Length of the buffer list /
		368	#ifdef __cplusplus
		369	void *virt;
		370	#else
		371	void virtual; /< Mmap'd area in user-virtual /
		372	#endif
		373	struct drm_buf_pub list; /< Buffer information /
		374	};
		375
		376	/**
		377	* DRM_IOCTL_DMA ioctl argument type.
		378	*
		379	* Indices here refer to the offset into the buffer list in drm_buf_get.
		380	*
		381	* \sa drmDMA().
		382	*/
		383	struct drm_dma {
		384	int context; /*< Context handle /
		385	int send_count; /*< Number of buffers to send /
		386	int send_indices; /< List of handles to buffers /
		387	int send_sizes; /< Lengths of data to send /
		388	enum drm_dma_flags flags; /*< Flags /
		389	int request_count; /*< Number of buffers requested /
		390	int request_size; /*< Desired size for buffers /
		391	int request_indices; /< Buffer information /
		392	int *request_sizes;
		393	int granted_count; /*< Number of buffers granted /
		394	};
		395
		396	enum drm_ctx_flags {
		397	_DRM_CONTEXT_PRESERVED = 0x01,
		398	_DRM_CONTEXT_2DONLY = 0x02
		399	};
		400
		401	/**
		402	* DRM_IOCTL_ADD_CTX ioctl argument type.
		403	*
		404	* \sa drmCreateContext() and drmDestroyContext().
		405	*/
		406	struct drm_ctx {
		407	drm_context_t handle;
		408	enum drm_ctx_flags flags;
		409	};
		410
		411	/**
		412	* DRM_IOCTL_RES_CTX ioctl argument type.
		413	*/
		414	struct drm_ctx_res {
		415	int count;
		416	struct drm_ctx *contexts;
		417	};
		418
		419	/**
		420	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
		421	*/
		422	struct drm_draw {
		423	drm_drawable_t handle;
		424	};
		425
		426	/**
		427	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
		428	*/
		429	typedef enum {
5068	serge	430	DRM_DRAWABLE_CLIPRECTS
4363	Serge	431	} drm_drawable_info_type_t;
		432
		433	struct drm_update_draw {
		434	drm_drawable_t handle;
		435	unsigned int type;
		436	unsigned int num;
		437	unsigned long long data;
		438	};
		439
		440	/**
		441	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
		442	*/
		443	struct drm_auth {
		444	drm_magic_t magic;
		445	};
		446
		447	/**
		448	* DRM_IOCTL_IRQ_BUSID ioctl argument type.
		449	*
		450	* \sa drmGetInterruptFromBusID().
		451	*/
		452	struct drm_irq_busid {
		453	int irq; /*< IRQ number /
		454	int busnum; /*< bus number /
		455	int devnum; /*< device number /
		456	int funcnum; /*< function number /
		457	};
		458
		459	enum drm_vblank_seq_type {
		460	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /
		461	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /
		462	_DRM_VBLANK_EVENT = 0x4000000, /*< Send event instead of blocking /
		463	_DRM_VBLANK_FLIP = 0x8000000, /*< Scheduled buffer swap should flip /
		464	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /
		465	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /
		466	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking, unsupported /
		467	};
		468
		469	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)
		470	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT \| _DRM_VBLANK_SIGNAL \| \
		471	_DRM_VBLANK_SECONDARY \| _DRM_VBLANK_NEXTONMISS)
		472
		473	struct drm_wait_vblank_request {
		474	enum drm_vblank_seq_type type;
		475	unsigned int sequence;
		476	unsigned long signal;
		477	};
		478
		479	struct drm_wait_vblank_reply {
		480	enum drm_vblank_seq_type type;
		481	unsigned int sequence;
		482	long tval_sec;
		483	long tval_usec;
		484	};
		485
		486	/**
		487	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
		488	*
		489	* \sa drmWaitVBlank().
		490	*/
		491	union drm_wait_vblank {
		492	struct drm_wait_vblank_request request;
		493	struct drm_wait_vblank_reply reply;
		494	};
		495
		496	#define _DRM_PRE_MODESET 1
		497	#define _DRM_POST_MODESET 2
		498
		499	/**
		500	* DRM_IOCTL_MODESET_CTL ioctl argument type
		501	*
		502	* \sa drmModesetCtl().
		503	*/
		504	struct drm_modeset_ctl {
		505	__u32 crtc;
		506	__u32 cmd;
		507	};
		508
		509	/**
		510	* DRM_IOCTL_AGP_ENABLE ioctl argument type.
		511	*
		512	* \sa drmAgpEnable().
		513	*/
		514	struct drm_agp_mode {
		515	unsigned long mode; /*< AGP mode /
		516	};
		517
		518	/**
		519	* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
		520	*
		521	* \sa drmAgpAlloc() and drmAgpFree().
		522	*/
		523	struct drm_agp_buffer {
		524	unsigned long size; /*< In bytes -- will round to page boundary /
		525	unsigned long handle; /*< Used for binding / unbinding /
		526	unsigned long type; /*< Type of memory to allocate /
		527	unsigned long physical; /*< Physical used by i810 /
		528	};
		529
		530	/**
		531	* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
		532	*
		533	* \sa drmAgpBind() and drmAgpUnbind().
		534	*/
		535	struct drm_agp_binding {
		536	unsigned long handle; /*< From drm_agp_buffer /
		537	unsigned long offset; /*< In bytes -- will round to page boundary /
		538	};
		539
		540	/**
		541	* DRM_IOCTL_AGP_INFO ioctl argument type.
		542	*
		543	* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
		544	* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
		545	* drmAgpVendorId() and drmAgpDeviceId().
		546	*/
		547	struct drm_agp_info {
		548	int agp_version_major;
		549	int agp_version_minor;
		550	unsigned long mode;
		551	unsigned long aperture_base; /* physical address */
		552	unsigned long aperture_size; /* bytes */
		553	unsigned long memory_allowed; /* bytes */
		554	unsigned long memory_used;
		555
		556	/* PCI information */
		557	unsigned short id_vendor;
		558	unsigned short id_device;
		559	};
		560
		561	/**
		562	* DRM_IOCTL_SG_ALLOC ioctl argument type.
		563	*/
		564	struct drm_scatter_gather {
		565	unsigned long size; /*< In bytes -- will round to page boundary /
		566	unsigned long handle; /*< Used for mapping / unmapping /
		567	};
		568
		569	/**
		570	* DRM_IOCTL_SET_VERSION ioctl argument type.
		571	*/
		572	struct drm_set_version {
		573	int drm_di_major;
		574	int drm_di_minor;
		575	int drm_dd_major;
		576	int drm_dd_minor;
		577	};
		578
		579	/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
		580	struct drm_gem_close {
		581	/** Handle of the object to be closed. */
		582	__u32 handle;
		583	__u32 pad;
		584	};
		585
		586	/** DRM_IOCTL_GEM_FLINK ioctl argument type */
		587	struct drm_gem_flink {
		588	/** Handle for the object being named */
		589	__u32 handle;
		590
		591	/** Returned global name */
		592	__u32 name;
		593	};
		594
		595	/** DRM_IOCTL_GEM_OPEN ioctl argument type */
		596	struct drm_gem_open {
		597	/** Name of object being opened */
		598	__u32 name;
		599
		600	/** Returned handle for the object */
		601	__u32 handle;
		602
		603	/** Returned size of the object */
		604	__u64 size;
		605	};
		606
		607	/** DRM_IOCTL_GET_CAP ioctl argument type */
		608	struct drm_get_cap {
		609	__u64 capability;
		610	__u64 value;
		611	};
		612
		613	/**
		614	* DRM_CLIENT_CAP_STEREO_3D
		615	*
		616	* if set to 1, the DRM core will expose the stereo 3D capabilities of the
		617	* monitor by advertising the supported 3D layouts in the flags of struct
		618	* drm_mode_modeinfo.
		619	*/
		620	#define DRM_CLIENT_CAP_STEREO_3D 1
		621
5068	serge	622	/**
		623	* DRM_CLIENT_CAP_UNIVERSAL_PLANES
		624	*
		625	* if set to 1, the DRM core will expose the full universal plane list
		626	* (including primary and cursor planes).
		627	*/
		628	#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
		629
4363	Serge	630	/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
		631	struct drm_set_client_cap {
		632	__u64 capability;
		633	__u64 value;
		634	};
		635
		636	#define DRM_CLOEXEC O_CLOEXEC
		637	struct drm_prime_handle {
		638	__u32 handle;
		639
		640	/** Flags.. only applicable for handle->fd */
		641	__u32 flags;
		642
		643	/** Returned dmabuf file descriptor */
		644	__s32 fd;
		645	};
		646
		647	#define SRV_GET_PCI_INFO 20
		648	#define SRV_I915_GET_PARAM 21
		649	#define SRV_I915_GEM_CREATE 22
		650	#define SRV_DRM_GEM_CLOSE 23
		651	#define SRV_DRM_GEM_FLINK 24
		652	#define SRV_DRM_GEM_OPEN 25
		653	#define SRV_I915_GEM_PIN 26
		654	#define SRV_I915_GEM_UNPIN 27
		655	#define SRV_I915_GEM_SET_CACHING 28
		656	#define SRV_I915_GEM_PWRITE 29
		657	#define SRV_I915_GEM_BUSY 30
		658	#define SRV_I915_GEM_SET_DOMAIN 31
		659	#define SRV_I915_GEM_MMAP 32
		660	#define SRV_I915_GEM_SET_TILING 33
		661	#define SRV_I915_GEM_GET_TILING 34
		662	#define SRV_I915_GEM_GET_APERTURE 35
		663	#define SRV_I915_GEM_MMAP_GTT 36
		664	#define SRV_I915_GEM_THROTTLE 37
		665	#define SRV_I915_GEM_EXECBUFFER2 38
		666	#define SRV_I915_GEM_WAIT 39
		667	#define SRV_I915_GEM_CONTEXT_CREATE 40
		668	#define SRV_I915_GEM_CONTEXT_DESTROY 41
		669	#define SRV_I915_REG_READ 42
		670
		671	#define SRV_FBINFO 43
		672	#define SRV_MASK_UPDATE 44
		673
		674
		675
		676	#include "drm_mode.h"
		677
		678	#define DRM_IOCTL_BASE 'd'
		679	#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
		680	#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
		681	#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
		682	#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
		683
		684	#define DRM_IOCTL_VERSION
		685	#define DRM_IOCTL_GET_UNIQUE
		686	#define DRM_IOCTL_GET_MAGIC
		687	#define DRM_IOCTL_IRQ_BUSID
		688	#define DRM_IOCTL_GET_MAP
		689	#define DRM_IOCTL_GET_CLIENT
		690	#define DRM_IOCTL_GET_STATS
		691	#define DRM_IOCTL_SET_VERSION
		692	#define DRM_IOCTL_MODESET_CTL
		693	#define DRM_IOCTL_GEM_CLOSE SRV_DRM_GEM_CLOSE
		694	#define DRM_IOCTL_GEM_FLINK SRV_DRM_GEM_FLINK
		695	#define DRM_IOCTL_GEM_OPEN SRV_DRM_GEM_OPEN
		696	#define DRM_IOCTL_GET_CAP
		697	#define DRM_IOCTL_SET_CLIENT_CAP
		698
		699	#define DRM_IOCTL_SET_UNIQUE
		700	#define DRM_IOCTL_AUTH_MAGIC
		701	#define DRM_IOCTL_BLOCK
		702	#define DRM_IOCTL_UNBLOCK
		703	#define DRM_IOCTL_CONTROL
		704	#define DRM_IOCTL_ADD_MAP
		705	#define DRM_IOCTL_ADD_BUFS
		706	#define DRM_IOCTL_MARK_BUFS
		707	#define DRM_IOCTL_INFO_BUFS
		708	#define DRM_IOCTL_MAP_BUFS
		709	#define DRM_IOCTL_FREE_BUFS
		710
		711	#define DRM_IOCTL_RM_MAP
		712
		713	#define DRM_IOCTL_SET_SAREA_CTX
		714	#define DRM_IOCTL_GET_SAREA_CTX
		715
		716	#define DRM_IOCTL_SET_MASTER
		717	#define DRM_IOCTL_DROP_MASTER
		718
		719	#define DRM_IOCTL_ADD_CTX
		720	#define DRM_IOCTL_RM_CTX
		721	#define DRM_IOCTL_MOD_CTX
		722	#define DRM_IOCTL_GET_CTX
		723	#define DRM_IOCTL_SWITCH_CTX
		724	#define DRM_IOCTL_NEW_CTX
		725	#define DRM_IOCTL_RES_CTX
		726	#define DRM_IOCTL_ADD_DRAW
		727	#define DRM_IOCTL_RM_DRAW
		728	#define DRM_IOCTL_DMA
		729	#define DRM_IOCTL_LOCK
		730	#define DRM_IOCTL_UNLOCK
		731	#define DRM_IOCTL_FINISH
		732
		733	#define DRM_IOCTL_PRIME_HANDLE_TO_FD
		734	#define DRM_IOCTL_PRIME_FD_TO_HANDLE
		735
		736	#define DRM_IOCTL_AGP_ACQUIRE
		737	#define DRM_IOCTL_AGP_RELEASE
		738	#define DRM_IOCTL_AGP_ENABLE
		739	#define DRM_IOCTL_AGP_INFO
		740	#define DRM_IOCTL_AGP_ALLOC
		741	#define DRM_IOCTL_AGP_FREE
		742	#define DRM_IOCTL_AGP_BIND
		743	#define DRM_IOCTL_AGP_UNBIND
		744
		745	#define DRM_IOCTL_SG_ALLOC
		746	#define DRM_IOCTL_SG_FREE
		747
		748	#define DRM_IOCTL_WAIT_VBLANK
		749
		750	#define DRM_IOCTL_UPDATE_DRAW
		751
		752	#define DRM_IOCTL_MODE_GETRESOURCES
		753	#define DRM_IOCTL_MODE_GETCRTC
		754	#define DRM_IOCTL_MODE_SETCRTC
		755	#define DRM_IOCTL_MODE_CURSOR
		756	#define DRM_IOCTL_MODE_GETGAMMA
		757	#define DRM_IOCTL_MODE_SETGAMMA
		758	#define DRM_IOCTL_MODE_GETENCODER
		759	#define DRM_IOCTL_MODE_GETCONNECTOR
		760	#define DRM_IOCTL_MODE_ATTACHMODE
		761	#define DRM_IOCTL_MODE_DETACHMODE
		762
		763	#define DRM_IOCTL_MODE_GETPROPERTY
		764	#define DRM_IOCTL_MODE_SETPROPERTY
		765	#define DRM_IOCTL_MODE_GETPROPBLOB
		766	#define DRM_IOCTL_MODE_GETFB
		767	#define DRM_IOCTL_MODE_ADDFB
		768	#define DRM_IOCTL_MODE_RMFB
		769	#define DRM_IOCTL_MODE_PAGE_FLIP
		770	#define DRM_IOCTL_MODE_DIRTYFB
		771
		772	#define DRM_IOCTL_MODE_CREATE_DUMB
		773	#define DRM_IOCTL_MODE_MAP_DUMB
		774	#define DRM_IOCTL_MODE_DESTROY_DUMB
		775	#define DRM_IOCTL_MODE_GETPLANERESOURCES
		776	#define DRM_IOCTL_MODE_GETPLANE
		777	#define DRM_IOCTL_MODE_SETPLANE
		778	#define DRM_IOCTL_MODE_ADDFB2
		779	#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES
		780	#define DRM_IOCTL_MODE_OBJ_SETPROPERTY
		781	#define DRM_IOCTL_MODE_CURSOR2
		782
		783	/**
		784	* Device specific ioctls should only be in their respective headers
		785	* The device specific ioctl range is from 0x40 to 0x99.
		786	* Generic IOCTLS restart at 0xA0.
		787	*
		788	* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
		789	* drmCommandReadWrite().
		790	*/
		791	#define DRM_COMMAND_BASE 0x40
		792	#define DRM_COMMAND_END 0xA0
		793
		794	/**
		795	* Header for events written back to userspace on the drm fd. The
		796	* type defines the type of event, the length specifies the total
		797	* length of the event (including the header), and user_data is
		798	* typically a 64 bit value passed with the ioctl that triggered the
		799	* event. A read on the drm fd will always only return complete
		800	* events, that is, if for example the read buffer is 100 bytes, and
		801	* there are two 64 byte events pending, only one will be returned.
		802	*
		803	* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
		804	* up are chipset specific.
		805	*/
		806	struct drm_event {
		807	__u32 type;
		808	__u32 length;
		809	};
		810
		811	#define DRM_EVENT_VBLANK 0x01
		812	#define DRM_EVENT_FLIP_COMPLETE 0x02
		813
		814	struct drm_event_vblank {
		815	struct drm_event base;
		816	__u64 user_data;
		817	__u32 tv_sec;
		818	__u32 tv_usec;
		819	__u32 sequence;
		820	__u32 reserved;
		821	};
		822
		823	#define DRM_CAP_DUMB_BUFFER 0x1
		824	#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
		825	#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
		826	#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
		827	#define DRM_CAP_PRIME 0x5
		828	#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
		829	#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
		830
		831	#define DRM_PRIME_CAP_IMPORT 0x1
		832	#define DRM_PRIME_CAP_EXPORT 0x2
		833
		834	/* typedef area */
		835	typedef struct drm_clip_rect drm_clip_rect_t;
		836	typedef struct drm_drawable_info drm_drawable_info_t;
		837	typedef struct drm_tex_region drm_tex_region_t;
		838	typedef struct drm_hw_lock drm_hw_lock_t;
		839	typedef struct drm_version drm_version_t;
		840	typedef struct drm_unique drm_unique_t;
		841	typedef struct drm_list drm_list_t;
		842	typedef struct drm_block drm_block_t;
		843	typedef struct drm_control drm_control_t;
		844	typedef enum drm_map_type drm_map_type_t;
		845	typedef enum drm_map_flags drm_map_flags_t;
		846	typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
		847	typedef struct drm_map drm_map_t;
		848	typedef struct drm_client drm_client_t;
		849	typedef enum drm_stat_type drm_stat_type_t;
		850	typedef struct drm_stats drm_stats_t;
		851	typedef enum drm_lock_flags drm_lock_flags_t;
		852	typedef struct drm_lock drm_lock_t;
		853	typedef enum drm_dma_flags drm_dma_flags_t;
		854	typedef struct drm_buf_desc drm_buf_desc_t;
		855	typedef struct drm_buf_info drm_buf_info_t;
		856	typedef struct drm_buf_free drm_buf_free_t;
		857	typedef struct drm_buf_pub drm_buf_pub_t;
		858	typedef struct drm_buf_map drm_buf_map_t;
		859	typedef struct drm_dma drm_dma_t;
		860	typedef union drm_wait_vblank drm_wait_vblank_t;
		861	typedef struct drm_agp_mode drm_agp_mode_t;
		862	typedef enum drm_ctx_flags drm_ctx_flags_t;
		863	typedef struct drm_ctx drm_ctx_t;
		864	typedef struct drm_ctx_res drm_ctx_res_t;
		865	typedef struct drm_draw drm_draw_t;
		866	typedef struct drm_update_draw drm_update_draw_t;
		867	typedef struct drm_auth drm_auth_t;
		868	typedef struct drm_irq_busid drm_irq_busid_t;
		869	typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
		870
		871	typedef struct drm_agp_buffer drm_agp_buffer_t;
		872	typedef struct drm_agp_binding drm_agp_binding_t;
		873	typedef struct drm_agp_info drm_agp_info_t;
		874	typedef struct drm_scatter_gather drm_scatter_gather_t;
		875	typedef struct drm_set_version drm_set_version_t;
		876
		877	int drmIoctl(int fd, unsigned long request, void *arg);
		878
		879	#endif

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(root)/contrib/sdk/sources/libdrm/include/drm/drm.h – Rev 5068