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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 6148 | serge | 1 | /* |
| 2 | * Copyright (c) 2008 Mans Rullgard |
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| 3 | * |
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| 4 | * This file is part of libswresample. |
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| 5 | * |
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| 6 | * libswresample is free software; you can redistribute it and/or |
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| 7 | * modify it under the terms of the GNU Lesser General Public |
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| 8 | * License as published by the Free Software Foundation; either |
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| 9 | * version 2.1 of the License, or (at your option) any later version. |
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| 10 | * |
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| 11 | * libswresample is distributed in the hope that it will be useful, |
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with libswresample; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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| 19 | */ |
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| 20 | |||
| 21 | #include "config.h" |
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| 22 | #include "libavutil/arm/asm.S" |
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| 23 | |||
| 24 | function swri_oldapi_conv_flt_to_s16_neon, export=1 |
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| 25 | subs r2, r2, #8 |
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| 26 | vld1.32 {q0}, [r1,:128]! |
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| 27 | vcvt.s32.f32 q8, q0, #31 |
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| 28 | vld1.32 {q1}, [r1,:128]! |
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| 29 | vcvt.s32.f32 q9, q1, #31 |
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| 30 | beq 3f |
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| 31 | bics r12, r2, #15 |
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| 32 | beq 2f |
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| 33 | 1: subs r12, r12, #16 |
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| 34 | vqrshrn.s32 d4, q8, #16 |
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| 35 | vld1.32 {q0}, [r1,:128]! |
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| 36 | vcvt.s32.f32 q0, q0, #31 |
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| 37 | vqrshrn.s32 d5, q9, #16 |
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| 38 | vld1.32 {q1}, [r1,:128]! |
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| 39 | vcvt.s32.f32 q1, q1, #31 |
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| 40 | vqrshrn.s32 d6, q0, #16 |
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| 41 | vst1.16 {q2}, [r0,:128]! |
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| 42 | vqrshrn.s32 d7, q1, #16 |
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| 43 | vld1.32 {q8}, [r1,:128]! |
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| 44 | vcvt.s32.f32 q8, q8, #31 |
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| 45 | vld1.32 {q9}, [r1,:128]! |
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| 46 | vcvt.s32.f32 q9, q9, #31 |
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| 47 | vst1.16 {q3}, [r0,:128]! |
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| 48 | bne 1b |
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| 49 | ands r2, r2, #15 |
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| 50 | beq 3f |
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| 51 | 2: vld1.32 {q0}, [r1,:128]! |
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| 52 | vqrshrn.s32 d4, q8, #16 |
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| 53 | vcvt.s32.f32 q0, q0, #31 |
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| 54 | vld1.32 {q1}, [r1,:128]! |
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| 55 | vqrshrn.s32 d5, q9, #16 |
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| 56 | vcvt.s32.f32 q1, q1, #31 |
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| 57 | vqrshrn.s32 d6, q0, #16 |
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| 58 | vst1.16 {q2}, [r0,:128]! |
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| 59 | vqrshrn.s32 d7, q1, #16 |
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| 60 | vst1.16 {q3}, [r0,:128]! |
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| 61 | bx lr |
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| 62 | 3: vqrshrn.s32 d4, q8, #16 |
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| 63 | vqrshrn.s32 d5, q9, #16 |
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| 64 | vst1.16 {q2}, [r0,:128]! |
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| 65 | bx lr |
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| 66 | endfunc |
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| 67 | |||
| 68 | function swri_oldapi_conv_fltp_to_s16_2ch_neon, export=1 |
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| 69 | ldm r1, {r1, r3} |
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| 70 | subs r2, r2, #8 |
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| 71 | vld1.32 {q0}, [r1,:128]! |
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| 72 | vcvt.s32.f32 q8, q0, #31 |
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| 73 | vld1.32 {q1}, [r1,:128]! |
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| 74 | vcvt.s32.f32 q9, q1, #31 |
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| 75 | vld1.32 {q10}, [r3,:128]! |
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| 76 | vcvt.s32.f32 q10, q10, #31 |
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| 77 | vld1.32 {q11}, [r3,:128]! |
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| 78 | vcvt.s32.f32 q11, q11, #31 |
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| 79 | beq 3f |
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| 80 | bics r12, r2, #15 |
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| 81 | beq 2f |
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| 82 | 1: subs r12, r12, #16 |
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| 83 | vld1.32 {q0}, [r1,:128]! |
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| 84 | vcvt.s32.f32 q0, q0, #31 |
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| 85 | vsri.32 q10, q8, #16 |
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| 86 | vld1.32 {q1}, [r1,:128]! |
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| 87 | vcvt.s32.f32 q1, q1, #31 |
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| 88 | vld1.32 {q12}, [r3,:128]! |
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| 89 | vcvt.s32.f32 q12, q12, #31 |
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| 90 | vld1.32 {q13}, [r3,:128]! |
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| 91 | vsri.32 q11, q9, #16 |
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| 92 | vst1.16 {q10}, [r0,:128]! |
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| 93 | vcvt.s32.f32 q13, q13, #31 |
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| 94 | vst1.16 {q11}, [r0,:128]! |
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| 95 | vsri.32 q12, q0, #16 |
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| 96 | vld1.32 {q8}, [r1,:128]! |
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| 97 | vsri.32 q13, q1, #16 |
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| 98 | vst1.16 {q12}, [r0,:128]! |
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| 99 | vcvt.s32.f32 q8, q8, #31 |
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| 100 | vld1.32 {q9}, [r1,:128]! |
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| 101 | vcvt.s32.f32 q9, q9, #31 |
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| 102 | vld1.32 {q10}, [r3,:128]! |
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| 103 | vcvt.s32.f32 q10, q10, #31 |
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| 104 | vld1.32 {q11}, [r3,:128]! |
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| 105 | vcvt.s32.f32 q11, q11, #31 |
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| 106 | vst1.16 {q13}, [r0,:128]! |
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| 107 | bne 1b |
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| 108 | ands r2, r2, #15 |
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| 109 | beq 3f |
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| 110 | 2: vsri.32 q10, q8, #16 |
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| 111 | vld1.32 {q0}, [r1,:128]! |
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| 112 | vcvt.s32.f32 q0, q0, #31 |
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| 113 | vld1.32 {q1}, [r1,:128]! |
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| 114 | vcvt.s32.f32 q1, q1, #31 |
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| 115 | vld1.32 {q12}, [r3,:128]! |
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| 116 | vcvt.s32.f32 q12, q12, #31 |
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| 117 | vsri.32 q11, q9, #16 |
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| 118 | vld1.32 {q13}, [r3,:128]! |
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| 119 | vcvt.s32.f32 q13, q13, #31 |
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| 120 | vst1.16 {q10}, [r0,:128]! |
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| 121 | vsri.32 q12, q0, #16 |
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| 122 | vst1.16 {q11}, [r0,:128]! |
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| 123 | vsri.32 q13, q1, #16 |
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| 124 | vst1.16 {q12-q13},[r0,:128]! |
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| 125 | bx lr |
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| 126 | 3: vsri.32 q10, q8, #16 |
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| 127 | vsri.32 q11, q9, #16 |
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| 128 | vst1.16 {q10-q11},[r0,:128]! |
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| 129 | bx lr |
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| 130 | endfunc |
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| 131 | |||
| 132 | function swri_oldapi_conv_fltp_to_s16_nch_neon, export=1 |
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| 133 | cmp r3, #2 |
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| 134 | itt lt |
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| 135 | ldrlt r1, [r1] |
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| 136 | blt swri_oldapi_conv_flt_to_s16_neon |
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| 137 | beq swri_oldapi_conv_fltp_to_s16_2ch_neon |
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| 138 | |||
| 139 | push {r4-r8, lr} |
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| 140 | cmp r3, #4 |
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| 141 | lsl r12, r3, #1 |
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| 142 | blt 4f |
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| 143 | |||
| 144 | @ 4 channels |
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| 145 | 5: ldm r1!, {r4-r7} |
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| 146 | mov lr, r2 |
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| 147 | mov r8, r0 |
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| 148 | vld1.32 {q8}, [r4,:128]! |
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| 149 | vcvt.s32.f32 q8, q8, #31 |
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| 150 | vld1.32 {q9}, [r5,:128]! |
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| 151 | vcvt.s32.f32 q9, q9, #31 |
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| 152 | vld1.32 {q10}, [r6,:128]! |
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| 153 | vcvt.s32.f32 q10, q10, #31 |
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| 154 | vld1.32 {q11}, [r7,:128]! |
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| 155 | vcvt.s32.f32 q11, q11, #31 |
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| 156 | 6: subs lr, lr, #8 |
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| 157 | vld1.32 {q0}, [r4,:128]! |
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| 158 | vcvt.s32.f32 q0, q0, #31 |
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| 159 | vsri.32 q9, q8, #16 |
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| 160 | vld1.32 {q1}, [r5,:128]! |
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| 161 | vcvt.s32.f32 q1, q1, #31 |
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| 162 | vsri.32 q11, q10, #16 |
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| 163 | vld1.32 {q2}, [r6,:128]! |
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| 164 | vcvt.s32.f32 q2, q2, #31 |
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| 165 | vzip.32 d18, d22 |
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| 166 | vld1.32 {q3}, [r7,:128]! |
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| 167 | vcvt.s32.f32 q3, q3, #31 |
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| 168 | vzip.32 d19, d23 |
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| 169 | vst1.16 {d18}, [r8], r12 |
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| 170 | vsri.32 q1, q0, #16 |
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| 171 | vst1.16 {d22}, [r8], r12 |
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| 172 | vsri.32 q3, q2, #16 |
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| 173 | vst1.16 {d19}, [r8], r12 |
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| 174 | vzip.32 d2, d6 |
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| 175 | vst1.16 {d23}, [r8], r12 |
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| 176 | vzip.32 d3, d7 |
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| 177 | beq 7f |
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| 178 | vld1.32 {q8}, [r4,:128]! |
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| 179 | vcvt.s32.f32 q8, q8, #31 |
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| 180 | vst1.16 {d2}, [r8], r12 |
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| 181 | vld1.32 {q9}, [r5,:128]! |
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| 182 | vcvt.s32.f32 q9, q9, #31 |
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| 183 | vst1.16 {d6}, [r8], r12 |
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| 184 | vld1.32 {q10}, [r6,:128]! |
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| 185 | vcvt.s32.f32 q10, q10, #31 |
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| 186 | vst1.16 {d3}, [r8], r12 |
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| 187 | vld1.32 {q11}, [r7,:128]! |
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| 188 | vcvt.s32.f32 q11, q11, #31 |
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| 189 | vst1.16 {d7}, [r8], r12 |
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| 190 | b 6b |
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| 191 | 7: vst1.16 {d2}, [r8], r12 |
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| 192 | vst1.16 {d6}, [r8], r12 |
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| 193 | vst1.16 {d3}, [r8], r12 |
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| 194 | vst1.16 {d7}, [r8], r12 |
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| 195 | subs r3, r3, #4 |
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| 196 | it eq |
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| 197 | popeq {r4-r8, pc} |
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| 198 | cmp r3, #4 |
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| 199 | add r0, r0, #8 |
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| 200 | bge 5b |
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| 201 | |||
| 202 | @ 2 channels |
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| 203 | 4: cmp r3, #2 |
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| 204 | blt 4f |
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| 205 | ldm r1!, {r4-r5} |
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| 206 | mov lr, r2 |
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| 207 | mov r8, r0 |
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| 208 | tst lr, #8 |
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| 209 | vld1.32 {q8}, [r4,:128]! |
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| 210 | vcvt.s32.f32 q8, q8, #31 |
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| 211 | vld1.32 {q9}, [r5,:128]! |
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| 212 | vcvt.s32.f32 q9, q9, #31 |
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| 213 | vld1.32 {q10}, [r4,:128]! |
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| 214 | vcvt.s32.f32 q10, q10, #31 |
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| 215 | vld1.32 {q11}, [r5,:128]! |
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| 216 | vcvt.s32.f32 q11, q11, #31 |
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| 217 | beq 6f |
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| 218 | subs lr, lr, #8 |
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| 219 | beq 7f |
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| 220 | vsri.32 d18, d16, #16 |
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| 221 | vsri.32 d19, d17, #16 |
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| 222 | vld1.32 {q8}, [r4,:128]! |
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| 223 | vcvt.s32.f32 q8, q8, #31 |
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| 224 | vst1.32 {d18[0]}, [r8], r12 |
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| 225 | vsri.32 d22, d20, #16 |
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| 226 | vst1.32 {d18[1]}, [r8], r12 |
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| 227 | vsri.32 d23, d21, #16 |
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| 228 | vst1.32 {d19[0]}, [r8], r12 |
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| 229 | vst1.32 {d19[1]}, [r8], r12 |
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| 230 | vld1.32 {q9}, [r5,:128]! |
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| 231 | vcvt.s32.f32 q9, q9, #31 |
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| 232 | vst1.32 {d22[0]}, [r8], r12 |
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| 233 | vst1.32 {d22[1]}, [r8], r12 |
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| 234 | vld1.32 {q10}, [r4,:128]! |
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| 235 | vcvt.s32.f32 q10, q10, #31 |
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| 236 | vst1.32 {d23[0]}, [r8], r12 |
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| 237 | vst1.32 {d23[1]}, [r8], r12 |
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| 238 | vld1.32 {q11}, [r5,:128]! |
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| 239 | vcvt.s32.f32 q11, q11, #31 |
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| 240 | 6: subs lr, lr, #16 |
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| 241 | vld1.32 {q0}, [r4,:128]! |
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| 242 | vcvt.s32.f32 q0, q0, #31 |
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| 243 | vsri.32 d18, d16, #16 |
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| 244 | vld1.32 {q1}, [r5,:128]! |
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| 245 | vcvt.s32.f32 q1, q1, #31 |
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| 246 | vsri.32 d19, d17, #16 |
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| 247 | vld1.32 {q2}, [r4,:128]! |
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| 248 | vcvt.s32.f32 q2, q2, #31 |
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| 249 | vld1.32 {q3}, [r5,:128]! |
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| 250 | vcvt.s32.f32 q3, q3, #31 |
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| 251 | vst1.32 {d18[0]}, [r8], r12 |
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| 252 | vsri.32 d22, d20, #16 |
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| 253 | vst1.32 {d18[1]}, [r8], r12 |
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| 254 | vsri.32 d23, d21, #16 |
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| 255 | vst1.32 {d19[0]}, [r8], r12 |
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| 256 | vsri.32 d2, d0, #16 |
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| 257 | vst1.32 {d19[1]}, [r8], r12 |
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| 258 | vsri.32 d3, d1, #16 |
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| 259 | vst1.32 {d22[0]}, [r8], r12 |
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| 260 | vsri.32 d6, d4, #16 |
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| 261 | vst1.32 {d22[1]}, [r8], r12 |
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| 262 | vsri.32 d7, d5, #16 |
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| 263 | vst1.32 {d23[0]}, [r8], r12 |
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| 264 | vst1.32 {d23[1]}, [r8], r12 |
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| 265 | beq 6f |
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| 266 | vld1.32 {q8}, [r4,:128]! |
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| 267 | vcvt.s32.f32 q8, q8, #31 |
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| 268 | vst1.32 {d2[0]}, [r8], r12 |
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| 269 | vst1.32 {d2[1]}, [r8], r12 |
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| 270 | vld1.32 {q9}, [r5,:128]! |
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| 271 | vcvt.s32.f32 q9, q9, #31 |
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| 272 | vst1.32 {d3[0]}, [r8], r12 |
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| 273 | vst1.32 {d3[1]}, [r8], r12 |
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| 274 | vld1.32 {q10}, [r4,:128]! |
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| 275 | vcvt.s32.f32 q10, q10, #31 |
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| 276 | vst1.32 {d6[0]}, [r8], r12 |
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| 277 | vst1.32 {d6[1]}, [r8], r12 |
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| 278 | vld1.32 {q11}, [r5,:128]! |
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| 279 | vcvt.s32.f32 q11, q11, #31 |
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| 280 | vst1.32 {d7[0]}, [r8], r12 |
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| 281 | vst1.32 {d7[1]}, [r8], r12 |
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| 282 | bgt 6b |
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| 283 | 6: vst1.32 {d2[0]}, [r8], r12 |
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| 284 | vst1.32 {d2[1]}, [r8], r12 |
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| 285 | vst1.32 {d3[0]}, [r8], r12 |
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| 286 | vst1.32 {d3[1]}, [r8], r12 |
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| 287 | vst1.32 {d6[0]}, [r8], r12 |
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| 288 | vst1.32 {d6[1]}, [r8], r12 |
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| 289 | vst1.32 {d7[0]}, [r8], r12 |
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| 290 | vst1.32 {d7[1]}, [r8], r12 |
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| 291 | b 8f |
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| 292 | 7: vsri.32 d18, d16, #16 |
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| 293 | vsri.32 d19, d17, #16 |
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| 294 | vst1.32 {d18[0]}, [r8], r12 |
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| 295 | vsri.32 d22, d20, #16 |
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| 296 | vst1.32 {d18[1]}, [r8], r12 |
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| 297 | vsri.32 d23, d21, #16 |
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| 298 | vst1.32 {d19[0]}, [r8], r12 |
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| 299 | vst1.32 {d19[1]}, [r8], r12 |
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| 300 | vst1.32 {d22[0]}, [r8], r12 |
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| 301 | vst1.32 {d22[1]}, [r8], r12 |
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| 302 | vst1.32 {d23[0]}, [r8], r12 |
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| 303 | vst1.32 {d23[1]}, [r8], r12 |
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| 304 | 8: subs r3, r3, #2 |
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| 305 | add r0, r0, #4 |
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| 306 | it eq |
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| 307 | popeq {r4-r8, pc} |
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| 308 | |||
| 309 | @ 1 channel |
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| 310 | 4: ldr r4, [r1] |
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| 311 | tst r2, #8 |
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| 312 | mov lr, r2 |
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| 313 | mov r5, r0 |
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| 314 | vld1.32 {q0}, [r4,:128]! |
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| 315 | vcvt.s32.f32 q0, q0, #31 |
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| 316 | vld1.32 {q1}, [r4,:128]! |
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| 317 | vcvt.s32.f32 q1, q1, #31 |
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| 318 | bne 8f |
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| 319 | 6: subs lr, lr, #16 |
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| 320 | vld1.32 {q2}, [r4,:128]! |
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| 321 | vcvt.s32.f32 q2, q2, #31 |
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| 322 | vld1.32 {q3}, [r4,:128]! |
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| 323 | vcvt.s32.f32 q3, q3, #31 |
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| 324 | vst1.16 {d0[1]}, [r5,:16], r12 |
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| 325 | vst1.16 {d0[3]}, [r5,:16], r12 |
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| 326 | vst1.16 {d1[1]}, [r5,:16], r12 |
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| 327 | vst1.16 {d1[3]}, [r5,:16], r12 |
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| 328 | vst1.16 {d2[1]}, [r5,:16], r12 |
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| 329 | vst1.16 {d2[3]}, [r5,:16], r12 |
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| 330 | vst1.16 {d3[1]}, [r5,:16], r12 |
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| 331 | vst1.16 {d3[3]}, [r5,:16], r12 |
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| 332 | beq 7f |
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| 333 | vld1.32 {q0}, [r4,:128]! |
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| 334 | vcvt.s32.f32 q0, q0, #31 |
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| 335 | vld1.32 {q1}, [r4,:128]! |
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| 336 | vcvt.s32.f32 q1, q1, #31 |
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| 337 | 7: vst1.16 {d4[1]}, [r5,:16], r12 |
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| 338 | vst1.16 {d4[3]}, [r5,:16], r12 |
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| 339 | vst1.16 {d5[1]}, [r5,:16], r12 |
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| 340 | vst1.16 {d5[3]}, [r5,:16], r12 |
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| 341 | vst1.16 {d6[1]}, [r5,:16], r12 |
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| 342 | vst1.16 {d6[3]}, [r5,:16], r12 |
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| 343 | vst1.16 {d7[1]}, [r5,:16], r12 |
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| 344 | vst1.16 {d7[3]}, [r5,:16], r12 |
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| 345 | bgt 6b |
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| 346 | pop {r4-r8, pc} |
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| 347 | 8: subs lr, lr, #8 |
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| 348 | vst1.16 {d0[1]}, [r5,:16], r12 |
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| 349 | vst1.16 {d0[3]}, [r5,:16], r12 |
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| 350 | vst1.16 {d1[1]}, [r5,:16], r12 |
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| 351 | vst1.16 {d1[3]}, [r5,:16], r12 |
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| 352 | vst1.16 {d2[1]}, [r5,:16], r12 |
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| 353 | vst1.16 {d2[3]}, [r5,:16], r12 |
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| 354 | vst1.16 {d3[1]}, [r5,:16], r12 |
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| 355 | vst1.16 {d3[3]}, [r5,:16], r12 |
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| 356 | it eq |
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| 357 | popeq {r4-r8, pc} |
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| 358 | vld1.32 {q0}, [r4,:128]! |
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| 359 | vcvt.s32.f32 q0, q0, #31 |
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| 360 | vld1.32 {q1}, [r4,:128]! |
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| 361 | vcvt.s32.f32 q1, q1, #31 |
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| 362 | b 6b |
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| 363 | endfunc |