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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4358 | Serge | 1 | #ifndef COMMON_CMDBUF_H |
| 2 | #define COMMON_CMDBUF_H |
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| 3 | |||
| 4 | GLboolean rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); |
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| 5 | int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); |
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| 6 | int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); |
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| 7 | void rcommonInitCmdBuf(radeonContextPtr rmesa); |
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| 8 | void rcommonDestroyCmdBuf(radeonContextPtr rmesa); |
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| 9 | |||
| 10 | void rcommonBeginBatch(radeonContextPtr rmesa, |
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| 11 | int n, |
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| 12 | int dostate, |
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| 13 | const char *file, |
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| 14 | const char *function, |
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| 15 | int line); |
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| 16 | |||
| 17 | /* +r6/r7 : code here moved */ |
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| 18 | |||
| 19 | #define CP_PACKET2 (2 << 30) |
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| 20 | #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) |
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| 21 | #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) |
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| 22 | #define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
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| 23 | |||
| 24 | /** |
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| 25 | * Every function writing to the command buffer needs to declare this |
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| 26 | * to get the necessary local variables. |
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| 27 | */ |
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| 28 | #define BATCH_LOCALS(rmesa) \ |
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| 29 | const radeonContextPtr b_l_rmesa = rmesa |
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| 30 | |||
| 31 | /** |
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| 32 | * Prepare writing n dwords to the command buffer, |
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| 33 | * including producing any necessary state emits on buffer wraparound. |
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| 34 | */ |
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| 35 | #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__) |
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| 36 | |||
| 37 | /** |
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| 38 | * Same as BEGIN_BATCH, but do not cause automatic state emits. |
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| 39 | */ |
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| 40 | #define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__) |
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| 41 | |||
| 42 | /** |
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| 43 | * Write one dword to the command buffer. |
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| 44 | */ |
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| 45 | #define OUT_BATCH(data) \ |
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| 46 | do { \ |
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| 47 | radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ |
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| 48 | } while(0) |
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| 49 | |||
| 50 | /** |
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| 51 | * Write a relocated dword to the command buffer. |
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| 52 | */ |
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| 53 | #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ |
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| 54 | do { \ |
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| 55 | int __offset = (offset); \ |
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| 56 | if (0 && __offset) { \ |
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| 57 | fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ |
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| 58 | __FILE__, __FUNCTION__, __LINE__, __offset); \ |
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| 59 | } \ |
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| 60 | radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset); \ |
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| 61 | radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ |
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| 62 | bo, rd, wd, flags); \ |
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| 63 | } while(0) |
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| 64 | |||
| 65 | |||
| 66 | /** |
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| 67 | * Write n dwords from ptr to the command buffer. |
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| 68 | */ |
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| 69 | #define OUT_BATCH_TABLE(ptr,n) \ |
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| 70 | do { \ |
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| 71 | radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\ |
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| 72 | } while(0) |
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| 73 | |||
| 74 | /** |
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| 75 | * Finish writing dwords to the command buffer. |
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| 76 | * The number of (direct or indirect) OUT_BATCH calls between the previous |
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| 77 | * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. |
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| 78 | */ |
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| 79 | #define END_BATCH() \ |
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| 80 | do { \ |
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| 81 | radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ |
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| 82 | } while(0) |
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| 83 | |||
| 84 | /** |
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| 85 | * After the last END_BATCH() of rendering, this indicates that flushing |
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| 86 | * the command buffer now is okay. |
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| 87 | */ |
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| 88 | #define COMMIT_BATCH() \ |
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| 89 | do { \ |
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| 90 | } while(0) |
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| 91 | |||
| 92 | |||
| 93 | /** Single register write to command buffer; requires 2 dwords. */ |
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| 94 | #define OUT_BATCH_REGVAL(reg, val) \ |
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| 95 | OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ |
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| 96 | OUT_BATCH((val)) |
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| 97 | |||
| 98 | /** Continuous register range write to command buffer; requires 1 dword, |
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| 99 | * expects count dwords afterwards for register contents. */ |
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| 100 | #define OUT_BATCH_REGSEQ(reg, count) \ |
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| 101 | OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))) |
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| 102 | |||
| 103 | /* +r6/r7 : code here moved */ |
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| 104 | |||
| 105 | /* Fire the buffered vertices no matter what. |
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| 106 | */ |
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| 107 | static INLINE void radeon_firevertices(radeonContextPtr radeon) |
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| 108 | { |
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| 109 | if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) |
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| 110 | radeon->glCtx.Driver.Flush(&radeon->glCtx); /* +r6/r7 */ |
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| 111 | } |
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| 112 | |||
| 113 | #endif |