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4358 | Serge | 1 | /* |
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. |
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3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to |
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4 | develop this 3D driver. |
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5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining |
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7 | a copy of this software and associated documentation files (the |
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8 | "Software"), to deal in the Software without restriction, including |
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9 | without limitation the rights to use, copy, modify, merge, publish, |
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10 | distribute, sublicense, and/or sell copies of the Software, and to |
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11 | permit persons to whom the Software is furnished to do so, subject to |
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12 | the following conditions: |
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13 | |||
14 | The above copyright notice and this permission notice (including the |
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15 | next paragraph) shall be included in all copies or substantial |
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16 | portions of the Software. |
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17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | |||
26 | **********************************************************************/ |
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27 | /* |
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28 | * Authors: |
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29 | * Keith Whitwell |
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30 | */ |
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31 | |||
32 | /** @file brw_reg.h |
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33 | * |
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34 | * This file defines struct brw_reg, which is our representation for EU |
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35 | * registers. They're not a hardware specific format, just an abstraction |
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36 | * that intends to capture the full flexibility of the hardware registers. |
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37 | * |
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38 | * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode |
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39 | * the abstract brw_reg type into the actual hardware instruction encoding. |
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40 | */ |
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41 | |||
42 | #ifndef BRW_REG_H |
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43 | #define BRW_REG_H |
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44 | |||
45 | #include |
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46 | #include "program/prog_instruction.h" |
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47 | #include "brw_defines.h" |
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48 | |||
49 | #ifdef __cplusplus |
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50 | extern "C" { |
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51 | #endif |
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52 | |||
53 | /** Number of general purpose registers (VS, WM, etc) */ |
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54 | #define BRW_MAX_GRF 128 |
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55 | |||
56 | /** |
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57 | * First GRF used for the MRF hack. |
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58 | * |
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59 | * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We |
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60 | * haven't converted our compiler to be aware of this, so it asks for MRFs and |
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61 | * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The |
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62 | * register allocators have to be careful of this to avoid corrupting the "MRF"s |
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63 | * with actual GRF allocations. |
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64 | */ |
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65 | #define GEN7_MRF_HACK_START 112 |
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66 | |||
67 | /** Number of message register file registers */ |
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68 | #define BRW_MAX_MRF 16 |
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69 | |||
70 | #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6)) |
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71 | #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3) |
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72 | |||
73 | #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3) |
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74 | #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3) |
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75 | #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0) |
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76 | #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1) |
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77 | #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2) |
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78 | #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3) |
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79 | #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1) |
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80 | |||
81 | static inline bool |
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82 | brw_is_single_value_swizzle(int swiz) |
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83 | { |
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84 | return (swiz == BRW_SWIZZLE_XXXX || |
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85 | swiz == BRW_SWIZZLE_YYYY || |
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86 | swiz == BRW_SWIZZLE_ZZZZ || |
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87 | swiz == BRW_SWIZZLE_WWWW); |
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88 | } |
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89 | |||
90 | #define REG_SIZE (8*4) |
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91 | |||
92 | /* These aren't hardware structs, just something useful for us to pass around: |
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93 | * |
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94 | * Align1 operation has a lot of control over input ranges. Used in |
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95 | * WM programs to implement shaders decomposed into "channel serial" |
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96 | * or "structure of array" form: |
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97 | */ |
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98 | struct brw_reg { |
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99 | unsigned type:4; |
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100 | unsigned file:2; |
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101 | unsigned nr:8; |
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102 | unsigned subnr:5; /* :1 in align16 */ |
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103 | unsigned negate:1; /* source only */ |
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104 | unsigned abs:1; /* source only */ |
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105 | unsigned vstride:4; /* source only */ |
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106 | unsigned width:3; /* src only, align1 only */ |
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107 | unsigned hstride:2; /* align1 only */ |
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108 | unsigned address_mode:1; /* relative addressing, hopefully! */ |
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109 | unsigned pad0:1; |
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110 | |||
111 | union { |
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112 | struct { |
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113 | unsigned swizzle:8; /* src only, align16 only */ |
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114 | unsigned writemask:4; /* dest only, align16 only */ |
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115 | int indirect_offset:10; /* relative addressing offset */ |
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116 | unsigned pad1:10; /* two dwords total */ |
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117 | } bits; |
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118 | |||
119 | float f; |
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120 | int d; |
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121 | unsigned ud; |
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122 | } dw1; |
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123 | }; |
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124 | |||
125 | |||
126 | struct brw_indirect { |
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127 | unsigned addr_subnr:4; |
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128 | int addr_offset:10; |
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129 | unsigned pad:18; |
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130 | }; |
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131 | |||
132 | |||
133 | static inline int |
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134 | type_sz(unsigned type) |
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135 | { |
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136 | switch(type) { |
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137 | case BRW_REGISTER_TYPE_UD: |
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138 | case BRW_REGISTER_TYPE_D: |
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139 | case BRW_REGISTER_TYPE_F: |
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140 | return 4; |
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141 | case BRW_REGISTER_TYPE_HF: |
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142 | case BRW_REGISTER_TYPE_UW: |
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143 | case BRW_REGISTER_TYPE_W: |
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144 | return 2; |
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145 | case BRW_REGISTER_TYPE_UB: |
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146 | case BRW_REGISTER_TYPE_B: |
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147 | return 1; |
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148 | default: |
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149 | return 0; |
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150 | } |
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151 | } |
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152 | |||
153 | /** |
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154 | * Construct a brw_reg. |
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155 | * \param file one of the BRW_x_REGISTER_FILE values |
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156 | * \param nr register number/index |
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157 | * \param subnr register sub number |
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158 | * \param type one of BRW_REGISTER_TYPE_x |
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159 | * \param vstride one of BRW_VERTICAL_STRIDE_x |
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160 | * \param width one of BRW_WIDTH_x |
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161 | * \param hstride one of BRW_HORIZONTAL_STRIDE_x |
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162 | * \param swizzle one of BRW_SWIZZLE_x |
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163 | * \param writemask WRITEMASK_X/Y/Z/W bitfield |
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164 | */ |
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165 | static inline struct brw_reg |
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166 | brw_reg(unsigned file, |
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167 | unsigned nr, |
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168 | unsigned subnr, |
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169 | unsigned type, |
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170 | unsigned vstride, |
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171 | unsigned width, |
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172 | unsigned hstride, |
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173 | unsigned swizzle, |
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174 | unsigned writemask) |
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175 | { |
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176 | struct brw_reg reg; |
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177 | if (file == BRW_GENERAL_REGISTER_FILE) |
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178 | assert(nr < BRW_MAX_GRF); |
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179 | else if (file == BRW_MESSAGE_REGISTER_FILE) |
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180 | assert((nr & ~(1 << 7)) < BRW_MAX_MRF); |
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181 | else if (file == BRW_ARCHITECTURE_REGISTER_FILE) |
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182 | assert(nr <= BRW_ARF_TIMESTAMP); |
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183 | |||
184 | reg.type = type; |
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185 | reg.file = file; |
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186 | reg.nr = nr; |
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187 | reg.subnr = subnr * type_sz(type); |
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188 | reg.negate = 0; |
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189 | reg.abs = 0; |
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190 | reg.vstride = vstride; |
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191 | reg.width = width; |
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192 | reg.hstride = hstride; |
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193 | reg.address_mode = BRW_ADDRESS_DIRECT; |
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194 | reg.pad0 = 0; |
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195 | |||
196 | /* Could do better: If the reg is r5.3<0;1,0>, we probably want to |
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197 | * set swizzle and writemask to W, as the lower bits of subnr will |
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198 | * be lost when converted to align16. This is probably too much to |
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199 | * keep track of as you'd want it adjusted by suboffset(), etc. |
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200 | * Perhaps fix up when converting to align16? |
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201 | */ |
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202 | reg.dw1.bits.swizzle = swizzle; |
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203 | reg.dw1.bits.writemask = writemask; |
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204 | reg.dw1.bits.indirect_offset = 0; |
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205 | reg.dw1.bits.pad1 = 0; |
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206 | return reg; |
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207 | } |
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208 | |||
209 | /** Construct float[16] register */ |
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210 | static inline struct brw_reg |
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211 | brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr) |
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212 | { |
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213 | return brw_reg(file, |
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214 | nr, |
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215 | subnr, |
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216 | BRW_REGISTER_TYPE_F, |
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217 | BRW_VERTICAL_STRIDE_16, |
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218 | BRW_WIDTH_16, |
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219 | BRW_HORIZONTAL_STRIDE_1, |
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220 | BRW_SWIZZLE_XYZW, |
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221 | WRITEMASK_XYZW); |
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222 | } |
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223 | |||
224 | /** Construct float[8] register */ |
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225 | static inline struct brw_reg |
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226 | brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr) |
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227 | { |
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228 | return brw_reg(file, |
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229 | nr, |
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230 | subnr, |
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231 | BRW_REGISTER_TYPE_F, |
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232 | BRW_VERTICAL_STRIDE_8, |
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233 | BRW_WIDTH_8, |
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234 | BRW_HORIZONTAL_STRIDE_1, |
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235 | BRW_SWIZZLE_XYZW, |
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236 | WRITEMASK_XYZW); |
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237 | } |
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238 | |||
239 | /** Construct float[4] register */ |
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240 | static inline struct brw_reg |
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241 | brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr) |
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242 | { |
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243 | return brw_reg(file, |
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244 | nr, |
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245 | subnr, |
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246 | BRW_REGISTER_TYPE_F, |
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247 | BRW_VERTICAL_STRIDE_4, |
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248 | BRW_WIDTH_4, |
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249 | BRW_HORIZONTAL_STRIDE_1, |
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250 | BRW_SWIZZLE_XYZW, |
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251 | WRITEMASK_XYZW); |
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252 | } |
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253 | |||
254 | /** Construct float[2] register */ |
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255 | static inline struct brw_reg |
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256 | brw_vec2_reg(unsigned file, unsigned nr, unsigned subnr) |
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257 | { |
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258 | return brw_reg(file, |
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259 | nr, |
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260 | subnr, |
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261 | BRW_REGISTER_TYPE_F, |
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262 | BRW_VERTICAL_STRIDE_2, |
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263 | BRW_WIDTH_2, |
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264 | BRW_HORIZONTAL_STRIDE_1, |
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265 | BRW_SWIZZLE_XYXY, |
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266 | WRITEMASK_XY); |
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267 | } |
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268 | |||
269 | /** Construct float[1] register */ |
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270 | static inline struct brw_reg |
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271 | brw_vec1_reg(unsigned file, unsigned nr, unsigned subnr) |
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272 | { |
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273 | return brw_reg(file, |
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274 | nr, |
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275 | subnr, |
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276 | BRW_REGISTER_TYPE_F, |
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277 | BRW_VERTICAL_STRIDE_0, |
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278 | BRW_WIDTH_1, |
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279 | BRW_HORIZONTAL_STRIDE_0, |
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280 | BRW_SWIZZLE_XXXX, |
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281 | WRITEMASK_X); |
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282 | } |
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283 | |||
284 | |||
285 | static inline struct brw_reg |
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286 | retype(struct brw_reg reg, unsigned type) |
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287 | { |
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288 | reg.type = type; |
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289 | return reg; |
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290 | } |
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291 | |||
292 | static inline struct brw_reg |
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293 | sechalf(struct brw_reg reg) |
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294 | { |
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295 | if (reg.vstride) |
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296 | reg.nr++; |
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297 | return reg; |
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298 | } |
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299 | |||
300 | static inline struct brw_reg |
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301 | suboffset(struct brw_reg reg, unsigned delta) |
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302 | { |
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303 | reg.subnr += delta * type_sz(reg.type); |
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304 | return reg; |
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305 | } |
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306 | |||
307 | |||
308 | static inline struct brw_reg |
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309 | offset(struct brw_reg reg, unsigned delta) |
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310 | { |
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311 | reg.nr += delta; |
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312 | return reg; |
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313 | } |
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314 | |||
315 | |||
316 | static inline struct brw_reg |
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317 | byte_offset(struct brw_reg reg, unsigned bytes) |
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318 | { |
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319 | unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes; |
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320 | reg.nr = newoffset / REG_SIZE; |
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321 | reg.subnr = newoffset % REG_SIZE; |
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322 | return reg; |
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323 | } |
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324 | |||
325 | |||
326 | /** Construct unsigned word[16] register */ |
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327 | static inline struct brw_reg |
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328 | brw_uw16_reg(unsigned file, unsigned nr, unsigned subnr) |
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329 | { |
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330 | return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); |
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331 | } |
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332 | |||
333 | /** Construct unsigned word[8] register */ |
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334 | static inline struct brw_reg |
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335 | brw_uw8_reg(unsigned file, unsigned nr, unsigned subnr) |
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336 | { |
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337 | return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); |
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338 | } |
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339 | |||
340 | /** Construct unsigned word[1] register */ |
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341 | static inline struct brw_reg |
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342 | brw_uw1_reg(unsigned file, unsigned nr, unsigned subnr) |
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343 | { |
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344 | return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); |
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345 | } |
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346 | |||
347 | static inline struct brw_reg |
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348 | brw_imm_reg(unsigned type) |
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349 | { |
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350 | return brw_reg(BRW_IMMEDIATE_VALUE, |
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351 | 0, |
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352 | 0, |
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353 | type, |
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354 | BRW_VERTICAL_STRIDE_0, |
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355 | BRW_WIDTH_1, |
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356 | BRW_HORIZONTAL_STRIDE_0, |
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357 | 0, |
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358 | 0); |
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359 | } |
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360 | |||
361 | /** Construct float immediate register */ |
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362 | static inline struct brw_reg |
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363 | brw_imm_f(float f) |
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364 | { |
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365 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); |
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366 | imm.dw1.f = f; |
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367 | return imm; |
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368 | } |
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369 | |||
370 | /** Construct integer immediate register */ |
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371 | static inline struct brw_reg |
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372 | brw_imm_d(int d) |
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373 | { |
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374 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); |
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375 | imm.dw1.d = d; |
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376 | return imm; |
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377 | } |
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378 | |||
379 | /** Construct uint immediate register */ |
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380 | static inline struct brw_reg |
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381 | brw_imm_ud(unsigned ud) |
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382 | { |
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383 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); |
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384 | imm.dw1.ud = ud; |
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385 | return imm; |
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386 | } |
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387 | |||
388 | /** Construct ushort immediate register */ |
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389 | static inline struct brw_reg |
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390 | brw_imm_uw(uint16_t uw) |
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391 | { |
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392 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); |
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393 | imm.dw1.ud = uw | (uw << 16); |
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394 | return imm; |
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395 | } |
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396 | |||
397 | /** Construct short immediate register */ |
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398 | static inline struct brw_reg |
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399 | brw_imm_w(int16_t w) |
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400 | { |
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401 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); |
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402 | imm.dw1.d = w | (w << 16); |
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403 | return imm; |
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404 | } |
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405 | |||
406 | /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type |
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407 | * numbers alias with _V and _VF below: |
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408 | */ |
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409 | |||
410 | /** Construct vector of eight signed half-byte values */ |
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411 | static inline struct brw_reg |
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412 | brw_imm_v(unsigned v) |
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413 | { |
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414 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V); |
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415 | imm.vstride = BRW_VERTICAL_STRIDE_0; |
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416 | imm.width = BRW_WIDTH_8; |
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417 | imm.hstride = BRW_HORIZONTAL_STRIDE_1; |
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418 | imm.dw1.ud = v; |
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419 | return imm; |
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420 | } |
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421 | |||
422 | /** Construct vector of four 8-bit float values */ |
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423 | static inline struct brw_reg |
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424 | brw_imm_vf(unsigned v) |
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425 | { |
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426 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); |
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427 | imm.vstride = BRW_VERTICAL_STRIDE_0; |
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428 | imm.width = BRW_WIDTH_4; |
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429 | imm.hstride = BRW_HORIZONTAL_STRIDE_1; |
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430 | imm.dw1.ud = v; |
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431 | return imm; |
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432 | } |
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433 | |||
434 | #define VF_ZERO 0x0 |
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435 | #define VF_ONE 0x30 |
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436 | #define VF_NEG (1<<7) |
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437 | |||
438 | static inline struct brw_reg |
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439 | brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3) |
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440 | { |
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441 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); |
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442 | imm.vstride = BRW_VERTICAL_STRIDE_0; |
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443 | imm.width = BRW_WIDTH_4; |
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444 | imm.hstride = BRW_HORIZONTAL_STRIDE_1; |
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445 | imm.dw1.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24)); |
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446 | return imm; |
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447 | } |
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448 | |||
449 | |||
450 | static inline struct brw_reg |
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451 | brw_address(struct brw_reg reg) |
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452 | { |
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453 | return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr); |
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454 | } |
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455 | |||
456 | /** Construct float[1] general-purpose register */ |
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457 | static inline struct brw_reg |
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458 | brw_vec1_grf(unsigned nr, unsigned subnr) |
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459 | { |
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460 | return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); |
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461 | } |
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462 | |||
463 | /** Construct float[2] general-purpose register */ |
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464 | static inline struct brw_reg |
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465 | brw_vec2_grf(unsigned nr, unsigned subnr) |
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466 | { |
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467 | return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); |
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468 | } |
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469 | |||
470 | /** Construct float[4] general-purpose register */ |
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471 | static inline struct brw_reg |
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472 | brw_vec4_grf(unsigned nr, unsigned subnr) |
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473 | { |
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474 | return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); |
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475 | } |
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476 | |||
477 | /** Construct float[8] general-purpose register */ |
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478 | static inline struct brw_reg |
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479 | brw_vec8_grf(unsigned nr, unsigned subnr) |
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480 | { |
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481 | return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); |
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482 | } |
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483 | |||
484 | |||
485 | static inline struct brw_reg |
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486 | brw_uw8_grf(unsigned nr, unsigned subnr) |
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487 | { |
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488 | return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); |
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489 | } |
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490 | |||
491 | static inline struct brw_reg |
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492 | brw_uw16_grf(unsigned nr, unsigned subnr) |
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493 | { |
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494 | return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); |
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495 | } |
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496 | |||
497 | |||
498 | /** Construct null register (usually used for setting condition codes) */ |
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499 | static inline struct brw_reg |
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500 | brw_null_reg(void) |
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501 | { |
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502 | return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); |
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503 | } |
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504 | |||
505 | static inline struct brw_reg |
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506 | brw_address_reg(unsigned subnr) |
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507 | { |
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508 | return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); |
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509 | } |
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510 | |||
511 | /* If/else instructions break in align16 mode if writemask & swizzle |
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512 | * aren't xyzw. This goes against the convention for other scalar |
||
513 | * regs: |
||
514 | */ |
||
515 | static inline struct brw_reg |
||
516 | brw_ip_reg(void) |
||
517 | { |
||
518 | return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, |
||
519 | BRW_ARF_IP, |
||
520 | 0, |
||
521 | BRW_REGISTER_TYPE_UD, |
||
522 | BRW_VERTICAL_STRIDE_4, /* ? */ |
||
523 | BRW_WIDTH_1, |
||
524 | BRW_HORIZONTAL_STRIDE_0, |
||
525 | BRW_SWIZZLE_XYZW, /* NOTE! */ |
||
526 | WRITEMASK_XYZW); /* NOTE! */ |
||
527 | } |
||
528 | |||
529 | static inline struct brw_reg |
||
530 | brw_acc_reg(void) |
||
531 | { |
||
532 | return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ACCUMULATOR, 0); |
||
533 | } |
||
534 | |||
535 | static inline struct brw_reg |
||
536 | brw_notification_1_reg(void) |
||
537 | { |
||
538 | |||
539 | return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, |
||
540 | BRW_ARF_NOTIFICATION_COUNT, |
||
541 | 1, |
||
542 | BRW_REGISTER_TYPE_UD, |
||
543 | BRW_VERTICAL_STRIDE_0, |
||
544 | BRW_WIDTH_1, |
||
545 | BRW_HORIZONTAL_STRIDE_0, |
||
546 | BRW_SWIZZLE_XXXX, |
||
547 | WRITEMASK_X); |
||
548 | } |
||
549 | |||
550 | |||
551 | static inline struct brw_reg |
||
552 | brw_flag_reg(int reg, int subreg) |
||
553 | { |
||
554 | return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, |
||
555 | BRW_ARF_FLAG + reg, subreg); |
||
556 | } |
||
557 | |||
558 | |||
559 | static inline struct brw_reg |
||
560 | brw_mask_reg(unsigned subnr) |
||
561 | { |
||
562 | return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr); |
||
563 | } |
||
564 | |||
565 | static inline struct brw_reg |
||
566 | brw_message_reg(unsigned nr) |
||
567 | { |
||
568 | assert((nr & ~(1 << 7)) < BRW_MAX_MRF); |
||
569 | return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0); |
||
570 | } |
||
571 | |||
572 | |||
573 | /* This is almost always called with a numeric constant argument, so |
||
574 | * make things easy to evaluate at compile time: |
||
575 | */ |
||
576 | static inline unsigned cvt(unsigned val) |
||
577 | { |
||
578 | switch (val) { |
||
579 | case 0: return 0; |
||
580 | case 1: return 1; |
||
581 | case 2: return 2; |
||
582 | case 4: return 3; |
||
583 | case 8: return 4; |
||
584 | case 16: return 5; |
||
585 | case 32: return 6; |
||
586 | } |
||
587 | return 0; |
||
588 | } |
||
589 | |||
590 | static inline struct brw_reg |
||
591 | stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride) |
||
592 | { |
||
593 | reg.vstride = cvt(vstride); |
||
594 | reg.width = cvt(width) - 1; |
||
595 | reg.hstride = cvt(hstride); |
||
596 | return reg; |
||
597 | } |
||
598 | |||
599 | |||
600 | static inline struct brw_reg |
||
601 | vec16(struct brw_reg reg) |
||
602 | { |
||
603 | return stride(reg, 16,16,1); |
||
604 | } |
||
605 | |||
606 | static inline struct brw_reg |
||
607 | vec8(struct brw_reg reg) |
||
608 | { |
||
609 | return stride(reg, 8,8,1); |
||
610 | } |
||
611 | |||
612 | static inline struct brw_reg |
||
613 | vec4(struct brw_reg reg) |
||
614 | { |
||
615 | return stride(reg, 4,4,1); |
||
616 | } |
||
617 | |||
618 | static inline struct brw_reg |
||
619 | vec2(struct brw_reg reg) |
||
620 | { |
||
621 | return stride(reg, 2,2,1); |
||
622 | } |
||
623 | |||
624 | static inline struct brw_reg |
||
625 | vec1(struct brw_reg reg) |
||
626 | { |
||
627 | return stride(reg, 0,1,0); |
||
628 | } |
||
629 | |||
630 | |||
631 | static inline struct brw_reg |
||
632 | get_element(struct brw_reg reg, unsigned elt) |
||
633 | { |
||
634 | return vec1(suboffset(reg, elt)); |
||
635 | } |
||
636 | |||
637 | static inline struct brw_reg |
||
638 | get_element_ud(struct brw_reg reg, unsigned elt) |
||
639 | { |
||
640 | return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt)); |
||
641 | } |
||
642 | |||
643 | static inline struct brw_reg |
||
644 | get_element_d(struct brw_reg reg, unsigned elt) |
||
645 | { |
||
646 | return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt)); |
||
647 | } |
||
648 | |||
649 | |||
650 | static inline struct brw_reg |
||
651 | brw_swizzle(struct brw_reg reg, unsigned x, unsigned y, unsigned z, unsigned w) |
||
652 | { |
||
653 | assert(reg.file != BRW_IMMEDIATE_VALUE); |
||
654 | |||
655 | reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x), |
||
656 | BRW_GET_SWZ(reg.dw1.bits.swizzle, y), |
||
657 | BRW_GET_SWZ(reg.dw1.bits.swizzle, z), |
||
658 | BRW_GET_SWZ(reg.dw1.bits.swizzle, w)); |
||
659 | return reg; |
||
660 | } |
||
661 | |||
662 | |||
663 | static inline struct brw_reg |
||
664 | brw_swizzle1(struct brw_reg reg, unsigned x) |
||
665 | { |
||
666 | return brw_swizzle(reg, x, x, x, x); |
||
667 | } |
||
668 | |||
669 | static inline struct brw_reg |
||
670 | brw_writemask(struct brw_reg reg, unsigned mask) |
||
671 | { |
||
672 | assert(reg.file != BRW_IMMEDIATE_VALUE); |
||
673 | reg.dw1.bits.writemask &= mask; |
||
674 | return reg; |
||
675 | } |
||
676 | |||
677 | static inline struct brw_reg |
||
678 | brw_set_writemask(struct brw_reg reg, unsigned mask) |
||
679 | { |
||
680 | assert(reg.file != BRW_IMMEDIATE_VALUE); |
||
681 | reg.dw1.bits.writemask = mask; |
||
682 | return reg; |
||
683 | } |
||
684 | |||
685 | static inline struct brw_reg |
||
686 | negate(struct brw_reg reg) |
||
687 | { |
||
688 | reg.negate ^= 1; |
||
689 | return reg; |
||
690 | } |
||
691 | |||
692 | static inline struct brw_reg |
||
693 | brw_abs(struct brw_reg reg) |
||
694 | { |
||
695 | reg.abs = 1; |
||
696 | reg.negate = 0; |
||
697 | return reg; |
||
698 | } |
||
699 | |||
700 | /************************************************************************/ |
||
701 | |||
702 | static inline struct brw_reg |
||
703 | brw_vec4_indirect(unsigned subnr, int offset) |
||
704 | { |
||
705 | struct brw_reg reg = brw_vec4_grf(0, 0); |
||
706 | reg.subnr = subnr; |
||
707 | reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; |
||
708 | reg.dw1.bits.indirect_offset = offset; |
||
709 | return reg; |
||
710 | } |
||
711 | |||
712 | static inline struct brw_reg |
||
713 | brw_vec1_indirect(unsigned subnr, int offset) |
||
714 | { |
||
715 | struct brw_reg reg = brw_vec1_grf(0, 0); |
||
716 | reg.subnr = subnr; |
||
717 | reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; |
||
718 | reg.dw1.bits.indirect_offset = offset; |
||
719 | return reg; |
||
720 | } |
||
721 | |||
722 | static inline struct brw_reg |
||
723 | deref_4f(struct brw_indirect ptr, int offset) |
||
724 | { |
||
725 | return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset); |
||
726 | } |
||
727 | |||
728 | static inline struct brw_reg |
||
729 | deref_1f(struct brw_indirect ptr, int offset) |
||
730 | { |
||
731 | return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset); |
||
732 | } |
||
733 | |||
734 | static inline struct brw_reg |
||
735 | deref_4b(struct brw_indirect ptr, int offset) |
||
736 | { |
||
737 | return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B); |
||
738 | } |
||
739 | |||
740 | static inline struct brw_reg |
||
741 | deref_1uw(struct brw_indirect ptr, int offset) |
||
742 | { |
||
743 | return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW); |
||
744 | } |
||
745 | |||
746 | static inline struct brw_reg |
||
747 | deref_1d(struct brw_indirect ptr, int offset) |
||
748 | { |
||
749 | return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D); |
||
750 | } |
||
751 | |||
752 | static inline struct brw_reg |
||
753 | deref_1ud(struct brw_indirect ptr, int offset) |
||
754 | { |
||
755 | return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD); |
||
756 | } |
||
757 | |||
758 | static inline struct brw_reg |
||
759 | get_addr_reg(struct brw_indirect ptr) |
||
760 | { |
||
761 | return brw_address_reg(ptr.addr_subnr); |
||
762 | } |
||
763 | |||
764 | static inline struct brw_indirect |
||
765 | brw_indirect_offset(struct brw_indirect ptr, int offset) |
||
766 | { |
||
767 | ptr.addr_offset += offset; |
||
768 | return ptr; |
||
769 | } |
||
770 | |||
771 | static inline struct brw_indirect |
||
772 | brw_indirect(unsigned addr_subnr, int offset) |
||
773 | { |
||
774 | struct brw_indirect ptr; |
||
775 | ptr.addr_subnr = addr_subnr; |
||
776 | ptr.addr_offset = offset; |
||
777 | ptr.pad = 0; |
||
778 | return ptr; |
||
779 | } |
||
780 | |||
781 | #ifdef __cplusplus |
||
782 | } |
||
783 | #endif |
||
784 | |||
785 | #endif>><>><>><>><>><>7) |