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| 4358 | Serge | 1 | /* |
| 2 | * Copyright © 2007 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: |
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| 24 | * Eric Anholt |
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| 25 | * |
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| 26 | */ |
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| 27 | |||
| 28 | #define PCI_CHIP_I810 0x7121 |
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| 29 | #define PCI_CHIP_I810_DC100 0x7123 |
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| 30 | #define PCI_CHIP_I810_E 0x7125 |
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| 31 | #define PCI_CHIP_I815 0x1132 |
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| 32 | |||
| 33 | #define PCI_CHIP_I830_M 0x3577 |
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| 34 | #define PCI_CHIP_845_G 0x2562 |
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| 35 | #define PCI_CHIP_I855_GM 0x3582 |
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| 36 | #define PCI_CHIP_I865_G 0x2572 |
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| 37 | |||
| 38 | #define PCI_CHIP_I915_G 0x2582 |
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| 39 | #define PCI_CHIP_E7221_G 0x258A |
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| 40 | #define PCI_CHIP_I915_GM 0x2592 |
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| 41 | #define PCI_CHIP_I945_G 0x2772 |
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| 42 | #define PCI_CHIP_I945_GM 0x27A2 |
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| 43 | #define PCI_CHIP_I945_GME 0x27AE |
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| 44 | |||
| 45 | #define PCI_CHIP_Q35_G 0x29B2 |
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| 46 | #define PCI_CHIP_G33_G 0x29C2 |
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| 47 | #define PCI_CHIP_Q33_G 0x29D2 |
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| 48 | |||
| 49 | #define PCI_CHIP_IGD_GM 0xA011 |
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| 50 | #define PCI_CHIP_IGD_G 0xA001 |
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| 51 | |||
| 52 | #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM) |
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| 53 | #define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G) |
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| 54 | #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) |
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| 55 | |||
| 56 | #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ |
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| 57 | devid == PCI_CHIP_I915_GM || \ |
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| 58 | devid == PCI_CHIP_I945_GM || \ |
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| 59 | devid == PCI_CHIP_I945_GME || \ |
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| 60 | devid == PCI_CHIP_I965_GM || \ |
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| 61 | devid == PCI_CHIP_I965_GME || \ |
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| 62 | devid == PCI_CHIP_GM45_GM || \ |
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| 63 | IS_IGD(devid) || \ |
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| 64 | devid == PCI_CHIP_ILM_G) |
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| 65 | |||
| 66 | #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ |
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| 67 | devid == PCI_CHIP_E7221_G || \ |
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| 68 | devid == PCI_CHIP_I915_GM) |
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| 69 | |||
| 70 | #define IS_945(devid) (devid == PCI_CHIP_I945_G || \ |
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| 71 | devid == PCI_CHIP_I945_GM || \ |
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| 72 | devid == PCI_CHIP_I945_GME || \ |
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| 73 | devid == PCI_CHIP_G33_G || \ |
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| 74 | devid == PCI_CHIP_Q33_G || \ |
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| 75 | devid == PCI_CHIP_Q35_G || IS_IGD(devid)) |
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| 76 | |||
| 77 | #define IS_9XX(devid) (IS_915(devid) || \ |
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| 78 | IS_945(devid)) |
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| 79 | |||
| 80 | #define IS_GEN3(devid) (IS_915(devid) || \ |
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| 81 | IS_945(devid)) |
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| 82 | |||
| 83 | #define IS_GEN2(devid) (devid == PCI_CHIP_I830_M || \ |
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| 84 | devid == PCI_CHIP_845_G || \ |
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| 85 | devid == PCI_CHIP_I855_GM || \ |
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| 86 | devid == PCI_CHIP_I865_G) |