WebSVN – Kolibri OS – Blame – /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_state.c

Rev	Author	Line No.	Line
4358	Serge	1	/*
		2	* Copyright 2012 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* on the rights to use, copy, modify, merge, publish, distribute, sub
		8	* license, and/or sell copies of the Software, and to permit persons to whom
		9	* the Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
		19	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
		20	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
		21	* USE OR OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Christian König
		25	*/
		26
		27	#include "util/u_memory.h"
		28	#include "util/u_framebuffer.h"
		29	#include "util/u_blitter.h"
		30	#include "util/u_helpers.h"
		31	#include "util/u_math.h"
		32	#include "util/u_pack_color.h"
		33	#include "util/u_upload_mgr.h"
		34	#include "util/u_format_s3tc.h"
		35	#include "tgsi/tgsi_parse.h"
		36	#include "radeonsi_pipe.h"
		37	#include "radeonsi_shader.h"
		38	#include "si_state.h"
		39	#include "sid.h"
		40
		41	static uint32_t cik_num_banks(uint32_t nbanks)
		42	{
		43	switch (nbanks) {
		44	case 2:
		45	return V_02803C_ADDR_SURF_2_BANK;
		46	case 4:
		47	return V_02803C_ADDR_SURF_4_BANK;
		48	case 8:
		49	default:
		50	return V_02803C_ADDR_SURF_8_BANK;
		51	case 16:
		52	return V_02803C_ADDR_SURF_16_BANK;
		53	}
		54	}
		55
		56
		57	static unsigned cik_tile_split(unsigned tile_split)
		58	{
		59	switch (tile_split) {
		60	case 64:
		61	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
		62	break;
		63	case 128:
		64	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
		65	break;
		66	case 256:
		67	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
		68	break;
		69	case 512:
		70	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
		71	break;
		72	default:
		73	case 1024:
		74	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
		75	break;
		76	case 2048:
		77	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
		78	break;
		79	case 4096:
		80	tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
		81	break;
		82	}
		83	return tile_split;
		84	}
		85
		86	static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
		87	{
		88	switch (macro_tile_aspect) {
		89	default:
		90	case 1:
		91	macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
		92	break;
		93	case 2:
		94	macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
		95	break;
		96	case 4:
		97	macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
		98	break;
		99	case 8:
		100	macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
		101	break;
		102	}
		103	return macro_tile_aspect;
		104	}
		105
		106	static unsigned cik_bank_wh(unsigned bankwh)
		107	{
		108	switch (bankwh) {
		109	default:
		110	case 1:
		111	bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
		112	break;
		113	case 2:
		114	bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
		115	break;
		116	case 4:
		117	bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
		118	break;
		119	case 8:
		120	bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
		121	break;
		122	}
		123	return bankwh;
		124	}
		125
		126	static unsigned cik_db_pipe_config(unsigned tile_pipes,
		127	unsigned num_rbs)
		128	{
		129	unsigned pipe_config;
		130
		131	switch (tile_pipes) {
		132	case 8:
		133	pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
		134	break;
		135	case 4:
		136	default:
		137	if (num_rbs == 4)
		138	pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
		139	else
		140	pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
		141	break;
		142	case 2:
		143	pipe_config = V_02803C_ADDR_SURF_P2;
		144	break;
		145	}
		146	return pipe_config;
		147	}
		148
		149	/*
		150	* inferred framebuffer and blender state
		151	*/
		152	static void si_update_fb_blend_state(struct r600_context *rctx)
		153	{
		154	struct si_pm4_state *pm4;
		155	struct si_state_blend *blend = rctx->queued.named.blend;
		156	uint32_t mask;
		157
		158	if (blend == NULL)
		159	return;
		160
		161	pm4 = si_pm4_alloc_state(rctx);
		162	if (pm4 == NULL)
		163	return;
		164
		165	mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
		166	mask &= blend->cb_target_mask;
		167	si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
		168
		169	si_pm4_set_state(rctx, fb_blend, pm4);
		170	}
		171
		172	/*
		173	* Blender functions
		174	*/
		175
		176	static uint32_t si_translate_blend_function(int blend_func)
		177	{
		178	switch (blend_func) {
		179	case PIPE_BLEND_ADD:
		180	return V_028780_COMB_DST_PLUS_SRC;
		181	case PIPE_BLEND_SUBTRACT:
		182	return V_028780_COMB_SRC_MINUS_DST;
		183	case PIPE_BLEND_REVERSE_SUBTRACT:
		184	return V_028780_COMB_DST_MINUS_SRC;
		185	case PIPE_BLEND_MIN:
		186	return V_028780_COMB_MIN_DST_SRC;
		187	case PIPE_BLEND_MAX:
		188	return V_028780_COMB_MAX_DST_SRC;
		189	default:
		190	R600_ERR("Unknown blend function %d\n", blend_func);
		191	assert(0);
		192	break;
		193	}
		194	return 0;
		195	}
		196
		197	static uint32_t si_translate_blend_factor(int blend_fact)
		198	{
		199	switch (blend_fact) {
		200	case PIPE_BLENDFACTOR_ONE:
		201	return V_028780_BLEND_ONE;
		202	case PIPE_BLENDFACTOR_SRC_COLOR:
		203	return V_028780_BLEND_SRC_COLOR;
		204	case PIPE_BLENDFACTOR_SRC_ALPHA:
		205	return V_028780_BLEND_SRC_ALPHA;
		206	case PIPE_BLENDFACTOR_DST_ALPHA:
		207	return V_028780_BLEND_DST_ALPHA;
		208	case PIPE_BLENDFACTOR_DST_COLOR:
		209	return V_028780_BLEND_DST_COLOR;
		210	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
		211	return V_028780_BLEND_SRC_ALPHA_SATURATE;
		212	case PIPE_BLENDFACTOR_CONST_COLOR:
		213	return V_028780_BLEND_CONSTANT_COLOR;
		214	case PIPE_BLENDFACTOR_CONST_ALPHA:
		215	return V_028780_BLEND_CONSTANT_ALPHA;
		216	case PIPE_BLENDFACTOR_ZERO:
		217	return V_028780_BLEND_ZERO;
		218	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
		219	return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
		220	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
		221	return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
		222	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
		223	return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
		224	case PIPE_BLENDFACTOR_INV_DST_COLOR:
		225	return V_028780_BLEND_ONE_MINUS_DST_COLOR;
		226	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
		227	return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
		228	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
		229	return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
		230	case PIPE_BLENDFACTOR_SRC1_COLOR:
		231	return V_028780_BLEND_SRC1_COLOR;
		232	case PIPE_BLENDFACTOR_SRC1_ALPHA:
		233	return V_028780_BLEND_SRC1_ALPHA;
		234	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
		235	return V_028780_BLEND_INV_SRC1_COLOR;
		236	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
		237	return V_028780_BLEND_INV_SRC1_ALPHA;
		238	default:
		239	R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
		240	assert(0);
		241	break;
		242	}
		243	return 0;
		244	}
		245
		246	static void si_create_blend_state(struct pipe_context ctx,
		247	const struct pipe_blend_state *state)
		248	{
		249	struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
		250	struct si_pm4_state *pm4 = &blend->pm4;
		251
		252	uint32_t color_control;
		253
		254	if (blend == NULL)
		255	return NULL;
		256
		257	color_control = S_028808_MODE(V_028808_CB_NORMAL);
		258	if (state->logicop_enable) {
		259	color_control \|= S_028808_ROP3(state->logicop_func \| (state->logicop_func << 4));
		260	} else {
		261	color_control \|= S_028808_ROP3(0xcc);
		262	}
		263	si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
		264
		265	si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
		266	si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
		267
		268	blend->cb_target_mask = 0;
		269	for (int i = 0; i < 8; i++) {
		270	/* state->rt entries > 0 only written if independent blending */
		271	const int j = state->independent_blend_enable ? i : 0;
		272
		273	unsigned eqRGB = state->rt[j].rgb_func;
		274	unsigned srcRGB = state->rt[j].rgb_src_factor;
		275	unsigned dstRGB = state->rt[j].rgb_dst_factor;
		276	unsigned eqA = state->rt[j].alpha_func;
		277	unsigned srcA = state->rt[j].alpha_src_factor;
		278	unsigned dstA = state->rt[j].alpha_dst_factor;
		279
		280	unsigned blend_cntl = 0;
		281
		282	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
		283	blend->cb_target_mask \|= state->rt[j].colormask << (4 * i);
		284
		285	if (!state->rt[j].blend_enable) {
		286	si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
		287	continue;
		288	}
		289
		290	blend_cntl \|= S_028780_ENABLE(1);
		291	blend_cntl \|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
		292	blend_cntl \|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
		293	blend_cntl \|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
		294
		295	if (srcA != srcRGB \|\| dstA != dstRGB \|\| eqA != eqRGB) {
		296	blend_cntl \|= S_028780_SEPARATE_ALPHA_BLEND(1);
		297	blend_cntl \|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
		298	blend_cntl \|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
		299	blend_cntl \|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
		300	}
		301	si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
		302	}
		303
		304	return blend;
		305	}
		306
		307	static void si_bind_blend_state(struct pipe_context ctx, void state)
		308	{
		309	struct r600_context rctx = (struct r600_context )ctx;
		310	si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
		311	si_update_fb_blend_state(rctx);
		312	}
		313
		314	static void si_delete_blend_state(struct pipe_context ctx, void state)
		315	{
		316	struct r600_context rctx = (struct r600_context )ctx;
		317	si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
		318	}
		319
		320	static void si_set_blend_color(struct pipe_context *ctx,
		321	const struct pipe_blend_color *state)
		322	{
		323	struct r600_context rctx = (struct r600_context )ctx;
		324	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		325
		326	if (pm4 == NULL)
		327	return;
		328
		329	si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
		330	si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
		331	si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
		332	si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
		333
		334	si_pm4_set_state(rctx, blend_color, pm4);
		335	}
		336
		337	/*
		338	* Clipping, scissors and viewport
		339	*/
		340
		341	static void si_set_clip_state(struct pipe_context *ctx,
		342	const struct pipe_clip_state *state)
		343	{
		344	struct r600_context rctx = (struct r600_context )ctx;
		345	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		346	struct pipe_constant_buffer cb;
		347
		348	if (pm4 == NULL)
		349	return;
		350
		351	for (int i = 0; i < 6; i++) {
		352	si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
		353	fui(state->ucp[i][0]));
		354	si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
		355	fui(state->ucp[i][1]));
		356	si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
		357	fui(state->ucp[i][2]));
		358	si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
		359	fui(state->ucp[i][3]));
		360	}
		361
		362	cb.buffer = NULL;
		363	cb.user_buffer = state->ucp;
		364	cb.buffer_offset = 0;
		365	cb.buffer_size = 448;
		366	ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
		367	pipe_resource_reference(&cb.buffer, NULL);
		368
		369	si_pm4_set_state(rctx, clip, pm4);
		370	}
		371
		372	static void si_set_scissor_states(struct pipe_context *ctx,
		373	unsigned start_slot,
		374	unsigned num_scissors,
		375	const struct pipe_scissor_state *state)
		376	{
		377	struct r600_context rctx = (struct r600_context )ctx;
		378	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		379	uint32_t tl, br;
		380
		381	if (pm4 == NULL)
		382	return;
		383
		384	tl = S_028240_TL_X(state->minx) \| S_028240_TL_Y(state->miny);
		385	br = S_028244_BR_X(state->maxx) \| S_028244_BR_Y(state->maxy);
		386	si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
		387	si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
		388	si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
		389	si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
		390	si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
		391	si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
		392	si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
		393	si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
		394
		395	si_pm4_set_state(rctx, scissor, pm4);
		396	}
		397
		398	static void si_set_viewport_states(struct pipe_context *ctx,
		399	unsigned start_slot,
		400	unsigned num_viewports,
		401	const struct pipe_viewport_state *state)
		402	{
		403	struct r600_context rctx = (struct r600_context )ctx;
		404	struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
		405	struct si_pm4_state *pm4 = &viewport->pm4;
		406
		407	if (viewport == NULL)
		408	return;
		409
		410	viewport->viewport = *state;
		411	si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
		412	si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
		413	si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
		414	si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
		415	si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
		416	si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
		417	si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
		418	si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
		419	si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
		420
		421	si_pm4_set_state(rctx, viewport, viewport);
		422	}
		423
		424	/*
		425	* inferred state between framebuffer and rasterizer
		426	*/
		427	static void si_update_fb_rs_state(struct r600_context *rctx)
		428	{
		429	struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
		430	struct si_pm4_state *pm4;
		431	unsigned offset_db_fmt_cntl = 0, depth;
		432	float offset_units;
		433
		434	if (!rs \|\| !rctx->framebuffer.zsbuf)
		435	return;
		436
		437	offset_units = rctx->queued.named.rasterizer->offset_units;
		438	switch (rctx->framebuffer.zsbuf->texture->format) {
		439	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		440	case PIPE_FORMAT_X8Z24_UNORM:
		441	case PIPE_FORMAT_Z24X8_UNORM:
		442	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		443	depth = -24;
		444	offset_units *= 2.0f;
		445	break;
		446	case PIPE_FORMAT_Z32_FLOAT:
		447	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		448	depth = -23;
		449	offset_units *= 1.0f;
		450	offset_db_fmt_cntl \|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
		451	break;
		452	case PIPE_FORMAT_Z16_UNORM:
		453	depth = -16;
		454	offset_units *= 4.0f;
		455	break;
		456	default:
		457	return;
		458	}
		459
		460	pm4 = si_pm4_alloc_state(rctx);
		461
		462	if (pm4 == NULL)
		463	return;
		464
		465	/* FIXME some of those reg can be computed with cso */
		466	offset_db_fmt_cntl \|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
		467	si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
		468	fui(rctx->queued.named.rasterizer->offset_scale));
		469	si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
		470	si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
		471	fui(rctx->queued.named.rasterizer->offset_scale));
		472	si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
		473	si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
		474
		475	si_pm4_set_state(rctx, fb_rs, pm4);
		476	}
		477
		478	/*
		479	* Rasterizer
		480	*/
		481
		482	static uint32_t si_translate_fill(uint32_t func)
		483	{
		484	switch(func) {
		485	case PIPE_POLYGON_MODE_FILL:
		486	return V_028814_X_DRAW_TRIANGLES;
		487	case PIPE_POLYGON_MODE_LINE:
		488	return V_028814_X_DRAW_LINES;
		489	case PIPE_POLYGON_MODE_POINT:
		490	return V_028814_X_DRAW_POINTS;
		491	default:
		492	assert(0);
		493	return V_028814_X_DRAW_POINTS;
		494	}
		495	}
		496
		497	static void si_create_rs_state(struct pipe_context ctx,
		498	const struct pipe_rasterizer_state *state)
		499	{
		500	struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
		501	struct si_pm4_state *pm4 = &rs->pm4;
		502	unsigned tmp;
		503	unsigned prov_vtx = 1, polygon_dual_mode;
		504	unsigned clip_rule;
		505	float psize_min, psize_max;
		506
		507	if (rs == NULL) {
		508	return NULL;
		509	}
		510
		511	rs->two_side = state->light_twoside;
		512	rs->clip_plane_enable = state->clip_plane_enable;
		513
		514	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL \|\|
		515	state->fill_back != PIPE_POLYGON_MODE_FILL);
		516
		517	if (state->flatshade_first)
		518	prov_vtx = 0;
		519
		520	rs->flatshade = state->flatshade;
		521	rs->sprite_coord_enable = state->sprite_coord_enable;
		522	rs->pa_sc_line_stipple = state->line_stipple_enable ?
		523	S_028A0C_LINE_PATTERN(state->line_stipple_pattern) \|
		524	S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
		525	rs->pa_su_sc_mode_cntl =
		526	S_028814_PROVOKING_VTX_LAST(prov_vtx) \|
		527	S_028814_CULL_FRONT(state->rasterizer_discard \|\| (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) \|
		528	S_028814_CULL_BACK(state->rasterizer_discard \|\| (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) \|
		529	S_028814_FACE(!state->front_ccw) \|
		530	S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) \|
		531	S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) \|
		532	S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) \|
		533	S_028814_POLY_MODE(polygon_dual_mode) \|
		534	S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) \|
		535	S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
		536	rs->pa_cl_clip_cntl =
		537	S_028810_PS_UCP_MODE(3) \|
		538	S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) \|
		539	S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) \|
		540	S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
		541
		542	clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
		543
		544	/* offset */
		545	rs->offset_units = state->offset_units;
		546	rs->offset_scale = state->offset_scale * 12.0f;
		547
		548	tmp = S_0286D4_FLAT_SHADE_ENA(1);
		549	if (state->sprite_coord_enable) {
		550	tmp \|= S_0286D4_PNT_SPRITE_ENA(1) \|
		551	S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) \|
		552	S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) \|
		553	S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) \|
		554	S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
		555	if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
		556	tmp \|= S_0286D4_PNT_SPRITE_TOP_1(1);
		557	}
		558	}
		559	si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
		560
		561	si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
		562	/* point size 12.4 fixed point */
		563	tmp = (unsigned)(state->point_size * 8.0);
		564	si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) \| S_028A00_WIDTH(tmp));
		565
		566	if (state->point_size_per_vertex) {
		567	psize_min = util_get_min_point_size(state);
		568	psize_max = 8192;
		569	} else {
		570	/* Force the point size to be as if the vertex output was disabled. */
		571	psize_min = state->point_size;
		572	psize_max = state->point_size;
		573	}
		574	/* Divide by two, because 0.5 = 1 pixel. */
		575	si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
		576	S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) \|
		577	S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
		578
		579	tmp = (unsigned)state->line_width * 8;
		580	si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
		581	si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
		582	S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
		583
		584	si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
		585	si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
		586	S_028BE4_PIX_CENTER(state->half_pixel_center));
		587	si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
		588	si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
		589	si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
		590	si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
		591
		592	si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
		593	si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
		594
		595	return rs;
		596	}
		597
		598	static void si_bind_rs_state(struct pipe_context ctx, void state)
		599	{
		600	struct r600_context rctx = (struct r600_context )ctx;
		601	struct si_state_rasterizer rs = (struct si_state_rasterizer )state;
		602
		603	if (state == NULL)
		604	return;
		605
		606	// TODO
		607	rctx->sprite_coord_enable = rs->sprite_coord_enable;
		608	rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
		609	rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
		610
		611	si_pm4_bind_state(rctx, rasterizer, rs);
		612	si_update_fb_rs_state(rctx);
		613	}
		614
		615	static void si_delete_rs_state(struct pipe_context ctx, void state)
		616	{
		617	struct r600_context rctx = (struct r600_context )ctx;
		618	si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
		619	}
		620
		621	/*
		622	* infeered state between dsa and stencil ref
		623	*/
		624	static void si_update_dsa_stencil_ref(struct r600_context *rctx)
		625	{
		626	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		627	struct pipe_stencil_ref *ref = &rctx->stencil_ref;
		628	struct si_state_dsa *dsa = rctx->queued.named.dsa;
		629
		630	if (pm4 == NULL)
		631	return;
		632
		633	si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
		634	S_028430_STENCILTESTVAL(ref->ref_value[0]) \|
		635	S_028430_STENCILMASK(dsa->valuemask[0]) \|
		636	S_028430_STENCILWRITEMASK(dsa->writemask[0]) \|
		637	S_028430_STENCILOPVAL(1));
		638	si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
		639	S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) \|
		640	S_028434_STENCILMASK_BF(dsa->valuemask[1]) \|
		641	S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) \|
		642	S_028434_STENCILOPVAL_BF(1));
		643
		644	si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
		645	}
		646
		647	static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
		648	const struct pipe_stencil_ref *state)
		649	{
		650	struct r600_context rctx = (struct r600_context )ctx;
		651	rctx->stencil_ref = *state;
		652	si_update_dsa_stencil_ref(rctx);
		653	}
		654
		655
		656	/*
		657	* DSA
		658	*/
		659
		660	static uint32_t si_translate_stencil_op(int s_op)
		661	{
		662	switch (s_op) {
		663	case PIPE_STENCIL_OP_KEEP:
		664	return V_02842C_STENCIL_KEEP;
		665	case PIPE_STENCIL_OP_ZERO:
		666	return V_02842C_STENCIL_ZERO;
		667	case PIPE_STENCIL_OP_REPLACE:
		668	return V_02842C_STENCIL_REPLACE_TEST;
		669	case PIPE_STENCIL_OP_INCR:
		670	return V_02842C_STENCIL_ADD_CLAMP;
		671	case PIPE_STENCIL_OP_DECR:
		672	return V_02842C_STENCIL_SUB_CLAMP;
		673	case PIPE_STENCIL_OP_INCR_WRAP:
		674	return V_02842C_STENCIL_ADD_WRAP;
		675	case PIPE_STENCIL_OP_DECR_WRAP:
		676	return V_02842C_STENCIL_SUB_WRAP;
		677	case PIPE_STENCIL_OP_INVERT:
		678	return V_02842C_STENCIL_INVERT;
		679	default:
		680	R600_ERR("Unknown stencil op %d", s_op);
		681	assert(0);
		682	break;
		683	}
		684	return 0;
		685	}
		686
		687	static void si_create_dsa_state(struct pipe_context ctx,
		688	const struct pipe_depth_stencil_alpha_state *state)
		689	{
		690	struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
		691	struct si_pm4_state *pm4 = &dsa->pm4;
		692	unsigned db_depth_control;
		693	unsigned db_render_override, db_render_control;
		694	uint32_t db_stencil_control = 0;
		695
		696	if (dsa == NULL) {
		697	return NULL;
		698	}
		699
		700	dsa->valuemask[0] = state->stencil[0].valuemask;
		701	dsa->valuemask[1] = state->stencil[1].valuemask;
		702	dsa->writemask[0] = state->stencil[0].writemask;
		703	dsa->writemask[1] = state->stencil[1].writemask;
		704
		705	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) \|
		706	S_028800_Z_WRITE_ENABLE(state->depth.writemask) \|
		707	S_028800_ZFUNC(state->depth.func);
		708
		709	/* stencil */
		710	if (state->stencil[0].enabled) {
		711	db_depth_control \|= S_028800_STENCIL_ENABLE(1);
		712	db_depth_control \|= S_028800_STENCILFUNC(state->stencil[0].func);
		713	db_stencil_control \|= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
		714	db_stencil_control \|= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
		715	db_stencil_control \|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
		716
		717	if (state->stencil[1].enabled) {
		718	db_depth_control \|= S_028800_BACKFACE_ENABLE(1);
		719	db_depth_control \|= S_028800_STENCILFUNC_BF(state->stencil[1].func);
		720	db_stencil_control \|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
		721	db_stencil_control \|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
		722	db_stencil_control \|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
		723	}
		724	}
		725
		726	/* alpha */
		727	if (state->alpha.enabled) {
		728	dsa->alpha_func = state->alpha.func;
		729	dsa->alpha_ref = state->alpha.ref_value;
		730	} else {
		731	dsa->alpha_func = PIPE_FUNC_ALWAYS;
		732	}
		733
		734	/* misc */
		735	db_render_control = 0;
		736	db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) \|
		737	S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) \|
		738	S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
		739	/* TODO db_render_override depends on query */
		740	si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
		741	si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
		742	si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
		743	si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
		744	//si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
		745	si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
		746	si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
		747	si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
		748	si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
		749	si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
		750	si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
		751	si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
		752	si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
		753	dsa->db_render_override = db_render_override;
		754
		755	return dsa;
		756	}
		757
		758	static void si_bind_dsa_state(struct pipe_context ctx, void state)
		759	{
		760	struct r600_context rctx = (struct r600_context )ctx;
		761	struct si_state_dsa *dsa = state;
		762
		763	if (state == NULL)
		764	return;
		765
		766	si_pm4_bind_state(rctx, dsa, dsa);
		767	si_update_dsa_stencil_ref(rctx);
		768	}
		769
		770	static void si_delete_dsa_state(struct pipe_context ctx, void state)
		771	{
		772	struct r600_context rctx = (struct r600_context )ctx;
		773	si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
		774	}
		775
		776	static void si_create_db_flush_dsa(struct r600_context rctx, bool copy_depth,
		777	bool copy_stencil)
		778	{
		779	struct pipe_depth_stencil_alpha_state dsa;
		780	struct si_state_dsa *state;
		781
		782	memset(&dsa, 0, sizeof(dsa));
		783
		784	state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
		785	if (copy_depth \|\| copy_stencil) {
		786	si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
		787	S_028000_DEPTH_COPY(copy_depth) \|
		788	S_028000_STENCIL_COPY(copy_stencil) \|
		789	S_028000_COPY_CENTROID(1));
		790	} else {
		791	si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
		792	S_028000_DEPTH_COMPRESS_DISABLE(1) \|
		793	S_028000_STENCIL_COMPRESS_DISABLE(1));
		794	si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
		795	S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) \|
		796	S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) \|
		797	S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) \|
		798	S_02800C_DISABLE_TILE_RATE_TILES(1));
		799	}
		800
		801	return state;
		802	}
		803
		804	/*
		805	* format translation
		806	*/
		807	static uint32_t si_translate_colorformat(enum pipe_format format)
		808	{
		809	switch (format) {
		810	/* 8-bit buffers. */
		811	case PIPE_FORMAT_A8_UNORM:
		812	case PIPE_FORMAT_A8_SNORM:
		813	case PIPE_FORMAT_A8_UINT:
		814	case PIPE_FORMAT_A8_SINT:
		815	case PIPE_FORMAT_I8_UNORM:
		816	case PIPE_FORMAT_I8_SNORM:
		817	case PIPE_FORMAT_I8_UINT:
		818	case PIPE_FORMAT_I8_SINT:
		819	case PIPE_FORMAT_L8_UNORM:
		820	case PIPE_FORMAT_L8_SNORM:
		821	case PIPE_FORMAT_L8_UINT:
		822	case PIPE_FORMAT_L8_SINT:
		823	case PIPE_FORMAT_L8_SRGB:
		824	case PIPE_FORMAT_R8_UNORM:
		825	case PIPE_FORMAT_R8_SNORM:
		826	case PIPE_FORMAT_R8_UINT:
		827	case PIPE_FORMAT_R8_SINT:
		828	return V_028C70_COLOR_8;
		829
		830	/* 16-bit buffers. */
		831	case PIPE_FORMAT_B5G6R5_UNORM:
		832	return V_028C70_COLOR_5_6_5;
		833
		834	case PIPE_FORMAT_B5G5R5A1_UNORM:
		835	case PIPE_FORMAT_B5G5R5X1_UNORM:
		836	return V_028C70_COLOR_1_5_5_5;
		837
		838	case PIPE_FORMAT_B4G4R4A4_UNORM:
		839	case PIPE_FORMAT_B4G4R4X4_UNORM:
		840	return V_028C70_COLOR_4_4_4_4;
		841
		842	case PIPE_FORMAT_L8A8_UNORM:
		843	case PIPE_FORMAT_L8A8_SNORM:
		844	case PIPE_FORMAT_L8A8_UINT:
		845	case PIPE_FORMAT_L8A8_SINT:
		846	case PIPE_FORMAT_R8G8_SNORM:
		847	case PIPE_FORMAT_R8G8_UNORM:
		848	case PIPE_FORMAT_R8G8_UINT:
		849	case PIPE_FORMAT_R8G8_SINT:
		850	return V_028C70_COLOR_8_8;
		851
		852	case PIPE_FORMAT_Z16_UNORM:
		853	case PIPE_FORMAT_R16_UNORM:
		854	case PIPE_FORMAT_R16_SNORM:
		855	case PIPE_FORMAT_R16_UINT:
		856	case PIPE_FORMAT_R16_SINT:
		857	case PIPE_FORMAT_R16_FLOAT:
		858	case PIPE_FORMAT_L16_UNORM:
		859	case PIPE_FORMAT_L16_SNORM:
		860	case PIPE_FORMAT_L16_FLOAT:
		861	case PIPE_FORMAT_I16_UNORM:
		862	case PIPE_FORMAT_I16_SNORM:
		863	case PIPE_FORMAT_I16_FLOAT:
		864	case PIPE_FORMAT_A16_UNORM:
		865	case PIPE_FORMAT_A16_SNORM:
		866	case PIPE_FORMAT_A16_FLOAT:
		867	return V_028C70_COLOR_16;
		868
		869	/* 32-bit buffers. */
		870	case PIPE_FORMAT_A8B8G8R8_SRGB:
		871	case PIPE_FORMAT_A8B8G8R8_UNORM:
		872	case PIPE_FORMAT_A8R8G8B8_UNORM:
		873	case PIPE_FORMAT_B8G8R8A8_SRGB:
		874	case PIPE_FORMAT_B8G8R8A8_UNORM:
		875	case PIPE_FORMAT_B8G8R8X8_UNORM:
		876	case PIPE_FORMAT_R8G8B8A8_SNORM:
		877	case PIPE_FORMAT_R8G8B8A8_UNORM:
		878	case PIPE_FORMAT_R8G8B8X8_UNORM:
		879	case PIPE_FORMAT_R8G8B8X8_SNORM:
		880	case PIPE_FORMAT_R8G8B8X8_SRGB:
		881	case PIPE_FORMAT_R8G8B8X8_UINT:
		882	case PIPE_FORMAT_R8G8B8X8_SINT:
		883	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
		884	case PIPE_FORMAT_X8B8G8R8_UNORM:
		885	case PIPE_FORMAT_X8R8G8B8_UNORM:
		886	case PIPE_FORMAT_R8G8B8A8_SSCALED:
		887	case PIPE_FORMAT_R8G8B8A8_USCALED:
		888	case PIPE_FORMAT_R8G8B8A8_SINT:
		889	case PIPE_FORMAT_R8G8B8A8_UINT:
		890	return V_028C70_COLOR_8_8_8_8;
		891
		892	case PIPE_FORMAT_R10G10B10A2_UNORM:
		893	case PIPE_FORMAT_R10G10B10X2_SNORM:
		894	case PIPE_FORMAT_B10G10R10A2_UNORM:
		895	case PIPE_FORMAT_B10G10R10A2_UINT:
		896	case PIPE_FORMAT_B10G10R10X2_UNORM:
		897	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
		898	return V_028C70_COLOR_2_10_10_10;
		899
		900	case PIPE_FORMAT_Z24X8_UNORM:
		901	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		902	return V_028C70_COLOR_8_24;
		903
		904	case PIPE_FORMAT_S8X24_UINT:
		905	case PIPE_FORMAT_X8Z24_UNORM:
		906	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		907	return V_028C70_COLOR_24_8;
		908
		909	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		910	return V_028C70_COLOR_X24_8_32_FLOAT;
		911
		912	case PIPE_FORMAT_I32_FLOAT:
		913	case PIPE_FORMAT_L32_FLOAT:
		914	case PIPE_FORMAT_R32_FLOAT:
		915	case PIPE_FORMAT_A32_FLOAT:
		916	case PIPE_FORMAT_Z32_FLOAT:
		917	return V_028C70_COLOR_32;
		918
		919	case PIPE_FORMAT_L16A16_UNORM:
		920	case PIPE_FORMAT_L16A16_SNORM:
		921	case PIPE_FORMAT_L16A16_FLOAT:
		922	case PIPE_FORMAT_R16G16_SSCALED:
		923	case PIPE_FORMAT_R16G16_UNORM:
		924	case PIPE_FORMAT_R16G16_SNORM:
		925	case PIPE_FORMAT_R16G16_UINT:
		926	case PIPE_FORMAT_R16G16_SINT:
		927	case PIPE_FORMAT_R16G16_FLOAT:
		928	return V_028C70_COLOR_16_16;
		929
		930	case PIPE_FORMAT_R11G11B10_FLOAT:
		931	return V_028C70_COLOR_10_11_11;
		932
		933	/* 64-bit buffers. */
		934	case PIPE_FORMAT_R16G16B16A16_UINT:
		935	case PIPE_FORMAT_R16G16B16A16_SINT:
		936	case PIPE_FORMAT_R16G16B16A16_USCALED:
		937	case PIPE_FORMAT_R16G16B16A16_SSCALED:
		938	case PIPE_FORMAT_R16G16B16A16_UNORM:
		939	case PIPE_FORMAT_R16G16B16A16_SNORM:
		940	case PIPE_FORMAT_R16G16B16A16_FLOAT:
		941	case PIPE_FORMAT_R16G16B16X16_UNORM:
		942	case PIPE_FORMAT_R16G16B16X16_SNORM:
		943	case PIPE_FORMAT_R16G16B16X16_FLOAT:
		944	case PIPE_FORMAT_R16G16B16X16_UINT:
		945	case PIPE_FORMAT_R16G16B16X16_SINT:
		946	return V_028C70_COLOR_16_16_16_16;
		947
		948	case PIPE_FORMAT_L32A32_FLOAT:
		949	case PIPE_FORMAT_L32A32_UINT:
		950	case PIPE_FORMAT_L32A32_SINT:
		951	case PIPE_FORMAT_R32G32_FLOAT:
		952	case PIPE_FORMAT_R32G32_USCALED:
		953	case PIPE_FORMAT_R32G32_SSCALED:
		954	case PIPE_FORMAT_R32G32_SINT:
		955	case PIPE_FORMAT_R32G32_UINT:
		956	return V_028C70_COLOR_32_32;
		957
		958	/* 128-bit buffers. */
		959	case PIPE_FORMAT_R32G32B32A32_SNORM:
		960	case PIPE_FORMAT_R32G32B32A32_UNORM:
		961	case PIPE_FORMAT_R32G32B32A32_SSCALED:
		962	case PIPE_FORMAT_R32G32B32A32_USCALED:
		963	case PIPE_FORMAT_R32G32B32A32_SINT:
		964	case PIPE_FORMAT_R32G32B32A32_UINT:
		965	case PIPE_FORMAT_R32G32B32A32_FLOAT:
		966	case PIPE_FORMAT_R32G32B32X32_FLOAT:
		967	case PIPE_FORMAT_R32G32B32X32_UINT:
		968	case PIPE_FORMAT_R32G32B32X32_SINT:
		969	return V_028C70_COLOR_32_32_32_32;
		970
		971	/* YUV buffers. */
		972	case PIPE_FORMAT_UYVY:
		973	case PIPE_FORMAT_YUYV:
		974	/* 96-bit buffers. */
		975	case PIPE_FORMAT_R32G32B32_FLOAT:
		976	/* 8-bit buffers. */
		977	case PIPE_FORMAT_L4A4_UNORM:
		978	case PIPE_FORMAT_R4A4_UNORM:
		979	case PIPE_FORMAT_A4R4_UNORM:
		980	default:
		981	return V_028C70_COLOR_INVALID; /* Unsupported. */
		982	}
		983	}
		984
		985	static uint32_t si_translate_colorswap(enum pipe_format format)
		986	{
		987	switch (format) {
		988	/* 8-bit buffers. */
		989	case PIPE_FORMAT_L4A4_UNORM:
		990	case PIPE_FORMAT_A4R4_UNORM:
		991	return V_028C70_SWAP_ALT;
		992
		993	case PIPE_FORMAT_A8_UNORM:
		994	case PIPE_FORMAT_A8_SNORM:
		995	case PIPE_FORMAT_A8_UINT:
		996	case PIPE_FORMAT_A8_SINT:
		997	case PIPE_FORMAT_R4A4_UNORM:
		998	return V_028C70_SWAP_ALT_REV;
		999	case PIPE_FORMAT_I8_UNORM:
		1000	case PIPE_FORMAT_I8_SNORM:
		1001	case PIPE_FORMAT_L8_UNORM:
		1002	case PIPE_FORMAT_L8_SNORM:
		1003	case PIPE_FORMAT_I8_UINT:
		1004	case PIPE_FORMAT_I8_SINT:
		1005	case PIPE_FORMAT_L8_UINT:
		1006	case PIPE_FORMAT_L8_SINT:
		1007	case PIPE_FORMAT_L8_SRGB:
		1008	case PIPE_FORMAT_R8_UNORM:
		1009	case PIPE_FORMAT_R8_SNORM:
		1010	case PIPE_FORMAT_R8_UINT:
		1011	case PIPE_FORMAT_R8_SINT:
		1012	return V_028C70_SWAP_STD;
		1013
		1014	/* 16-bit buffers. */
		1015	case PIPE_FORMAT_B5G6R5_UNORM:
		1016	return V_028C70_SWAP_STD_REV;
		1017
		1018	case PIPE_FORMAT_B5G5R5A1_UNORM:
		1019	case PIPE_FORMAT_B5G5R5X1_UNORM:
		1020	return V_028C70_SWAP_ALT;
		1021
		1022	case PIPE_FORMAT_B4G4R4A4_UNORM:
		1023	case PIPE_FORMAT_B4G4R4X4_UNORM:
		1024	return V_028C70_SWAP_ALT;
		1025
		1026	case PIPE_FORMAT_Z16_UNORM:
		1027	return V_028C70_SWAP_STD;
		1028
		1029	case PIPE_FORMAT_L8A8_UNORM:
		1030	case PIPE_FORMAT_L8A8_SNORM:
		1031	case PIPE_FORMAT_L8A8_UINT:
		1032	case PIPE_FORMAT_L8A8_SINT:
		1033	return V_028C70_SWAP_ALT;
		1034	case PIPE_FORMAT_R8G8_SNORM:
		1035	case PIPE_FORMAT_R8G8_UNORM:
		1036	case PIPE_FORMAT_R8G8_UINT:
		1037	case PIPE_FORMAT_R8G8_SINT:
		1038	return V_028C70_SWAP_STD;
		1039
		1040	case PIPE_FORMAT_I16_UNORM:
		1041	case PIPE_FORMAT_I16_SNORM:
		1042	case PIPE_FORMAT_I16_FLOAT:
		1043	case PIPE_FORMAT_L16_UNORM:
		1044	case PIPE_FORMAT_L16_SNORM:
		1045	case PIPE_FORMAT_L16_FLOAT:
		1046	case PIPE_FORMAT_R16_UNORM:
		1047	case PIPE_FORMAT_R16_SNORM:
		1048	case PIPE_FORMAT_R16_UINT:
		1049	case PIPE_FORMAT_R16_SINT:
		1050	case PIPE_FORMAT_R16_FLOAT:
		1051	return V_028C70_SWAP_STD;
		1052
		1053	case PIPE_FORMAT_A16_UNORM:
		1054	case PIPE_FORMAT_A16_SNORM:
		1055	case PIPE_FORMAT_A16_FLOAT:
		1056	return V_028C70_SWAP_ALT_REV;
		1057
		1058	/* 32-bit buffers. */
		1059	case PIPE_FORMAT_A8B8G8R8_SRGB:
		1060	return V_028C70_SWAP_STD_REV;
		1061	case PIPE_FORMAT_B8G8R8A8_SRGB:
		1062	return V_028C70_SWAP_ALT;
		1063
		1064	case PIPE_FORMAT_B8G8R8A8_UNORM:
		1065	case PIPE_FORMAT_B8G8R8X8_UNORM:
		1066	return V_028C70_SWAP_ALT;
		1067
		1068	case PIPE_FORMAT_A8R8G8B8_UNORM:
		1069	case PIPE_FORMAT_X8R8G8B8_UNORM:
		1070	return V_028C70_SWAP_ALT_REV;
		1071	case PIPE_FORMAT_R8G8B8A8_SNORM:
		1072	case PIPE_FORMAT_R8G8B8A8_UNORM:
		1073	case PIPE_FORMAT_R8G8B8A8_SSCALED:
		1074	case PIPE_FORMAT_R8G8B8A8_USCALED:
		1075	case PIPE_FORMAT_R8G8B8A8_SINT:
		1076	case PIPE_FORMAT_R8G8B8A8_UINT:
		1077	case PIPE_FORMAT_R8G8B8X8_UNORM:
		1078	case PIPE_FORMAT_R8G8B8X8_SNORM:
		1079	case PIPE_FORMAT_R8G8B8X8_SRGB:
		1080	case PIPE_FORMAT_R8G8B8X8_UINT:
		1081	case PIPE_FORMAT_R8G8B8X8_SINT:
		1082	return V_028C70_SWAP_STD;
		1083
		1084	case PIPE_FORMAT_A8B8G8R8_UNORM:
		1085	case PIPE_FORMAT_X8B8G8R8_UNORM:
		1086	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
		1087	return V_028C70_SWAP_STD_REV;
		1088
		1089	case PIPE_FORMAT_Z24X8_UNORM:
		1090	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		1091	return V_028C70_SWAP_STD;
		1092
		1093	case PIPE_FORMAT_S8X24_UINT:
		1094	case PIPE_FORMAT_X8Z24_UNORM:
		1095	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		1096	return V_028C70_SWAP_STD_REV;
		1097
		1098	case PIPE_FORMAT_R10G10B10A2_UNORM:
		1099	case PIPE_FORMAT_R10G10B10X2_SNORM:
		1100	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
		1101	return V_028C70_SWAP_STD;
		1102
		1103	case PIPE_FORMAT_B10G10R10A2_UNORM:
		1104	case PIPE_FORMAT_B10G10R10A2_UINT:
		1105	case PIPE_FORMAT_B10G10R10X2_UNORM:
		1106	return V_028C70_SWAP_ALT;
		1107
		1108	case PIPE_FORMAT_R11G11B10_FLOAT:
		1109	case PIPE_FORMAT_I32_FLOAT:
		1110	case PIPE_FORMAT_L32_FLOAT:
		1111	case PIPE_FORMAT_R32_FLOAT:
		1112	case PIPE_FORMAT_R32_UINT:
		1113	case PIPE_FORMAT_R32_SINT:
		1114	case PIPE_FORMAT_Z32_FLOAT:
		1115	case PIPE_FORMAT_R16G16_FLOAT:
		1116	case PIPE_FORMAT_R16G16_UNORM:
		1117	case PIPE_FORMAT_R16G16_SNORM:
		1118	case PIPE_FORMAT_R16G16_UINT:
		1119	case PIPE_FORMAT_R16G16_SINT:
		1120	return V_028C70_SWAP_STD;
		1121
		1122	case PIPE_FORMAT_L16A16_UNORM:
		1123	case PIPE_FORMAT_L16A16_SNORM:
		1124	case PIPE_FORMAT_L16A16_FLOAT:
		1125	return V_028C70_SWAP_ALT;
		1126
		1127	case PIPE_FORMAT_A32_FLOAT:
		1128	return V_028C70_SWAP_ALT_REV;
		1129
		1130	/* 64-bit buffers. */
		1131	case PIPE_FORMAT_R32G32_FLOAT:
		1132	case PIPE_FORMAT_R32G32_UINT:
		1133	case PIPE_FORMAT_R32G32_SINT:
		1134	case PIPE_FORMAT_R16G16B16A16_UNORM:
		1135	case PIPE_FORMAT_R16G16B16A16_SNORM:
		1136	case PIPE_FORMAT_R16G16B16A16_USCALED:
		1137	case PIPE_FORMAT_R16G16B16A16_SSCALED:
		1138	case PIPE_FORMAT_R16G16B16A16_UINT:
		1139	case PIPE_FORMAT_R16G16B16A16_SINT:
		1140	case PIPE_FORMAT_R16G16B16A16_FLOAT:
		1141	case PIPE_FORMAT_R16G16B16X16_UNORM:
		1142	case PIPE_FORMAT_R16G16B16X16_SNORM:
		1143	case PIPE_FORMAT_R16G16B16X16_FLOAT:
		1144	case PIPE_FORMAT_R16G16B16X16_UINT:
		1145	case PIPE_FORMAT_R16G16B16X16_SINT:
		1146	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		1147	return V_028C70_SWAP_STD;
		1148
		1149	case PIPE_FORMAT_L32A32_FLOAT:
		1150	case PIPE_FORMAT_L32A32_UINT:
		1151	case PIPE_FORMAT_L32A32_SINT:
		1152	return V_028C70_SWAP_ALT;
		1153
		1154	/* 128-bit buffers. */
		1155	case PIPE_FORMAT_R32G32B32A32_FLOAT:
		1156	case PIPE_FORMAT_R32G32B32A32_SNORM:
		1157	case PIPE_FORMAT_R32G32B32A32_UNORM:
		1158	case PIPE_FORMAT_R32G32B32A32_SSCALED:
		1159	case PIPE_FORMAT_R32G32B32A32_USCALED:
		1160	case PIPE_FORMAT_R32G32B32A32_SINT:
		1161	case PIPE_FORMAT_R32G32B32A32_UINT:
		1162	case PIPE_FORMAT_R32G32B32X32_FLOAT:
		1163	case PIPE_FORMAT_R32G32B32X32_UINT:
		1164	case PIPE_FORMAT_R32G32B32X32_SINT:
		1165	return V_028C70_SWAP_STD;
		1166	default:
		1167	R600_ERR("unsupported colorswap format %d\n", format);
		1168	return ~0U;
		1169	}
		1170	return ~0U;
		1171	}
		1172
		1173	static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
		1174	{
		1175	if (R600_BIG_ENDIAN) {
		1176	switch(colorformat) {
		1177	/* 8-bit buffers. */
		1178	case V_028C70_COLOR_8:
		1179	return V_028C70_ENDIAN_NONE;
		1180
		1181	/* 16-bit buffers. */
		1182	case V_028C70_COLOR_5_6_5:
		1183	case V_028C70_COLOR_1_5_5_5:
		1184	case V_028C70_COLOR_4_4_4_4:
		1185	case V_028C70_COLOR_16:
		1186	case V_028C70_COLOR_8_8:
		1187	return V_028C70_ENDIAN_8IN16;
		1188
		1189	/* 32-bit buffers. */
		1190	case V_028C70_COLOR_8_8_8_8:
		1191	case V_028C70_COLOR_2_10_10_10:
		1192	case V_028C70_COLOR_8_24:
		1193	case V_028C70_COLOR_24_8:
		1194	case V_028C70_COLOR_16_16:
		1195	return V_028C70_ENDIAN_8IN32;
		1196
		1197	/* 64-bit buffers. */
		1198	case V_028C70_COLOR_16_16_16_16:
		1199	return V_028C70_ENDIAN_8IN16;
		1200
		1201	case V_028C70_COLOR_32_32:
		1202	return V_028C70_ENDIAN_8IN32;
		1203
		1204	/* 128-bit buffers. */
		1205	case V_028C70_COLOR_32_32_32_32:
		1206	return V_028C70_ENDIAN_8IN32;
		1207	default:
		1208	return V_028C70_ENDIAN_NONE; /* Unsupported. */
		1209	}
		1210	} else {
		1211	return V_028C70_ENDIAN_NONE;
		1212	}
		1213	}
		1214
		1215	/* Returns the size in bits of the widest component of a CB format */
		1216	static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
		1217	{
		1218	switch(colorformat) {
		1219	case V_028C70_COLOR_4_4_4_4:
		1220	return 4;
		1221
		1222	case V_028C70_COLOR_1_5_5_5:
		1223	case V_028C70_COLOR_5_5_5_1:
		1224	return 5;
		1225
		1226	case V_028C70_COLOR_5_6_5:
		1227	return 6;
		1228
		1229	case V_028C70_COLOR_8:
		1230	case V_028C70_COLOR_8_8:
		1231	case V_028C70_COLOR_8_8_8_8:
		1232	return 8;
		1233
		1234	case V_028C70_COLOR_10_10_10_2:
		1235	case V_028C70_COLOR_2_10_10_10:
		1236	return 10;
		1237
		1238	case V_028C70_COLOR_10_11_11:
		1239	case V_028C70_COLOR_11_11_10:
		1240	return 11;
		1241
		1242	case V_028C70_COLOR_16:
		1243	case V_028C70_COLOR_16_16:
		1244	case V_028C70_COLOR_16_16_16_16:
		1245	return 16;
		1246
		1247	case V_028C70_COLOR_8_24:
		1248	case V_028C70_COLOR_24_8:
		1249	return 24;
		1250
		1251	case V_028C70_COLOR_32:
		1252	case V_028C70_COLOR_32_32:
		1253	case V_028C70_COLOR_32_32_32_32:
		1254	case V_028C70_COLOR_X24_8_32_FLOAT:
		1255	return 32;
		1256	}
		1257
		1258	assert(!"Unknown maximum component size");
		1259	return 0;
		1260	}
		1261
		1262	static uint32_t si_translate_dbformat(enum pipe_format format)
		1263	{
		1264	switch (format) {
		1265	case PIPE_FORMAT_Z16_UNORM:
		1266	return V_028040_Z_16;
		1267	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		1268	case PIPE_FORMAT_X8Z24_UNORM:
		1269	case PIPE_FORMAT_Z24X8_UNORM:
		1270	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		1271	return V_028040_Z_24; /* deprecated on SI */
		1272	case PIPE_FORMAT_Z32_FLOAT:
		1273	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		1274	return V_028040_Z_32_FLOAT;
		1275	default:
		1276	return V_028040_Z_INVALID;
		1277	}
		1278	}
		1279
		1280	/*
		1281	* Texture translation
		1282	*/
		1283
		1284	static uint32_t si_translate_texformat(struct pipe_screen *screen,
		1285	enum pipe_format format,
		1286	const struct util_format_description *desc,
		1287	int first_non_void)
		1288	{
		1289	struct r600_screen rscreen = (struct r600_screen)screen;
		1290	bool enable_s3tc = rscreen->info.drm_minor >= 31;
		1291	boolean uniform = TRUE;
		1292	int i;
		1293
		1294	/* Colorspace (return non-RGB formats directly). */
		1295	switch (desc->colorspace) {
		1296	/* Depth stencil formats */
		1297	case UTIL_FORMAT_COLORSPACE_ZS:
		1298	switch (format) {
		1299	case PIPE_FORMAT_Z16_UNORM:
		1300	return V_008F14_IMG_DATA_FORMAT_16;
		1301	case PIPE_FORMAT_X24S8_UINT:
		1302	case PIPE_FORMAT_Z24X8_UNORM:
		1303	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		1304	return V_008F14_IMG_DATA_FORMAT_8_24;
		1305	case PIPE_FORMAT_X8Z24_UNORM:
		1306	case PIPE_FORMAT_S8X24_UINT:
		1307	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		1308	return V_008F14_IMG_DATA_FORMAT_24_8;
		1309	case PIPE_FORMAT_S8_UINT:
		1310	return V_008F14_IMG_DATA_FORMAT_8;
		1311	case PIPE_FORMAT_Z32_FLOAT:
		1312	return V_008F14_IMG_DATA_FORMAT_32;
		1313	case PIPE_FORMAT_X32_S8X24_UINT:
		1314	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		1315	return V_008F14_IMG_DATA_FORMAT_X24_8_32;
		1316	default:
		1317	goto out_unknown;
		1318	}
		1319
		1320	case UTIL_FORMAT_COLORSPACE_YUV:
		1321	goto out_unknown; /* TODO */
		1322
		1323	case UTIL_FORMAT_COLORSPACE_SRGB:
		1324	if (desc->nr_channels != 4 && desc->nr_channels != 1)
		1325	goto out_unknown;
		1326	break;
		1327
		1328	default:
		1329	break;
		1330	}
		1331
		1332	if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
		1333	if (!enable_s3tc)
		1334	goto out_unknown;
		1335
		1336	switch (format) {
		1337	case PIPE_FORMAT_RGTC1_SNORM:
		1338	case PIPE_FORMAT_LATC1_SNORM:
		1339	case PIPE_FORMAT_RGTC1_UNORM:
		1340	case PIPE_FORMAT_LATC1_UNORM:
		1341	return V_008F14_IMG_DATA_FORMAT_BC4;
		1342	case PIPE_FORMAT_RGTC2_SNORM:
		1343	case PIPE_FORMAT_LATC2_SNORM:
		1344	case PIPE_FORMAT_RGTC2_UNORM:
		1345	case PIPE_FORMAT_LATC2_UNORM:
		1346	return V_008F14_IMG_DATA_FORMAT_BC5;
		1347	default:
		1348	goto out_unknown;
		1349	}
		1350	}
		1351
		1352	if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
		1353
		1354	if (!enable_s3tc)
		1355	goto out_unknown;
		1356
		1357	if (!util_format_s3tc_enabled) {
		1358	goto out_unknown;
		1359	}
		1360
		1361	switch (format) {
		1362	case PIPE_FORMAT_DXT1_RGB:
		1363	case PIPE_FORMAT_DXT1_RGBA:
		1364	case PIPE_FORMAT_DXT1_SRGB:
		1365	case PIPE_FORMAT_DXT1_SRGBA:
		1366	return V_008F14_IMG_DATA_FORMAT_BC1;
		1367	case PIPE_FORMAT_DXT3_RGBA:
		1368	case PIPE_FORMAT_DXT3_SRGBA:
		1369	return V_008F14_IMG_DATA_FORMAT_BC2;
		1370	case PIPE_FORMAT_DXT5_RGBA:
		1371	case PIPE_FORMAT_DXT5_SRGBA:
		1372	return V_008F14_IMG_DATA_FORMAT_BC3;
		1373	default:
		1374	goto out_unknown;
		1375	}
		1376	}
		1377
		1378	if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
		1379	return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
		1380	} else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
		1381	return V_008F14_IMG_DATA_FORMAT_10_11_11;
		1382	}
		1383
		1384	/* R8G8Bx_SNORM - TODO CxV8U8 */
		1385
		1386	/* See whether the components are of the same size. */
		1387	for (i = 1; i < desc->nr_channels; i++) {
		1388	uniform = uniform && desc->channel[0].size == desc->channel[i].size;
		1389	}
		1390
		1391	/* Non-uniform formats. */
		1392	if (!uniform) {
		1393	switch(desc->nr_channels) {
		1394	case 3:
		1395	if (desc->channel[0].size == 5 &&
		1396	desc->channel[1].size == 6 &&
		1397	desc->channel[2].size == 5) {
		1398	return V_008F14_IMG_DATA_FORMAT_5_6_5;
		1399	}
		1400	goto out_unknown;
		1401	case 4:
		1402	if (desc->channel[0].size == 5 &&
		1403	desc->channel[1].size == 5 &&
		1404	desc->channel[2].size == 5 &&
		1405	desc->channel[3].size == 1) {
		1406	return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
		1407	}
		1408	if (desc->channel[0].size == 10 &&
		1409	desc->channel[1].size == 10 &&
		1410	desc->channel[2].size == 10 &&
		1411	desc->channel[3].size == 2) {
		1412	return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
		1413	}
		1414	goto out_unknown;
		1415	}
		1416	goto out_unknown;
		1417	}
		1418
		1419	if (first_non_void < 0 \|\| first_non_void > 3)
		1420	goto out_unknown;
		1421
		1422	/* uniform formats */
		1423	switch (desc->channel[first_non_void].size) {
		1424	case 4:
		1425	switch (desc->nr_channels) {
		1426	#if 0 /* Not supported for render targets */
		1427	case 2:
		1428	return V_008F14_IMG_DATA_FORMAT_4_4;
		1429	#endif
		1430	case 4:
		1431	return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
		1432	}
		1433	break;
		1434	case 8:
		1435	switch (desc->nr_channels) {
		1436	case 1:
		1437	return V_008F14_IMG_DATA_FORMAT_8;
		1438	case 2:
		1439	return V_008F14_IMG_DATA_FORMAT_8_8;
		1440	case 4:
		1441	return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
		1442	}
		1443	break;
		1444	case 16:
		1445	switch (desc->nr_channels) {
		1446	case 1:
		1447	return V_008F14_IMG_DATA_FORMAT_16;
		1448	case 2:
		1449	return V_008F14_IMG_DATA_FORMAT_16_16;
		1450	case 4:
		1451	return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
		1452	}
		1453	break;
		1454	case 32:
		1455	switch (desc->nr_channels) {
		1456	case 1:
		1457	return V_008F14_IMG_DATA_FORMAT_32;
		1458	case 2:
		1459	return V_008F14_IMG_DATA_FORMAT_32_32;
		1460	#if 0 /* Not supported for render targets */
		1461	case 3:
		1462	return V_008F14_IMG_DATA_FORMAT_32_32_32;
		1463	#endif
		1464	case 4:
		1465	return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
		1466	}
		1467	}
		1468
		1469	out_unknown:
		1470	/* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
		1471	return ~0;
		1472	}
		1473
		1474	static unsigned si_tex_wrap(unsigned wrap)
		1475	{
		1476	switch (wrap) {
		1477	default:
		1478	case PIPE_TEX_WRAP_REPEAT:
		1479	return V_008F30_SQ_TEX_WRAP;
		1480	case PIPE_TEX_WRAP_CLAMP:
		1481	return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
		1482	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
		1483	return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
		1484	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
		1485	return V_008F30_SQ_TEX_CLAMP_BORDER;
		1486	case PIPE_TEX_WRAP_MIRROR_REPEAT:
		1487	return V_008F30_SQ_TEX_MIRROR;
		1488	case PIPE_TEX_WRAP_MIRROR_CLAMP:
		1489	return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
		1490	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
		1491	return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
		1492	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
		1493	return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
		1494	}
		1495	}
		1496
		1497	static unsigned si_tex_filter(unsigned filter)
		1498	{
		1499	switch (filter) {
		1500	default:
		1501	case PIPE_TEX_FILTER_NEAREST:
		1502	return V_008F38_SQ_TEX_XY_FILTER_POINT;
		1503	case PIPE_TEX_FILTER_LINEAR:
		1504	return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
		1505	}
		1506	}
		1507
		1508	static unsigned si_tex_mipfilter(unsigned filter)
		1509	{
		1510	switch (filter) {
		1511	case PIPE_TEX_MIPFILTER_NEAREST:
		1512	return V_008F38_SQ_TEX_Z_FILTER_POINT;
		1513	case PIPE_TEX_MIPFILTER_LINEAR:
		1514	return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
		1515	default:
		1516	case PIPE_TEX_MIPFILTER_NONE:
		1517	return V_008F38_SQ_TEX_Z_FILTER_NONE;
		1518	}
		1519	}
		1520
		1521	static unsigned si_tex_compare(unsigned compare)
		1522	{
		1523	switch (compare) {
		1524	default:
		1525	case PIPE_FUNC_NEVER:
		1526	return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
		1527	case PIPE_FUNC_LESS:
		1528	return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
		1529	case PIPE_FUNC_EQUAL:
		1530	return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
		1531	case PIPE_FUNC_LEQUAL:
		1532	return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
		1533	case PIPE_FUNC_GREATER:
		1534	return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
		1535	case PIPE_FUNC_NOTEQUAL:
		1536	return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
		1537	case PIPE_FUNC_GEQUAL:
		1538	return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
		1539	case PIPE_FUNC_ALWAYS:
		1540	return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
		1541	}
		1542	}
		1543
		1544	static unsigned si_tex_dim(unsigned dim)
		1545	{
		1546	switch (dim) {
		1547	default:
		1548	case PIPE_TEXTURE_1D:
		1549	return V_008F1C_SQ_RSRC_IMG_1D;
		1550	case PIPE_TEXTURE_1D_ARRAY:
		1551	return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
		1552	case PIPE_TEXTURE_2D:
		1553	case PIPE_TEXTURE_RECT:
		1554	return V_008F1C_SQ_RSRC_IMG_2D;
		1555	case PIPE_TEXTURE_2D_ARRAY:
		1556	return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
		1557	case PIPE_TEXTURE_3D:
		1558	return V_008F1C_SQ_RSRC_IMG_3D;
		1559	case PIPE_TEXTURE_CUBE:
		1560	return V_008F1C_SQ_RSRC_IMG_CUBE;
		1561	}
		1562	}
		1563
		1564	/*
		1565	* Format support testing
		1566	*/
		1567
		1568	static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
		1569	{
		1570	return si_translate_texformat(screen, format, util_format_description(format),
		1571	util_format_get_first_non_void_channel(format)) != ~0U;
		1572	}
		1573
		1574	static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
		1575	enum pipe_format format,
		1576	const struct util_format_description *desc,
		1577	int first_non_void)
		1578	{
		1579	unsigned type = desc->channel[first_non_void].type;
		1580	int i;
		1581
		1582	if (type == UTIL_FORMAT_TYPE_FIXED)
		1583	return V_008F0C_BUF_DATA_FORMAT_INVALID;
		1584
		1585	/* See whether the components are of the same size. */
		1586	for (i = 0; i < desc->nr_channels; i++) {
		1587	if (desc->channel[first_non_void].size != desc->channel[i].size)
		1588	return V_008F0C_BUF_DATA_FORMAT_INVALID;
		1589	}
		1590
		1591	switch (desc->channel[first_non_void].size) {
		1592	case 8:
		1593	switch (desc->nr_channels) {
		1594	case 1:
		1595	return V_008F0C_BUF_DATA_FORMAT_8;
		1596	case 2:
		1597	return V_008F0C_BUF_DATA_FORMAT_8_8;
		1598	case 3:
		1599	case 4:
		1600	return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
		1601	}
		1602	break;
		1603	case 16:
		1604	switch (desc->nr_channels) {
		1605	case 1:
		1606	return V_008F0C_BUF_DATA_FORMAT_16;
		1607	case 2:
		1608	return V_008F0C_BUF_DATA_FORMAT_16_16;
		1609	case 3:
		1610	case 4:
		1611	return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
		1612	}
		1613	break;
		1614	case 32:
		1615	if (type != UTIL_FORMAT_TYPE_FLOAT)
		1616	return V_008F0C_BUF_DATA_FORMAT_INVALID;
		1617
		1618	switch (desc->nr_channels) {
		1619	case 1:
		1620	return V_008F0C_BUF_DATA_FORMAT_32;
		1621	case 2:
		1622	return V_008F0C_BUF_DATA_FORMAT_32_32;
		1623	case 3:
		1624	return V_008F0C_BUF_DATA_FORMAT_32_32_32;
		1625	case 4:
		1626	return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
		1627	}
		1628	break;
		1629	}
		1630
		1631	return V_008F0C_BUF_DATA_FORMAT_INVALID;
		1632	}
		1633
		1634	static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
		1635	{
		1636	const struct util_format_description *desc;
		1637	int first_non_void;
		1638	unsigned data_format;
		1639
		1640	desc = util_format_description(format);
		1641	first_non_void = util_format_get_first_non_void_channel(format);
		1642	data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
		1643	return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
		1644	}
		1645
		1646	static bool si_is_colorbuffer_format_supported(enum pipe_format format)
		1647	{
		1648	return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
		1649	si_translate_colorswap(format) != ~0U;
		1650	}
		1651
		1652	static bool si_is_zs_format_supported(enum pipe_format format)
		1653	{
		1654	return si_translate_dbformat(format) != V_028040_Z_INVALID;
		1655	}
		1656
		1657	boolean si_is_format_supported(struct pipe_screen *screen,
		1658	enum pipe_format format,
		1659	enum pipe_texture_target target,
		1660	unsigned sample_count,
		1661	unsigned usage)
		1662	{
		1663	unsigned retval = 0;
		1664
		1665	if (target >= PIPE_MAX_TEXTURE_TYPES) {
		1666	R600_ERR("r600: unsupported texture type %d\n", target);
		1667	return FALSE;
		1668	}
		1669
		1670	if (!util_format_is_supported(format, usage))
		1671	return FALSE;
		1672
		1673	/* Multisample */
		1674	if (sample_count > 1)
		1675	return FALSE;
		1676
		1677	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
		1678	si_is_sampler_format_supported(screen, format)) {
		1679	retval \|= PIPE_BIND_SAMPLER_VIEW;
		1680	}
		1681
		1682	if ((usage & (PIPE_BIND_RENDER_TARGET \|
		1683	PIPE_BIND_DISPLAY_TARGET \|
		1684	PIPE_BIND_SCANOUT \|
		1685	PIPE_BIND_SHARED)) &&
		1686	si_is_colorbuffer_format_supported(format)) {
		1687	retval \|= usage &
		1688	(PIPE_BIND_RENDER_TARGET \|
		1689	PIPE_BIND_DISPLAY_TARGET \|
		1690	PIPE_BIND_SCANOUT \|
		1691	PIPE_BIND_SHARED);
		1692	}
		1693
		1694	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
		1695	si_is_zs_format_supported(format)) {
		1696	retval \|= PIPE_BIND_DEPTH_STENCIL;
		1697	}
		1698
		1699	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
		1700	si_is_vertex_format_supported(screen, format)) {
		1701	retval \|= PIPE_BIND_VERTEX_BUFFER;
		1702	}
		1703
		1704	if (usage & PIPE_BIND_TRANSFER_READ)
		1705	retval \|= PIPE_BIND_TRANSFER_READ;
		1706	if (usage & PIPE_BIND_TRANSFER_WRITE)
		1707	retval \|= PIPE_BIND_TRANSFER_WRITE;
		1708
		1709	return retval == usage;
		1710	}
		1711
		1712	static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil)
		1713	{
		1714	unsigned tile_mode_index = 0;
		1715
		1716	if (stencil) {
		1717	tile_mode_index = rtex->surface.stencil_tiling_index[level];
		1718	} else {
		1719	tile_mode_index = rtex->surface.tiling_index[level];
		1720	}
		1721	return tile_mode_index;
		1722	}
		1723
		1724	/*
		1725	* framebuffer handling
		1726	*/
		1727
		1728	static void si_cb(struct r600_context rctx, struct si_pm4_state pm4,
		1729	const struct pipe_framebuffer_state *state, int cb)
		1730	{
		1731	struct r600_resource_texture *rtex;
		1732	struct r600_surface *surf;
		1733	unsigned level = state->cbufs[cb]->u.tex.level;
		1734	unsigned pitch, slice;
		1735	unsigned color_info, color_attrib;
		1736	unsigned tile_mode_index;
		1737	unsigned format, swap, ntype, endian;
		1738	uint64_t offset;
		1739	const struct util_format_description *desc;
		1740	int i;
		1741	unsigned blend_clamp = 0, blend_bypass = 0;
		1742	unsigned max_comp_size;
		1743
		1744	surf = (struct r600_surface *)state->cbufs[cb];
		1745	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
		1746
		1747	offset = rtex->surface.level[level].offset;
		1748	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
		1749	offset += rtex->surface.level[level].slice_size *
		1750	state->cbufs[cb]->u.tex.first_layer;
		1751	}
		1752	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
		1753	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
		1754	if (slice) {
		1755	slice = slice - 1;
		1756	}
		1757
		1758	tile_mode_index = si_tile_mode_index(rtex, level, false);
		1759
		1760	desc = util_format_description(surf->base.format);
		1761	for (i = 0; i < 4; i++) {
		1762	if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
		1763	break;
		1764	}
		1765	}
		1766	if (i == 4 \|\| desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
		1767	ntype = V_028C70_NUMBER_FLOAT;
		1768	} else {
		1769	ntype = V_028C70_NUMBER_UNORM;
		1770	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
		1771	ntype = V_028C70_NUMBER_SRGB;
		1772	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
		1773	if (desc->channel[i].pure_integer) {
		1774	ntype = V_028C70_NUMBER_SINT;
		1775	} else {
		1776	assert(desc->channel[i].normalized);
		1777	ntype = V_028C70_NUMBER_SNORM;
		1778	}
		1779	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
		1780	if (desc->channel[i].pure_integer) {
		1781	ntype = V_028C70_NUMBER_UINT;
		1782	} else {
		1783	assert(desc->channel[i].normalized);
		1784	ntype = V_028C70_NUMBER_UNORM;
		1785	}
		1786	}
		1787	}
		1788
		1789	format = si_translate_colorformat(surf->base.format);
		1790	if (format == V_028C70_COLOR_INVALID) {
		1791	R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
		1792	}
		1793	assert(format != V_028C70_COLOR_INVALID);
		1794	swap = si_translate_colorswap(surf->base.format);
		1795	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
		1796	endian = V_028C70_ENDIAN_NONE;
		1797	} else {
		1798	endian = si_colorformat_endian_swap(format);
		1799	}
		1800
		1801	/* blend clamp should be set for all NORM/SRGB types */
		1802	if (ntype == V_028C70_NUMBER_UNORM \|\|
		1803	ntype == V_028C70_NUMBER_SNORM \|\|
		1804	ntype == V_028C70_NUMBER_SRGB)
		1805	blend_clamp = 1;
		1806
		1807	/* set blend bypass according to docs if SINT/UINT or
		1808	8/24 COLOR variants */
		1809	if (ntype == V_028C70_NUMBER_UINT \|\| ntype == V_028C70_NUMBER_SINT \|\|
		1810	format == V_028C70_COLOR_8_24 \|\| format == V_028C70_COLOR_24_8 \|\|
		1811	format == V_028C70_COLOR_X24_8_32_FLOAT) {
		1812	blend_clamp = 0;
		1813	blend_bypass = 1;
		1814	}
		1815
		1816	color_info = S_028C70_FORMAT(format) \|
		1817	S_028C70_COMP_SWAP(swap) \|
		1818	S_028C70_BLEND_CLAMP(blend_clamp) \|
		1819	S_028C70_BLEND_BYPASS(blend_bypass) \|
		1820	S_028C70_NUMBER_TYPE(ntype) \|
		1821	S_028C70_ENDIAN(endian);
		1822
		1823	color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) \|
		1824	S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
		1825
		1826	offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
		1827	offset >>= 8;
		1828
		1829	/* FIXME handle enabling of CB beyond BASE8 which has different offset */
		1830	si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
		1831	si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
		1832	si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
		1833	si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
		1834
		1835	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
		1836	si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
		1837	} else {
		1838	si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
		1839	S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) \|
		1840	S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
		1841	}
		1842	si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
		1843	si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
		1844
		1845	/* set CB_COLOR1_INFO for possible dual-src blending */
		1846	if (state->nr_cbufs == 1) {
		1847	assert(cb == 0);
		1848	si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
		1849	}
		1850
		1851	/* Determine pixel shader export format */
		1852	max_comp_size = si_colorformat_max_comp_size(format);
		1853	if (ntype == V_028C70_NUMBER_SRGB \|\|
		1854	((ntype == V_028C70_NUMBER_UNORM \|\| ntype == V_028C70_NUMBER_SNORM) &&
		1855	max_comp_size <= 10) \|\|
		1856	(ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
		1857	rctx->export_16bpc \|= 1 << cb;
		1858	/* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
		1859	if (state->nr_cbufs == 1)
		1860	rctx->export_16bpc \|= 1 << 1;
		1861	}
		1862	}
		1863
		1864	static void si_db(struct r600_context rctx, struct si_pm4_state pm4,
		1865	const struct pipe_framebuffer_state *state)
		1866	{
		1867	struct r600_screen *rscreen = rctx->screen;
		1868	struct r600_resource_texture *rtex;
		1869	struct r600_surface *surf;
		1870	unsigned level, pitch, slice, format, tile_mode_index, array_mode;
		1871	unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
		1872	uint32_t z_info, s_info, db_depth_info;
		1873	uint64_t z_offs, s_offs;
		1874
		1875	if (state->zsbuf == NULL) {
		1876	si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
		1877	si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
		1878	return;
		1879	}
		1880
		1881	surf = (struct r600_surface *)state->zsbuf;
		1882	level = surf->base.u.tex.level;
		1883	rtex = (struct r600_resource_texture*)surf->base.texture;
		1884
		1885	format = si_translate_dbformat(rtex->real_format);
		1886
		1887	if (format == V_028040_Z_INVALID) {
		1888	R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
		1889	}
		1890	assert(format != V_028040_Z_INVALID);
		1891
		1892	s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
		1893	z_offs += rtex->surface.level[level].offset;
		1894	s_offs += rtex->surface.stencil_level[level].offset;
		1895
		1896	z_offs >>= 8;
		1897	s_offs >>= 8;
		1898
		1899	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
		1900	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
		1901	if (slice) {
		1902	slice = slice - 1;
		1903	}
		1904
		1905	db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
		1906
		1907	z_info = S_028040_FORMAT(format);
		1908	if (rtex->surface.flags & RADEON_SURF_SBUFFER)
		1909	s_info = S_028044_FORMAT(V_028044_STENCIL_8);
		1910	else
		1911	s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
		1912
		1913	if (rctx->chip_class >= CIK) {
		1914	switch (rtex->surface.level[level].mode) {
		1915	case RADEON_SURF_MODE_2D:
		1916	array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
		1917	break;
		1918	case RADEON_SURF_MODE_1D:
		1919	case RADEON_SURF_MODE_LINEAR_ALIGNED:
		1920	case RADEON_SURF_MODE_LINEAR:
		1921	default:
		1922	array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
		1923	break;
		1924	}
		1925	tile_split = rtex->surface.tile_split;
		1926	stile_split = rtex->surface.stencil_tile_split;
		1927	macro_aspect = rtex->surface.mtilea;
		1928	bankw = rtex->surface.bankw;
		1929	bankh = rtex->surface.bankh;
		1930	tile_split = cik_tile_split(tile_split);
		1931	stile_split = cik_tile_split(stile_split);
		1932	macro_aspect = cik_macro_tile_aspect(macro_aspect);
		1933	bankw = cik_bank_wh(bankw);
		1934	bankh = cik_bank_wh(bankh);
		1935	nbanks = cik_num_banks(rscreen->tiling_info.num_banks);
		1936	pipe_config = cik_db_pipe_config(rscreen->info.r600_num_tile_pipes,
		1937	rscreen->info.r600_num_backends);
		1938
		1939	db_depth_info \|= S_02803C_ARRAY_MODE(array_mode) \|
		1940	S_02803C_PIPE_CONFIG(pipe_config) \|
		1941	S_02803C_BANK_WIDTH(bankw) \|
		1942	S_02803C_BANK_HEIGHT(bankh) \|
		1943	S_02803C_MACRO_TILE_ASPECT(macro_aspect) \|
		1944	S_02803C_NUM_BANKS(nbanks);
		1945	z_info \|= S_028040_TILE_SPLIT(tile_split);
		1946	s_info \|= S_028044_TILE_SPLIT(stile_split);
		1947	} else {
		1948	tile_mode_index = si_tile_mode_index(rtex, level, false);
		1949	z_info \|= S_028040_TILE_MODE_INDEX(tile_mode_index);
		1950	tile_mode_index = si_tile_mode_index(rtex, level, true);
		1951	s_info \|= S_028044_TILE_MODE_INDEX(tile_mode_index);
		1952	}
		1953
		1954	si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
		1955	S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) \|
		1956	S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
		1957
		1958	si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
		1959	si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
		1960	si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
		1961
		1962	si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
		1963	si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
		1964	si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
		1965	si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
		1966	si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
		1967
		1968	si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
		1969	si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
		1970	}
		1971
		1972	static void si_set_framebuffer_state(struct pipe_context *ctx,
		1973	const struct pipe_framebuffer_state *state)
		1974	{
		1975	struct r600_context rctx = (struct r600_context )ctx;
		1976	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		1977	uint32_t tl, br;
		1978	int tl_x, tl_y, br_x, br_y;
		1979
		1980	if (pm4 == NULL)
		1981	return;
		1982
		1983	si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
		1984
		1985	if (state->zsbuf)
		1986	si_pm4_inval_zsbuf_cache(pm4);
		1987
		1988	util_copy_framebuffer_state(&rctx->framebuffer, state);
		1989
		1990	/* build states */
		1991	rctx->export_16bpc = 0;
		1992	for (int i = 0; i < state->nr_cbufs; i++) {
		1993	si_cb(rctx, pm4, state, i);
		1994	}
		1995	assert(!(rctx->export_16bpc & ~0xff));
		1996	si_db(rctx, pm4, state);
		1997
		1998	tl_x = 0;
		1999	tl_y = 0;
		2000	br_x = state->width;
		2001	br_y = state->height;
		2002
		2003	tl = S_028240_TL_X(tl_x) \| S_028240_TL_Y(tl_y);
		2004	br = S_028244_BR_X(br_x) \| S_028244_BR_Y(br_y);
		2005
		2006	si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
		2007	si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
		2008	si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
		2009	si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
		2010	si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
		2011	si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
		2012	si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
		2013	si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
		2014	si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
		2015	si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
		2016	si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
		2017
		2018	si_pm4_set_state(rctx, framebuffer, pm4);
		2019	si_update_fb_rs_state(rctx);
		2020	si_update_fb_blend_state(rctx);
		2021	}
		2022
		2023	/*
		2024	* shaders
		2025	*/
		2026
		2027	/* Compute the key for the hw shader variant */
		2028	static INLINE void si_shader_selector_key(struct pipe_context *ctx,
		2029	struct si_pipe_shader_selector *sel,
		2030	union si_shader_key *key)
		2031	{
		2032	struct r600_context rctx = (struct r600_context )ctx;
		2033	memset(key, 0, sizeof(*key));
		2034
		2035	if (sel->type == PIPE_SHADER_VERTEX) {
		2036	unsigned i;
		2037	if (!rctx->vertex_elements)
		2038	return;
		2039
		2040	for (i = 0; i < rctx->vertex_elements->count; ++i)
		2041	key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
		2042
		2043	} else if (sel->type == PIPE_SHADER_FRAGMENT) {
		2044	if (sel->fs_write_all)
		2045	key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
		2046	key->ps.export_16bpc = rctx->export_16bpc;
		2047	if (rctx->queued.named.rasterizer) {
		2048	key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
		2049	key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
		2050	}
		2051	if (rctx->queued.named.dsa) {
		2052	key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
		2053	key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
		2054	} else {
		2055	key->ps.alpha_func = PIPE_FUNC_ALWAYS;
		2056	}
		2057	}
		2058	}
		2059
		2060	/* Select the hw shader variant depending on the current state.
		2061	* (dirty) is set to 1 if current variant was changed /
		2062	int si_shader_select(struct pipe_context *ctx,
		2063	struct si_pipe_shader_selector *sel,
		2064	unsigned *dirty)
		2065	{
		2066	union si_shader_key key;
		2067	struct si_pipe_shader * shader = NULL;
		2068	int r;
		2069
		2070	si_shader_selector_key(ctx, sel, &key);
		2071
		2072	/* Check if we don't need to change anything.
		2073	* This path is also used for most shaders that don't need multiple
		2074	* variants, it will cost just a computation of the key and this
		2075	* test. */
		2076	if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
		2077	return 0;
		2078	}
		2079
		2080	/* lookup if we have other variants in the list */
		2081	if (sel->num_shaders > 1) {
		2082	struct si_pipe_shader p = sel->current, c = p->next_variant;
		2083
		2084	while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
		2085	p = c;
		2086	c = c->next_variant;
		2087	}
		2088
		2089	if (c) {
		2090	p->next_variant = c->next_variant;
		2091	shader = c;
		2092	}
		2093	}
		2094
		2095	if (unlikely(!shader)) {
		2096	shader = CALLOC(1, sizeof(struct si_pipe_shader));
		2097	shader->selector = sel;
		2098	shader->key = key;
		2099
		2100	r = si_pipe_shader_create(ctx, shader);
		2101	if (unlikely(r)) {
		2102	R600_ERR("Failed to build shader variant (type=%u) %d\n",
		2103	sel->type, r);
		2104	sel->current = NULL;
		2105	FREE(shader);
		2106	return r;
		2107	}
		2108
		2109	/* We don't know the value of fs_write_all property until we built
		2110	* at least one variant, so we may need to recompute the key (include
		2111	* rctx->framebuffer.nr_cbufs) after building first variant. */
		2112	if (sel->type == PIPE_SHADER_FRAGMENT &&
		2113	sel->num_shaders == 0 &&
		2114	shader->shader.fs_write_all) {
		2115	sel->fs_write_all = 1;
		2116	si_shader_selector_key(ctx, sel, &shader->key);
		2117	}
		2118
		2119	sel->num_shaders++;
		2120	}
		2121
		2122	if (dirty)
		2123	*dirty = 1;
		2124
		2125	shader->next_variant = sel->current;
		2126	sel->current = shader;
		2127
		2128	return 0;
		2129	}
		2130
		2131	static void si_create_shader_state(struct pipe_context ctx,
		2132	const struct pipe_shader_state *state,
		2133	unsigned pipe_shader_type)
		2134	{
		2135	struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
		2136	int r;
		2137
		2138	sel->type = pipe_shader_type;
		2139	sel->tokens = tgsi_dup_tokens(state->tokens);
		2140	sel->so = state->stream_output;
		2141
		2142	r = si_shader_select(ctx, sel, NULL);
		2143	if (r) {
		2144	free(sel);
		2145	return NULL;
		2146	}
		2147
		2148	return sel;
		2149	}
		2150
		2151	static void si_create_fs_state(struct pipe_context ctx,
		2152	const struct pipe_shader_state *state)
		2153	{
		2154	return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
		2155	}
		2156
		2157	static void si_create_vs_state(struct pipe_context ctx,
		2158	const struct pipe_shader_state *state)
		2159	{
		2160	return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
		2161	}
		2162
		2163	static void si_bind_vs_shader(struct pipe_context ctx, void state)
		2164	{
		2165	struct r600_context rctx = (struct r600_context )ctx;
		2166	struct si_pipe_shader_selector *sel = state;
		2167
		2168	if (rctx->vs_shader == sel)
		2169	return;
		2170
		2171	rctx->vs_shader = sel;
		2172
		2173	if (sel && sel->current)
		2174	si_pm4_bind_state(rctx, vs, sel->current->pm4);
		2175	else
		2176	si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
		2177	}
		2178
		2179	static void si_bind_ps_shader(struct pipe_context ctx, void state)
		2180	{
		2181	struct r600_context rctx = (struct r600_context )ctx;
		2182	struct si_pipe_shader_selector *sel = state;
		2183
		2184	if (rctx->ps_shader == sel)
		2185	return;
		2186
		2187	rctx->ps_shader = sel;
		2188
		2189	if (sel && sel->current)
		2190	si_pm4_bind_state(rctx, ps, sel->current->pm4);
		2191	else
		2192	si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
		2193	}
		2194
		2195	static void si_delete_shader_selector(struct pipe_context *ctx,
		2196	struct si_pipe_shader_selector *sel)
		2197	{
		2198	struct r600_context rctx = (struct r600_context )ctx;
		2199	struct si_pipe_shader p = sel->current, c;
		2200
		2201	while (p) {
		2202	c = p->next_variant;
		2203	si_pm4_delete_state(rctx, vs, p->pm4);
		2204	si_pipe_shader_destroy(ctx, p);
		2205	free(p);
		2206	p = c;
		2207	}
		2208
		2209	free(sel->tokens);
		2210	free(sel);
		2211	}
		2212
		2213	static void si_delete_vs_shader(struct pipe_context ctx, void state)
		2214	{
		2215	struct r600_context rctx = (struct r600_context )ctx;
		2216	struct si_pipe_shader_selector sel = (struct si_pipe_shader_selector )state;
		2217
		2218	if (rctx->vs_shader == sel) {
		2219	rctx->vs_shader = NULL;
		2220	}
		2221
		2222	si_delete_shader_selector(ctx, sel);
		2223	}
		2224
		2225	static void si_delete_ps_shader(struct pipe_context ctx, void state)
		2226	{
		2227	struct r600_context rctx = (struct r600_context )ctx;
		2228	struct si_pipe_shader_selector sel = (struct si_pipe_shader_selector )state;
		2229
		2230	if (rctx->ps_shader == sel) {
		2231	rctx->ps_shader = NULL;
		2232	}
		2233
		2234	si_delete_shader_selector(ctx, sel);
		2235	}
		2236
		2237	/*
		2238	* Samplers
		2239	*/
		2240
		2241	static struct pipe_sampler_view si_create_sampler_view(struct pipe_context ctx,
		2242	struct pipe_resource *texture,
		2243	const struct pipe_sampler_view *state)
		2244	{
		2245	struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
		2246	struct r600_resource_texture tmp = (struct r600_resource_texture)texture;
		2247	const struct util_format_description *desc;
		2248	unsigned format, num_format;
		2249	uint32_t pitch = 0;
		2250	unsigned char state_swizzle[4], swizzle[4];
		2251	unsigned height, depth, width;
		2252	enum pipe_format pipe_format = state->format;
		2253	struct radeon_surface_level *surflevel;
		2254	int first_non_void;
		2255	uint64_t va;
		2256
		2257	if (view == NULL)
		2258	return NULL;
		2259
		2260	/* initialize base object */
		2261	view->base = *state;
		2262	view->base.texture = NULL;
		2263	pipe_reference(NULL, &texture->reference);
		2264	view->base.texture = texture;
		2265	view->base.reference.count = 1;
		2266	view->base.context = ctx;
		2267
		2268	state_swizzle[0] = state->swizzle_r;
		2269	state_swizzle[1] = state->swizzle_g;
		2270	state_swizzle[2] = state->swizzle_b;
		2271	state_swizzle[3] = state->swizzle_a;
		2272
		2273	surflevel = tmp->surface.level;
		2274
		2275	/* Texturing with separate depth and stencil. */
		2276	if (tmp->is_depth && !tmp->is_flushing_texture) {
		2277	switch (pipe_format) {
		2278	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		2279	pipe_format = PIPE_FORMAT_Z32_FLOAT;
		2280	break;
		2281	case PIPE_FORMAT_X8Z24_UNORM:
		2282	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		2283	/* Z24 is always stored like this. */
		2284	pipe_format = PIPE_FORMAT_Z24X8_UNORM;
		2285	break;
		2286	case PIPE_FORMAT_X24S8_UINT:
		2287	case PIPE_FORMAT_S8X24_UINT:
		2288	case PIPE_FORMAT_X32_S8X24_UINT:
		2289	pipe_format = PIPE_FORMAT_S8_UINT;
		2290	surflevel = tmp->surface.stencil_level;
		2291	break;
		2292	default:;
		2293	}
		2294	}
		2295
		2296	desc = util_format_description(pipe_format);
		2297
		2298	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
		2299	const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
		2300	const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
		2301
		2302	switch (pipe_format) {
		2303	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		2304	case PIPE_FORMAT_X24S8_UINT:
		2305	case PIPE_FORMAT_X32_S8X24_UINT:
		2306	case PIPE_FORMAT_X8Z24_UNORM:
		2307	util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
		2308	break;
		2309	default:
		2310	util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
		2311	}
		2312	} else {
		2313	util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
		2314	}
		2315
		2316	first_non_void = util_format_get_first_non_void_channel(pipe_format);
		2317
		2318	switch (pipe_format) {
		2319	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		2320	num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
		2321	break;
		2322	default:
		2323	if (first_non_void < 0) {
		2324	if (util_format_is_compressed(pipe_format)) {
		2325	switch (pipe_format) {
		2326	case PIPE_FORMAT_DXT1_SRGB:
		2327	case PIPE_FORMAT_DXT1_SRGBA:
		2328	case PIPE_FORMAT_DXT3_SRGBA:
		2329	case PIPE_FORMAT_DXT5_SRGBA:
		2330	num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
		2331	break;
		2332	case PIPE_FORMAT_RGTC1_SNORM:
		2333	case PIPE_FORMAT_LATC1_SNORM:
		2334	case PIPE_FORMAT_RGTC2_SNORM:
		2335	case PIPE_FORMAT_LATC2_SNORM:
		2336	num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
		2337	break;
		2338	default:
		2339	num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
		2340	break;
		2341	}
		2342	} else {
		2343	num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
		2344	}
		2345	} else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
		2346	num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
		2347	} else {
		2348	num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
		2349
		2350	switch (desc->channel[first_non_void].type) {
		2351	case UTIL_FORMAT_TYPE_FLOAT:
		2352	num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
		2353	break;
		2354	case UTIL_FORMAT_TYPE_SIGNED:
		2355	if (desc->channel[first_non_void].normalized)
		2356	num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
		2357	else if (desc->channel[first_non_void].pure_integer)
		2358	num_format = V_008F14_IMG_NUM_FORMAT_SINT;
		2359	else
		2360	num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
		2361	break;
		2362	case UTIL_FORMAT_TYPE_UNSIGNED:
		2363	if (desc->channel[first_non_void].normalized)
		2364	num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
		2365	else if (desc->channel[first_non_void].pure_integer)
		2366	num_format = V_008F14_IMG_NUM_FORMAT_UINT;
		2367	else
		2368	num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
		2369	}
		2370	}
		2371	}
		2372
		2373	format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
		2374	if (format == ~0) {
		2375	format = 0;
		2376	}
		2377
		2378	view->resource = &tmp->resource;
		2379
		2380	/* not supported any more */
		2381	//endian = si_colorformat_endian_swap(format);
		2382
		2383	width = surflevel[0].npix_x;
		2384	height = surflevel[0].npix_y;
		2385	depth = surflevel[0].npix_z;
		2386	pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
		2387
		2388	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
		2389	height = 1;
		2390	depth = texture->array_size;
		2391	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
		2392	depth = texture->array_size;
		2393	}
		2394
		2395	va = r600_resource_va(ctx->screen, texture);
		2396	va += surflevel[0].offset;
4401	Serge	2397	va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
4358	Serge	2398	view->state[0] = va >> 8;
		2399	view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) \|
		2400	S_008F14_DATA_FORMAT(format) \|
		2401	S_008F14_NUM_FORMAT(num_format));
		2402	view->state[2] = (S_008F18_WIDTH(width - 1) \|
		2403	S_008F18_HEIGHT(height - 1));
		2404	view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) \|
		2405	S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) \|
		2406	S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) \|
		2407	S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) \|
4401	Serge	2408	S_008F1C_BASE_LEVEL(state->u.tex.first_level - tmp->mipmap_shift) \|
		2409	S_008F1C_LAST_LEVEL(state->u.tex.last_level - tmp->mipmap_shift) \|
4358	Serge	2410	S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) \|
		2411	S_008F1C_POW2_PAD(texture->last_level > 0) \|
		2412	S_008F1C_TYPE(si_tex_dim(texture->target)));
		2413	view->state[4] = (S_008F20_DEPTH(depth - 1) \| S_008F20_PITCH(pitch - 1));
		2414	view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) \|
		2415	S_008F24_LAST_ARRAY(state->u.tex.last_layer));
		2416	view->state[6] = 0;
		2417	view->state[7] = 0;
		2418
		2419	return &view->base;
		2420	}
		2421
		2422	static void si_sampler_view_destroy(struct pipe_context *ctx,
		2423	struct pipe_sampler_view *state)
		2424	{
		2425	struct r600_pipe_sampler_view resource = (struct r600_pipe_sampler_view )state;
		2426
		2427	pipe_resource_reference(&state->texture, NULL);
		2428	FREE(resource);
		2429	}
		2430
		2431	static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
		2432	{
		2433	return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER \|\|
		2434	wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER \|\|
		2435	(linear_filter &&
		2436	(wrap == PIPE_TEX_WRAP_CLAMP \|\|
		2437	wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
		2438	}
		2439
		2440	static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
		2441	{
		2442	bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST \|\|
		2443	state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
		2444
		2445	return (state->border_color.ui[0] \|\| state->border_color.ui[1] \|\|
		2446	state->border_color.ui[2] \|\| state->border_color.ui[3]) &&
		2447	(wrap_mode_uses_border_color(state->wrap_s, linear_filter) \|\|
		2448	wrap_mode_uses_border_color(state->wrap_t, linear_filter) \|\|
		2449	wrap_mode_uses_border_color(state->wrap_r, linear_filter));
		2450	}
		2451
		2452	static void si_create_sampler_state(struct pipe_context ctx,
		2453	const struct pipe_sampler_state *state)
		2454	{
		2455	struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
		2456	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
		2457	unsigned border_color_type;
		2458
		2459	if (rstate == NULL) {
		2460	return NULL;
		2461	}
		2462
		2463	if (sampler_state_needs_border_color(state))
		2464	border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
		2465	else
		2466	border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
		2467
		2468	rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) \|
		2469	S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) \|
		2470	S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) \|
		2471	(state->max_anisotropy & 0x7) << 9 \| /* XXX */
		2472	S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) \|
		2473	S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) \|
		2474	aniso_flag_offset << 16 \| /* XXX */
		2475	S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
		2476	rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) \|
		2477	S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
		2478	rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) \|
		2479	S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) \|
		2480	S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) \|
		2481	S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
		2482	rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
		2483
		2484	if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
		2485	memcpy(rstate->border_color, state->border_color.ui,
		2486	sizeof(rstate->border_color));
		2487	}
		2488
		2489	return rstate;
		2490	}
		2491
		2492	static struct si_pm4_state si_set_sampler_view(struct r600_context rctx,
		2493	unsigned count,
		2494	struct pipe_sampler_view **views,
		2495	struct r600_textures_info *samplers,
		2496	unsigned user_data_reg)
		2497	{
		2498	struct si_pipe_sampler_view resource = (struct si_pipe_sampler_view )views;
		2499	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		2500	int i, j;
		2501
		2502	if (!count)
		2503	goto out;
		2504
		2505	si_pm4_inval_texture_cache(pm4);
		2506
		2507	si_pm4_sh_data_begin(pm4);
		2508	for (i = 0; i < count; i++) {
		2509	pipe_sampler_view_reference(
		2510	(struct pipe_sampler_view **)&samplers->views[i],
		2511	views[i]);
		2512
		2513	if (views[i]) {
		2514	struct r600_resource_texture *rtex =
		2515	(struct r600_resource_texture*)views[i]->texture;
		2516
		2517	if (rtex->is_depth && !rtex->is_flushing_texture) {
		2518	samplers->depth_texture_mask \|= 1 << i;
		2519	} else {
		2520	samplers->depth_texture_mask &= ~(1 << i);
		2521	}
		2522
		2523	si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
		2524	} else {
		2525	samplers->depth_texture_mask &= ~(1 << i);
		2526	}
		2527
		2528	for (j = 0; j < Elements(resource[i]->state); ++j) {
		2529	si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
		2530	}
		2531	}
		2532
		2533	for (i = count; i < NUM_TEX_UNITS; i++) {
		2534	if (samplers->views[i])
		2535	pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
		2536	}
		2537
		2538	si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
		2539
		2540	out:
		2541	rctx->ps_samplers.n_views = count;
		2542	return pm4;
		2543	}
		2544
		2545	static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
		2546	struct pipe_sampler_view **views)
		2547	{
		2548	struct r600_context rctx = (struct r600_context )ctx;
		2549	struct si_pm4_state *pm4;
		2550
		2551	pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
		2552	R_00B130_SPI_SHADER_USER_DATA_VS_0);
		2553	si_pm4_set_state(rctx, vs_sampler_views, pm4);
		2554	}
		2555
		2556	static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
		2557	struct pipe_sampler_view **views)
		2558	{
		2559	struct r600_context rctx = (struct r600_context )ctx;
		2560	struct si_pm4_state *pm4;
		2561
		2562	pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
		2563	R_00B030_SPI_SHADER_USER_DATA_PS_0);
		2564	si_pm4_set_state(rctx, ps_sampler_views, pm4);
		2565	}
		2566
		2567	static struct si_pm4_state si_bind_sampler(struct r600_context rctx, unsigned count,
		2568	void **states,
		2569	struct r600_textures_info *samplers,
		2570	unsigned user_data_reg)
		2571	{
		2572	struct si_pipe_sampler_state rstates = (struct si_pipe_sampler_state )states;
		2573	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		2574	uint32_t *border_color_table = NULL;
		2575	int i, j;
		2576
		2577	if (!count)
		2578	goto out;
		2579
		2580	si_pm4_inval_texture_cache(pm4);
		2581
		2582	si_pm4_sh_data_begin(pm4);
		2583	for (i = 0; i < count; i++) {
		2584	if (rstates[i] &&
		2585	G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
		2586	V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
		2587	if (!rctx->border_color_table \|\|
		2588	((rctx->border_color_offset + count - i) &
		2589	C_008F3C_BORDER_COLOR_PTR)) {
		2590	si_resource_reference(&rctx->border_color_table, NULL);
		2591	rctx->border_color_offset = 0;
		2592
		2593	rctx->border_color_table =
		2594	si_resource_create_custom(&rctx->screen->screen,
		2595	PIPE_USAGE_STAGING,
		2596	4096 * 4 * 4);
		2597	}
		2598
		2599	if (!border_color_table) {
		2600	border_color_table =
		2601	rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
		2602	rctx->cs,
		2603	PIPE_TRANSFER_WRITE \|
		2604	PIPE_TRANSFER_UNSYNCHRONIZED);
		2605	}
		2606
		2607	for (j = 0; j < 4; j++) {
		2608	border_color_table[4 * rctx->border_color_offset + j] =
		2609	util_le32_to_cpu(rstates[i]->border_color[j]);
		2610	}
		2611
		2612	rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
		2613	rstates[i]->val[3] \|= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
		2614	}
		2615
		2616	for (j = 0; j < Elements(rstates[i]->val); ++j) {
		2617	si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
		2618	}
		2619	}
		2620	si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
		2621
		2622	if (border_color_table) {
		2623	uint64_t va_offset =
		2624	r600_resource_va(&rctx->screen->screen,
		2625	(void*)rctx->border_color_table);
		2626
		2627	si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
		2628	if (rctx->chip_class >= CIK)
		2629	si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
		2630	rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
		2631	si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
		2632	}
		2633
		2634	memcpy(samplers->samplers, states, sizeof(void) count);
		2635
		2636	out:
		2637	samplers->n_samplers = count;
		2638	return pm4;
		2639	}
		2640
		2641	static void si_bind_vs_sampler(struct pipe_context ctx, unsigned count, void *states)
		2642	{
		2643	struct r600_context rctx = (struct r600_context )ctx;
		2644	struct si_pm4_state *pm4;
		2645
		2646	pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
		2647	R_00B130_SPI_SHADER_USER_DATA_VS_0);
		2648	si_pm4_set_state(rctx, vs_sampler, pm4);
		2649	}
		2650
		2651	static void si_bind_ps_sampler(struct pipe_context ctx, unsigned count, void *states)
		2652	{
		2653	struct r600_context rctx = (struct r600_context )ctx;
		2654	struct si_pm4_state *pm4;
		2655
		2656	pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
		2657	R_00B030_SPI_SHADER_USER_DATA_PS_0);
		2658	si_pm4_set_state(rctx, ps_sampler, pm4);
		2659	}
		2660
		2661	static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
		2662	{
		2663	}
		2664
		2665	static void si_delete_sampler_state(struct pipe_context ctx, void state)
		2666	{
		2667	free(state);
		2668	}
		2669
		2670	/*
		2671	* Constants
		2672	*/
		2673	static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
		2674	struct pipe_constant_buffer *input)
		2675	{
		2676	struct r600_context rctx = (struct r600_context )ctx;
		2677	struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
		2678	struct pipe_constant_buffer *cb;
		2679	const uint8_t *ptr;
		2680
		2681	/* Note that the state tracker can unbind constant buffers by
		2682	* passing NULL here.
		2683	*/
		2684	if (unlikely(!input \|\| (!input->buffer && !input->user_buffer))) {
		2685	state->enabled_mask &= ~(1 << index);
		2686	state->dirty_mask &= ~(1 << index);
		2687	pipe_resource_reference(&state->cb[index].buffer, NULL);
		2688	return;
		2689	}
		2690
		2691	cb = &state->cb[index];
		2692	cb->buffer_size = input->buffer_size;
		2693
		2694	ptr = input->user_buffer;
		2695
		2696	if (ptr) {
		2697	r600_upload_const_buffer(rctx,
		2698	(struct si_resource**)&cb->buffer, ptr,
		2699	cb->buffer_size, &cb->buffer_offset);
		2700	} else {
		2701	/* Setup the hw buffer. */
		2702	cb->buffer_offset = input->buffer_offset;
		2703	pipe_resource_reference(&cb->buffer, input->buffer);
		2704	}
		2705
		2706	state->enabled_mask \|= 1 << index;
		2707	state->dirty_mask \|= 1 << index;
		2708	}
		2709
		2710	/*
		2711	* Vertex elements & buffers
		2712	*/
		2713
		2714	static void si_create_vertex_elements(struct pipe_context ctx,
		2715	unsigned count,
		2716	const struct pipe_vertex_element *elements)
		2717	{
		2718	struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
		2719	int i;
		2720
		2721	assert(count < PIPE_MAX_ATTRIBS);
		2722	if (!v)
		2723	return NULL;
		2724
		2725	v->count = count;
		2726	for (i = 0; i < count; ++i) {
		2727	const struct util_format_description *desc;
		2728	unsigned data_format, num_format;
		2729	int first_non_void;
		2730
		2731	desc = util_format_description(elements[i].src_format);
		2732	first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
		2733	data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
		2734	desc, first_non_void);
		2735
		2736	switch (desc->channel[first_non_void].type) {
		2737	case UTIL_FORMAT_TYPE_FIXED:
		2738	num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
		2739	break;
		2740	case UTIL_FORMAT_TYPE_SIGNED:
		2741	if (desc->channel[first_non_void].normalized)
		2742	num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
		2743	else if (desc->channel[first_non_void].pure_integer)
		2744	num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
		2745	else
		2746	num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
		2747	break;
		2748	case UTIL_FORMAT_TYPE_UNSIGNED:
		2749	if (desc->channel[first_non_void].normalized)
		2750	num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
		2751	else if (desc->channel[first_non_void].pure_integer)
		2752	num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
		2753	else
		2754	num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
		2755	break;
		2756	case UTIL_FORMAT_TYPE_FLOAT:
		2757	default:
		2758	num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
		2759	}
		2760
		2761	v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) \|
		2762	S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) \|
		2763	S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) \|
		2764	S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) \|
		2765	S_008F0C_NUM_FORMAT(num_format) \|
		2766	S_008F0C_DATA_FORMAT(data_format);
		2767	}
		2768	memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
		2769
		2770	return v;
		2771	}
		2772
		2773	static void si_bind_vertex_elements(struct pipe_context ctx, void state)
		2774	{
		2775	struct r600_context rctx = (struct r600_context )ctx;
		2776	struct si_vertex_element v = (struct si_vertex_element)state;
		2777
		2778	rctx->vertex_elements = v;
		2779	}
		2780
		2781	static void si_delete_vertex_element(struct pipe_context ctx, void state)
		2782	{
		2783	struct r600_context rctx = (struct r600_context )ctx;
		2784
		2785	if (rctx->vertex_elements == state)
		2786	rctx->vertex_elements = NULL;
		2787	FREE(state);
		2788	}
		2789
		2790	static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
		2791	const struct pipe_vertex_buffer *buffers)
		2792	{
		2793	struct r600_context rctx = (struct r600_context )ctx;
		2794
		2795	util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
		2796	}
		2797
		2798	static void si_set_index_buffer(struct pipe_context *ctx,
		2799	const struct pipe_index_buffer *ib)
		2800	{
		2801	struct r600_context rctx = (struct r600_context )ctx;
		2802
		2803	if (ib) {
		2804	pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
		2805	memcpy(&rctx->index_buffer, ib, sizeof(*ib));
		2806	} else {
		2807	pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
		2808	}
		2809	}
		2810
		2811	/*
		2812	* Misc
		2813	*/
		2814	static void si_set_polygon_stipple(struct pipe_context *ctx,
		2815	const struct pipe_poly_stipple *state)
		2816	{
		2817	}
		2818
		2819	static void si_texture_barrier(struct pipe_context *ctx)
		2820	{
		2821	struct r600_context rctx = (struct r600_context )ctx;
		2822	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		2823
		2824	if (pm4 == NULL)
		2825	return;
		2826
		2827	si_pm4_inval_texture_cache(pm4);
		2828	si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
		2829	si_pm4_set_state(rctx, texture_barrier, pm4);
		2830	}
		2831
		2832	void si_init_state_functions(struct r600_context *rctx)
		2833	{
		2834	rctx->context.create_blend_state = si_create_blend_state;
		2835	rctx->context.bind_blend_state = si_bind_blend_state;
		2836	rctx->context.delete_blend_state = si_delete_blend_state;
		2837	rctx->context.set_blend_color = si_set_blend_color;
		2838
		2839	rctx->context.create_rasterizer_state = si_create_rs_state;
		2840	rctx->context.bind_rasterizer_state = si_bind_rs_state;
		2841	rctx->context.delete_rasterizer_state = si_delete_rs_state;
		2842
		2843	rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
		2844	rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
		2845	rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
		2846	rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
		2847	rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
		2848	rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
		2849	rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
		2850
		2851	rctx->context.set_clip_state = si_set_clip_state;
		2852	rctx->context.set_scissor_states = si_set_scissor_states;
		2853	rctx->context.set_viewport_states = si_set_viewport_states;
		2854	rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
		2855
		2856	rctx->context.set_framebuffer_state = si_set_framebuffer_state;
		2857
		2858	rctx->context.create_vs_state = si_create_vs_state;
		2859	rctx->context.create_fs_state = si_create_fs_state;
		2860	rctx->context.bind_vs_state = si_bind_vs_shader;
		2861	rctx->context.bind_fs_state = si_bind_ps_shader;
		2862	rctx->context.delete_vs_state = si_delete_vs_shader;
		2863	rctx->context.delete_fs_state = si_delete_ps_shader;
		2864
		2865	rctx->context.create_sampler_state = si_create_sampler_state;
		2866	rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
		2867	rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
		2868	rctx->context.delete_sampler_state = si_delete_sampler_state;
		2869
		2870	rctx->context.create_sampler_view = si_create_sampler_view;
		2871	rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
		2872	rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
		2873	rctx->context.sampler_view_destroy = si_sampler_view_destroy;
		2874
		2875	rctx->context.set_sample_mask = si_set_sample_mask;
		2876
		2877	rctx->context.set_constant_buffer = si_set_constant_buffer;
		2878
		2879	rctx->context.create_vertex_elements_state = si_create_vertex_elements;
		2880	rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
		2881	rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
		2882	rctx->context.set_vertex_buffers = si_set_vertex_buffers;
		2883	rctx->context.set_index_buffer = si_set_index_buffer;
		2884
		2885	rctx->context.create_stream_output_target = si_create_so_target;
		2886	rctx->context.stream_output_target_destroy = si_so_target_destroy;
		2887	rctx->context.set_stream_output_targets = si_set_so_targets;
		2888
		2889	rctx->context.texture_barrier = si_texture_barrier;
		2890	rctx->context.set_polygon_stipple = si_set_polygon_stipple;
		2891
		2892	rctx->context.draw_vbo = si_draw_vbo;
		2893	}
		2894
		2895	void si_init_config(struct r600_context *rctx)
		2896	{
		2897	struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
		2898
		2899	if (pm4 == NULL)
		2900	return;
		2901
		2902	si_cmd_context_control(pm4);
		2903
		2904	si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
		2905
		2906	si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
		2907	si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
		2908	si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
		2909	si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
		2910	si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
		2911	si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
		2912	si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
		2913	si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
		2914	si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
		2915	si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
		2916	si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
		2917	si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
		2918	si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
		2919	si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
		2920	si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
		2921	si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
		2922	si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
		2923	si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
		2924	S_028AA8_SWITCH_ON_EOP(1) \|
		2925	S_028AA8_PARTIAL_VS_WAVE_ON(1) \|
		2926	S_028AA8_PRIMGROUP_SIZE(63));
		2927	si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
		2928	si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
		2929	if (rctx->chip_class < CIK)
		2930	si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) \|
		2931	S_008A14_CLIP_VTX_REORDER_ENA(1));
		2932
		2933	si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
		2934	si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
		2935	si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
		2936
		2937	si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
		2938
		2939	si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
		2940
		2941	if (rctx->chip_class >= CIK) {
		2942	switch (rctx->screen->family) {
		2943	case CHIP_BONAIRE:
		2944	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
		2945	si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
		2946	break;
		2947	case CHIP_KAVERI:
		2948	/* XXX todo */
		2949	case CHIP_KABINI:
		2950	/* XXX todo */
		2951	default:
		2952	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
		2953	si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
		2954	break;
		2955	}
		2956	} else {
		2957	switch (rctx->screen->family) {
		2958	case CHIP_TAHITI:
		2959	case CHIP_PITCAIRN:
		2960	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
		2961	break;
		2962	case CHIP_VERDE:
		2963	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
		2964	break;
		2965	case CHIP_OLAND:
		2966	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
		2967	break;
		2968	case CHIP_HAINAN:
		2969	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
		2970	break;
		2971	default:
		2972	si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
		2973	break;
		2974	}
		2975	}
		2976
		2977	si_pm4_set_state(rctx, init, pm4);
		2978	}

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(root)/contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_state.c – Rev 4401