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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4358 | Serge | 1 | /* |
| 2 | * Copyright 2010 Jerome Glisse |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
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| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
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| 9 | * the Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: |
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| 24 | * Jerome Glisse |
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| 25 | * Corbin Simpson |
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| 26 | */ |
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| 27 | #include |
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| 28 | #include "pipe/p_screen.h" |
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| 29 | #include "util/u_format.h" |
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| 30 | #include "util/u_format_s3tc.h" |
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| 31 | #include "util/u_math.h" |
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| 32 | #include "util/u_inlines.h" |
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| 33 | #include "util/u_memory.h" |
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| 34 | #include "pipebuffer/pb_buffer.h" |
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| 35 | #include "radeonsi_pipe.h" |
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| 36 | #include "r600_resource.h" |
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| 37 | #include "sid.h" |
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| 38 | |||
| 39 | /* Copy from a full GPU texture to a transfer's staging one. */ |
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| 40 | static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) |
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| 41 | { |
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| 42 | struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; |
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| 43 | struct pipe_resource *texture = transfer->resource; |
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| 44 | |||
| 45 | ctx->resource_copy_region(ctx, rtransfer->staging, |
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| 46 | 0, 0, 0, 0, texture, transfer->level, |
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| 47 | &transfer->box); |
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| 48 | } |
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| 49 | |||
| 50 | /* Copy from a transfer's staging texture to a full GPU one. */ |
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| 51 | static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) |
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| 52 | { |
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| 53 | struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; |
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| 54 | struct pipe_resource *texture = transfer->resource; |
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| 55 | struct pipe_box sbox; |
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| 56 | |||
| 57 | u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox); |
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| 58 | |||
| 59 | ctx->resource_copy_region(ctx, texture, transfer->level, |
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| 60 | transfer->box.x, transfer->box.y, transfer->box.z, |
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| 61 | rtransfer->staging, |
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| 62 | 0, &sbox); |
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| 63 | } |
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| 64 | |||
| 65 | static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, |
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| 66 | unsigned level, unsigned layer) |
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| 67 | { |
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| 68 | return rtex->surface.level[level].offset + |
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| 69 | layer * rtex->surface.level[level].slice_size; |
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| 70 | } |
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| 71 | |||
| 72 | static int r600_init_surface(struct r600_screen *rscreen, |
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| 73 | struct radeon_surface *surface, |
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| 74 | const struct pipe_resource *ptex, |
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| 75 | unsigned array_mode, |
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| 76 | bool is_flushed_depth) |
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| 77 | { |
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| 78 | const struct util_format_description *desc = |
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| 79 | util_format_description(ptex->format); |
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| 80 | bool is_depth, is_stencil; |
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| 81 | |||
| 82 | is_depth = util_format_has_depth(desc); |
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| 83 | is_stencil = util_format_has_stencil(desc); |
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| 84 | |||
| 85 | surface->npix_x = ptex->width0; |
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| 86 | surface->npix_y = ptex->height0; |
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| 87 | surface->npix_z = ptex->depth0; |
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| 88 | surface->blk_w = util_format_get_blockwidth(ptex->format); |
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| 89 | surface->blk_h = util_format_get_blockheight(ptex->format); |
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| 90 | surface->blk_d = 1; |
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| 91 | surface->array_size = 1; |
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| 92 | surface->last_level = ptex->last_level; |
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| 93 | |||
| 94 | if (!is_flushed_depth && |
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| 95 | ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { |
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| 96 | surface->bpe = 4; /* stencil is allocated separately on evergreen */ |
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| 97 | } else { |
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| 98 | surface->bpe = util_format_get_blocksize(ptex->format); |
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| 99 | /* align byte per element on dword */ |
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| 100 | if (surface->bpe == 3) { |
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| 101 | surface->bpe = 4; |
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| 102 | } |
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| 103 | } |
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| 104 | |||
| 105 | surface->nsamples = 1; |
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| 106 | surface->flags = 0; |
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| 107 | switch (array_mode) { |
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| 108 | case V_009910_ARRAY_1D_TILED_THIN1: |
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| 109 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); |
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| 110 | break; |
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| 111 | case V_009910_ARRAY_2D_TILED_THIN1: |
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| 112 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); |
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| 113 | break; |
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| 114 | case V_009910_ARRAY_LINEAR_ALIGNED: |
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| 115 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); |
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| 116 | break; |
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| 117 | case V_009910_ARRAY_LINEAR_GENERAL: |
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| 118 | default: |
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| 119 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); |
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| 120 | break; |
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| 121 | } |
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| 122 | switch (ptex->target) { |
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| 123 | case PIPE_TEXTURE_1D: |
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| 124 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); |
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| 125 | break; |
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| 126 | case PIPE_TEXTURE_RECT: |
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| 127 | case PIPE_TEXTURE_2D: |
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| 128 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); |
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| 129 | break; |
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| 130 | case PIPE_TEXTURE_3D: |
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| 131 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); |
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| 132 | break; |
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| 133 | case PIPE_TEXTURE_1D_ARRAY: |
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| 134 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); |
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| 135 | surface->array_size = ptex->array_size; |
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| 136 | break; |
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| 137 | case PIPE_TEXTURE_2D_ARRAY: |
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| 138 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); |
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| 139 | surface->array_size = ptex->array_size; |
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| 140 | break; |
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| 141 | case PIPE_TEXTURE_CUBE: |
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| 142 | surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); |
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| 143 | break; |
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| 144 | case PIPE_BUFFER: |
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| 145 | default: |
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| 146 | return -EINVAL; |
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| 147 | } |
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| 148 | if (ptex->bind & PIPE_BIND_SCANOUT) { |
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| 149 | surface->flags |= RADEON_SURF_SCANOUT; |
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| 150 | } |
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| 151 | |||
| 152 | if (!is_flushed_depth && is_depth) { |
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| 153 | surface->flags |= RADEON_SURF_ZBUFFER; |
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| 154 | if (is_stencil) { |
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| 155 | surface->flags |= RADEON_SURF_SBUFFER | |
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| 156 | RADEON_SURF_HAS_SBUFFER_MIPTREE; |
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| 157 | } |
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| 158 | } |
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| 159 | surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; |
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| 160 | return 0; |
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| 161 | } |
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| 162 | |||
| 163 | static int r600_setup_surface(struct pipe_screen *screen, |
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| 164 | struct r600_resource_texture *rtex, |
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| 165 | unsigned array_mode, |
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| 166 | unsigned pitch_in_bytes_override) |
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| 167 | { |
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| 168 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
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| 169 | int r; |
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| 170 | |||
| 171 | r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); |
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| 172 | if (r) { |
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| 173 | return r; |
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| 174 | } |
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| 175 | if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { |
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| 176 | /* old ddx on evergreen over estimate alignment for 1d, only 1 level |
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| 177 | * for those |
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| 178 | */ |
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| 179 | rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; |
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| 180 | rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; |
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| 181 | rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; |
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| 182 | if (rtex->surface.flags & RADEON_SURF_SBUFFER) { |
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| 183 | rtex->surface.stencil_offset = |
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| 184 | rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size; |
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| 185 | } |
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| 186 | } |
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| 187 | return 0; |
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| 188 | } |
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| 189 | |||
| 190 | static boolean r600_texture_get_handle(struct pipe_screen* screen, |
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| 191 | struct pipe_resource *ptex, |
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| 192 | struct winsys_handle *whandle) |
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| 193 | { |
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| 194 | struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; |
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| 195 | struct si_resource *resource = &rtex->resource; |
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| 196 | struct radeon_surface *surface = &rtex->surface; |
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| 197 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
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| 198 | |||
| 199 | rscreen->ws->buffer_set_tiling(resource->buf, |
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| 200 | NULL, |
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| 201 | surface->level[0].mode >= RADEON_SURF_MODE_1D ? |
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| 202 | RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, |
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| 203 | surface->level[0].mode >= RADEON_SURF_MODE_2D ? |
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| 204 | RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, |
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| 205 | surface->bankw, surface->bankh, |
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| 206 | surface->tile_split, |
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| 207 | surface->stencil_tile_split, |
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| 208 | surface->mtilea, |
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| 209 | surface->level[0].pitch_bytes); |
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| 210 | |||
| 211 | return rscreen->ws->buffer_get_handle(resource->buf, |
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| 212 | surface->level[0].pitch_bytes, whandle); |
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| 213 | } |
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| 214 | |||
| 215 | static void r600_texture_destroy(struct pipe_screen *screen, |
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| 216 | struct pipe_resource *ptex) |
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| 217 | { |
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| 218 | struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; |
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| 219 | struct si_resource *resource = &rtex->resource; |
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| 220 | |||
| 221 | if (rtex->flushed_depth_texture) |
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| 222 | si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL); |
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| 223 | |||
| 224 | pb_reference(&resource->buf, NULL); |
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| 225 | FREE(rtex); |
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| 226 | } |
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| 227 | |||
| 228 | static void *si_texture_transfer_map(struct pipe_context *ctx, |
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| 229 | struct pipe_resource *texture, |
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| 230 | unsigned level, |
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| 231 | unsigned usage, |
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| 232 | const struct pipe_box *box, |
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| 233 | struct pipe_transfer **ptransfer) |
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| 234 | { |
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| 235 | struct r600_context *rctx = (struct r600_context *)ctx; |
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| 236 | struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; |
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| 237 | struct r600_transfer *trans; |
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| 238 | boolean use_staging_texture = FALSE; |
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| 239 | struct radeon_winsys_cs_handle *buf; |
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| 240 | enum pipe_format format = texture->format; |
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| 241 | unsigned offset = 0; |
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| 242 | char *map; |
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| 243 | |||
| 244 | /* We cannot map a tiled texture directly because the data is |
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| 245 | * in a different order, therefore we do detiling using a blit. |
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| 246 | * |
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| 247 | * Also, use a temporary in GTT memory for read transfers, as |
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| 248 | * the CPU is much happier reading out of cached system memory |
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| 249 | * than uncached VRAM. |
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| 250 | */ |
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| 251 | if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED && |
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| 252 | rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR) |
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| 253 | use_staging_texture = TRUE; |
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| 254 | |||
| 255 | /* XXX: Use a staging texture for uploads if the underlying BO |
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| 256 | * is busy. No interface for checking that currently? so do |
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| 257 | * it eagerly whenever the transfer doesn't require a readback |
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| 258 | * and might block. |
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| 259 | */ |
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| 260 | if ((usage & PIPE_TRANSFER_WRITE) && |
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| 261 | !(usage & (PIPE_TRANSFER_READ | |
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| 262 | PIPE_TRANSFER_DONTBLOCK | |
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| 263 | PIPE_TRANSFER_UNSYNCHRONIZED))) |
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| 264 | use_staging_texture = TRUE; |
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| 265 | |||
| 266 | if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) |
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| 267 | use_staging_texture = FALSE; |
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| 268 | |||
| 269 | if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) |
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| 270 | return NULL; |
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| 271 | |||
| 272 | trans = CALLOC_STRUCT(r600_transfer); |
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| 273 | if (trans == NULL) |
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| 274 | return NULL; |
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| 275 | pipe_resource_reference(&trans->transfer.resource, texture); |
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| 276 | trans->transfer.level = level; |
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| 277 | trans->transfer.usage = usage; |
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| 278 | trans->transfer.box = *box; |
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| 279 | if (rtex->is_depth) { |
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| 280 | /* XXX: only readback the rectangle which is being mapped? |
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| 281 | */ |
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| 282 | /* XXX: when discard is true, no need to read back from depth texture |
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| 283 | */ |
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| 284 | struct r600_resource_texture *staging_depth; |
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| 285 | |||
| 286 | if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { |
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| 287 | R600_ERR("failed to create temporary texture to hold untiled copy\n"); |
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| 288 | pipe_resource_reference(&trans->transfer.resource, NULL); |
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| 289 | FREE(trans); |
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| 290 | return NULL; |
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| 291 | } |
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| 292 | si_blit_uncompress_depth(ctx, rtex, staging_depth, |
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| 293 | level, level, |
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| 294 | box->z, box->z + box->depth - 1); |
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| 295 | trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; |
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| 296 | trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size; |
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| 297 | trans->offset = r600_texture_get_offset(staging_depth, level, box->z); |
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| 298 | |||
| 299 | trans->staging = &staging_depth->resource.b.b; |
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| 300 | } else if (use_staging_texture) { |
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| 301 | struct pipe_resource resource; |
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| 302 | struct r600_resource_texture *staging; |
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| 303 | |||
| 304 | memset(&resource, 0, sizeof(resource)); |
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| 305 | resource.format = texture->format; |
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| 306 | resource.width0 = box->width; |
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| 307 | resource.height0 = box->height; |
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| 308 | resource.depth0 = 1; |
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| 309 | resource.array_size = 1; |
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| 310 | resource.usage = PIPE_USAGE_STAGING; |
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| 311 | resource.flags = R600_RESOURCE_FLAG_TRANSFER; |
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| 312 | |||
| 313 | /* We must set the correct texture target and dimensions if needed for a 3D transfer. */ |
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| 314 | if (box->depth > 1 && util_max_layer(texture, level) > 0) |
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| 315 | resource.target = texture->target; |
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| 316 | else |
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| 317 | resource.target = PIPE_TEXTURE_2D; |
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| 318 | |||
| 319 | switch (resource.target) { |
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| 320 | case PIPE_TEXTURE_1D_ARRAY: |
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| 321 | case PIPE_TEXTURE_2D_ARRAY: |
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| 322 | case PIPE_TEXTURE_CUBE_ARRAY: |
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| 323 | resource.array_size = box->depth; |
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| 324 | break; |
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| 325 | case PIPE_TEXTURE_3D: |
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| 326 | resource.depth0 = box->depth; |
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| 327 | break; |
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| 328 | default:; |
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| 329 | } |
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| 330 | /* Create the temporary texture. */ |
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| 331 | staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource); |
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| 332 | if (staging == NULL) { |
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| 333 | R600_ERR("failed to create temporary texture to hold untiled copy\n"); |
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| 334 | pipe_resource_reference(&trans->transfer.resource, NULL); |
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| 335 | FREE(trans); |
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| 336 | return NULL; |
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| 337 | } |
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| 338 | |||
| 339 | trans->staging = &staging->resource.b.b; |
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| 340 | trans->transfer.stride = staging->surface.level[0].pitch_bytes; |
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| 341 | trans->transfer.layer_stride = staging->surface.level[0].slice_size; |
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| 342 | if (usage & PIPE_TRANSFER_READ) { |
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| 343 | r600_copy_to_staging_texture(ctx, trans); |
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| 344 | /* Always referenced in the blit. */ |
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| 345 | radeonsi_flush(ctx, NULL, 0); |
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| 346 | } |
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| 347 | } else { |
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| 348 | trans->transfer.stride = rtex->surface.level[level].pitch_bytes; |
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| 349 | trans->transfer.layer_stride = rtex->surface.level[level].slice_size; |
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| 350 | trans->offset = r600_texture_get_offset(rtex, level, box->z); |
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| 351 | } |
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| 352 | |||
| 353 | if (trans->staging) { |
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| 354 | buf = si_resource(trans->staging)->cs_buf; |
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| 355 | } else { |
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| 356 | buf = rtex->resource.cs_buf; |
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| 357 | } |
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| 358 | |||
| 359 | if (rtex->is_depth || !trans->staging) |
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| 360 | offset = trans->offset + |
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| 361 | box->y / util_format_get_blockheight(format) * trans->transfer.stride + |
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| 362 | box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); |
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| 363 | |||
| 364 | if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) { |
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| 365 | pipe_resource_reference(&trans->staging, NULL); |
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| 366 | pipe_resource_reference(&trans->transfer.resource, NULL); |
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| 367 | FREE(trans); |
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| 368 | return NULL; |
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| 369 | } |
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| 370 | |||
| 371 | *ptransfer = &trans->transfer; |
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| 372 | return map + offset; |
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| 373 | } |
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| 374 | |||
| 375 | static void si_texture_transfer_unmap(struct pipe_context *ctx, |
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| 376 | struct pipe_transfer* transfer) |
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| 377 | { |
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| 378 | struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; |
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| 379 | struct r600_context *rctx = (struct r600_context*)ctx; |
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| 380 | struct radeon_winsys_cs_handle *buf; |
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| 381 | struct pipe_resource *texture = transfer->resource; |
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| 382 | struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; |
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| 383 | |||
| 384 | if (rtransfer->staging) { |
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| 385 | buf = si_resource(rtransfer->staging)->cs_buf; |
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| 386 | } else { |
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| 387 | buf = si_resource(transfer->resource)->cs_buf; |
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| 388 | } |
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| 389 | rctx->ws->buffer_unmap(buf); |
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| 390 | |||
| 391 | if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { |
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| 392 | if (rtex->is_depth) { |
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| 393 | ctx->resource_copy_region(ctx, texture, transfer->level, |
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| 394 | transfer->box.x, transfer->box.y, transfer->box.z, |
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| 395 | &si_resource(rtransfer->staging)->b.b, transfer->level, |
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| 396 | &transfer->box); |
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| 397 | } else { |
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| 398 | r600_copy_from_staging_texture(ctx, rtransfer); |
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| 399 | } |
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| 400 | } |
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| 401 | |||
| 402 | if (rtransfer->staging) |
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| 403 | pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); |
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| 404 | |||
| 405 | pipe_resource_reference(&transfer->resource, NULL); |
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| 406 | FREE(transfer); |
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| 407 | } |
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| 408 | |||
| 409 | static const struct u_resource_vtbl r600_texture_vtbl = |
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| 410 | { |
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| 411 | r600_texture_get_handle, /* get_handle */ |
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| 412 | r600_texture_destroy, /* resource_destroy */ |
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| 413 | si_texture_transfer_map, /* transfer_map */ |
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| 414 | u_default_transfer_flush_region,/* transfer_flush_region */ |
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| 415 | si_texture_transfer_unmap, /* transfer_unmap */ |
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| 416 | NULL /* transfer_inline_write */ |
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| 417 | }; |
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| 418 | |||
| 419 | DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE); |
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| 420 | |||
| 421 | static struct r600_resource_texture * |
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| 422 | r600_texture_create_object(struct pipe_screen *screen, |
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| 423 | const struct pipe_resource *base, |
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| 424 | unsigned array_mode, |
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| 425 | unsigned pitch_in_bytes_override, |
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| 426 | unsigned max_buffer_size, |
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| 427 | struct pb_buffer *buf, |
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| 428 | boolean alloc_bo, |
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| 429 | struct radeon_surface *surface) |
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| 430 | { |
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| 431 | struct r600_resource_texture *rtex; |
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| 432 | struct si_resource *resource; |
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| 433 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
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| 434 | int r; |
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| 435 | |||
| 436 | rtex = CALLOC_STRUCT(r600_resource_texture); |
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| 437 | if (rtex == NULL) |
||
| 438 | return NULL; |
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| 439 | |||
| 440 | resource = &rtex->resource; |
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| 441 | resource->b.b = *base; |
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| 442 | resource->b.vtbl = &r600_texture_vtbl; |
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| 443 | pipe_reference_init(&resource->b.b.reference, 1); |
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| 444 | resource->b.b.screen = screen; |
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| 445 | rtex->pitch_override = pitch_in_bytes_override; |
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| 446 | rtex->real_format = base->format; |
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| 447 | |||
| 448 | /* don't include stencil-only formats which we don't support for rendering */ |
||
| 449 | rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); |
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| 450 | |||
| 451 | rtex->surface = *surface; |
||
| 452 | r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override); |
||
| 453 | if (r) { |
||
| 454 | FREE(rtex); |
||
| 455 | return NULL; |
||
| 456 | } |
||
| 457 | |||
| 458 | /* Now create the backing buffer. */ |
||
| 459 | if (!buf && alloc_bo) { |
||
| 460 | unsigned base_align = rtex->surface.bo_alignment; |
||
| 461 | unsigned size = rtex->surface.bo_size; |
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| 462 | |||
| 463 | base_align = rtex->surface.bo_alignment; |
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| 464 | if (!si_init_resource(rscreen, resource, size, base_align, FALSE, base->usage)) { |
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| 465 | FREE(rtex); |
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| 466 | return NULL; |
||
| 467 | } |
||
| 468 | } else if (buf) { |
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| 469 | resource->buf = buf; |
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| 470 | resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); |
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| 471 | resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; |
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| 472 | } |
||
| 473 | |||
| 474 | if (debug_get_option_print_texdepth() && rtex->is_depth) { |
||
| 475 | printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " |
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| 476 | "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, " |
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| 477 | "bpe=%u, nsamples=%u, flags=%u\n", |
||
| 478 | rtex->surface.npix_x, rtex->surface.npix_y, |
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| 479 | rtex->surface.npix_z, rtex->surface.blk_w, |
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| 480 | rtex->surface.blk_h, rtex->surface.blk_d, |
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| 481 | rtex->surface.array_size, rtex->surface.last_level, |
||
| 482 | rtex->surface.bpe, rtex->surface.nsamples, |
||
| 483 | rtex->surface.flags); |
||
| 484 | if (rtex->surface.flags & RADEON_SURF_ZBUFFER) { |
||
| 485 | for (int i = 0; i <= rtex->surface.last_level; i++) { |
||
| 486 | printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, " |
||
| 487 | "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " |
||
| 488 | "nblk_z=%u, pitch_bytes=%u, mode=%u\n", |
||
| 489 | i, rtex->surface.level[i].offset, |
||
| 490 | rtex->surface.level[i].slice_size, |
||
| 491 | rtex->surface.level[i].npix_x, |
||
| 492 | rtex->surface.level[i].npix_y, |
||
| 493 | rtex->surface.level[i].npix_z, |
||
| 494 | rtex->surface.level[i].nblk_x, |
||
| 495 | rtex->surface.level[i].nblk_y, |
||
| 496 | rtex->surface.level[i].nblk_z, |
||
| 497 | rtex->surface.level[i].pitch_bytes, |
||
| 498 | rtex->surface.level[i].mode); |
||
| 499 | } |
||
| 500 | } |
||
| 501 | if (rtex->surface.flags & RADEON_SURF_SBUFFER) { |
||
| 502 | for (int i = 0; i <= rtex->surface.last_level; i++) { |
||
| 503 | printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, " |
||
| 504 | "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " |
||
| 505 | "nblk_z=%u, pitch_bytes=%u, mode=%u\n", |
||
| 506 | i, rtex->surface.stencil_level[i].offset, |
||
| 507 | rtex->surface.stencil_level[i].slice_size, |
||
| 508 | rtex->surface.stencil_level[i].npix_x, |
||
| 509 | rtex->surface.stencil_level[i].npix_y, |
||
| 510 | rtex->surface.stencil_level[i].npix_z, |
||
| 511 | rtex->surface.stencil_level[i].nblk_x, |
||
| 512 | rtex->surface.stencil_level[i].nblk_y, |
||
| 513 | rtex->surface.stencil_level[i].nblk_z, |
||
| 514 | rtex->surface.stencil_level[i].pitch_bytes, |
||
| 515 | rtex->surface.stencil_level[i].mode); |
||
| 516 | } |
||
| 517 | } |
||
| 518 | } |
||
| 519 | return rtex; |
||
| 520 | } |
||
| 521 | |||
| 522 | struct pipe_resource *si_texture_create(struct pipe_screen *screen, |
||
| 523 | const struct pipe_resource *templ) |
||
| 524 | { |
||
| 525 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
||
| 526 | struct radeon_surface surface; |
||
| 527 | unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; |
||
| 528 | int r; |
||
| 529 | |||
| 530 | if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && |
||
| 531 | !(templ->bind & PIPE_BIND_SCANOUT)) { |
||
| 532 | if (util_format_is_compressed(templ->format)) { |
||
| 533 | array_mode = V_009910_ARRAY_1D_TILED_THIN1; |
||
| 534 | } else { |
||
| 535 | if (rscreen->chip_class >= CIK) |
||
| 536 | array_mode = V_009910_ARRAY_1D_TILED_THIN1; /* XXX fix me */ |
||
| 537 | else |
||
| 538 | array_mode = V_009910_ARRAY_2D_TILED_THIN1; |
||
| 539 | } |
||
| 540 | } |
||
| 541 | |||
| 542 | r = r600_init_surface(rscreen, &surface, templ, array_mode, |
||
| 543 | templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); |
||
| 544 | if (r) { |
||
| 545 | return NULL; |
||
| 546 | } |
||
| 547 | r = rscreen->ws->surface_best(rscreen->ws, &surface); |
||
| 548 | if (r) { |
||
| 549 | return NULL; |
||
| 550 | } |
||
| 551 | return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, |
||
| 552 | 0, 0, NULL, TRUE, &surface); |
||
| 553 | } |
||
| 554 | |||
| 555 | static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, |
||
| 556 | struct pipe_resource *texture, |
||
| 557 | const struct pipe_surface *surf_tmpl) |
||
| 558 | { |
||
| 559 | struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; |
||
| 560 | struct r600_surface *surface = CALLOC_STRUCT(r600_surface); |
||
| 561 | unsigned level = surf_tmpl->u.tex.level; |
||
| 562 | |||
| 563 | assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); |
||
| 564 | assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); |
||
| 565 | assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); |
||
| 566 | if (surface == NULL) |
||
| 567 | return NULL; |
||
| 568 | /* XXX no offset */ |
||
| 569 | /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ |
||
| 570 | pipe_reference_init(&surface->base.reference, 1); |
||
| 571 | pipe_resource_reference(&surface->base.texture, texture); |
||
| 572 | surface->base.context = pipe; |
||
| 573 | surface->base.format = surf_tmpl->format; |
||
| 574 | surface->base.width = rtex->surface.level[level].npix_x; |
||
| 575 | surface->base.height = rtex->surface.level[level].npix_y; |
||
| 576 | surface->base.texture = texture; |
||
| 577 | surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; |
||
| 578 | surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; |
||
| 579 | surface->base.u.tex.level = level; |
||
| 580 | |||
| 581 | return &surface->base; |
||
| 582 | } |
||
| 583 | |||
| 584 | static void r600_surface_destroy(struct pipe_context *pipe, |
||
| 585 | struct pipe_surface *surface) |
||
| 586 | { |
||
| 587 | pipe_resource_reference(&surface->texture, NULL); |
||
| 588 | FREE(surface); |
||
| 589 | } |
||
| 590 | |||
| 591 | struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, |
||
| 592 | const struct pipe_resource *templ, |
||
| 593 | struct winsys_handle *whandle) |
||
| 594 | { |
||
| 595 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
||
| 596 | struct pb_buffer *buf = NULL; |
||
| 597 | unsigned stride = 0; |
||
| 598 | unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; |
||
| 599 | enum radeon_bo_layout micro, macro; |
||
| 600 | struct radeon_surface surface; |
||
| 601 | int r; |
||
| 602 | |||
| 603 | /* Support only 2D textures without mipmaps */ |
||
| 604 | if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || |
||
| 605 | templ->depth0 != 1 || templ->last_level != 0) |
||
| 606 | return NULL; |
||
| 607 | |||
| 608 | buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); |
||
| 609 | if (!buf) |
||
| 610 | return NULL; |
||
| 611 | |||
| 612 | rscreen->ws->buffer_get_tiling(buf, µ, ¯o, |
||
| 613 | &surface.bankw, &surface.bankh, |
||
| 614 | &surface.tile_split, |
||
| 615 | &surface.stencil_tile_split, |
||
| 616 | &surface.mtilea); |
||
| 617 | |||
| 618 | if (macro == RADEON_LAYOUT_TILED) |
||
| 619 | array_mode = V_009910_ARRAY_2D_TILED_THIN1; |
||
| 620 | else if (micro == RADEON_LAYOUT_TILED) |
||
| 621 | array_mode = V_009910_ARRAY_1D_TILED_THIN1; |
||
| 622 | else |
||
| 623 | array_mode = V_009910_ARRAY_LINEAR_ALIGNED; |
||
| 624 | |||
| 625 | r = r600_init_surface(rscreen, &surface, templ, array_mode, false); |
||
| 626 | if (r) { |
||
| 627 | return NULL; |
||
| 628 | } |
||
| 629 | /* always set the scanout flags */ |
||
| 630 | surface.flags |= RADEON_SURF_SCANOUT; |
||
| 631 | return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, |
||
| 632 | stride, 0, buf, FALSE, &surface); |
||
| 633 | } |
||
| 634 | |||
| 635 | bool r600_init_flushed_depth_texture(struct pipe_context *ctx, |
||
| 636 | struct pipe_resource *texture, |
||
| 637 | struct r600_resource_texture **staging) |
||
| 638 | { |
||
| 639 | struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; |
||
| 640 | struct pipe_resource resource; |
||
| 641 | struct r600_resource_texture **flushed_depth_texture = staging ? |
||
| 642 | staging : &rtex->flushed_depth_texture; |
||
| 643 | |||
| 644 | if (!staging && rtex->flushed_depth_texture) |
||
| 645 | return true; /* it's ready */ |
||
| 646 | |||
| 647 | resource.target = texture->target; |
||
| 648 | resource.format = texture->format; |
||
| 649 | resource.width0 = texture->width0; |
||
| 650 | resource.height0 = texture->height0; |
||
| 651 | resource.depth0 = texture->depth0; |
||
| 652 | resource.array_size = texture->array_size; |
||
| 653 | resource.last_level = texture->last_level; |
||
| 654 | resource.nr_samples = texture->nr_samples; |
||
| 655 | resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT; |
||
| 656 | resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; |
||
| 657 | resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; |
||
| 658 | |||
| 659 | if (staging) |
||
| 660 | resource.flags |= R600_RESOURCE_FLAG_TRANSFER; |
||
| 661 | else |
||
| 662 | rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1; |
||
| 663 | |||
| 664 | *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); |
||
| 665 | if (*flushed_depth_texture == NULL) { |
||
| 666 | R600_ERR("failed to create temporary texture to hold flushed depth\n"); |
||
| 667 | return false; |
||
| 668 | } |
||
| 669 | |||
| 670 | (*flushed_depth_texture)->is_flushing_texture = TRUE; |
||
| 671 | return true; |
||
| 672 | } |
||
| 673 | |||
| 674 | void si_init_surface_functions(struct r600_context *r600) |
||
| 675 | { |
||
| 676 | r600->context.create_surface = r600_create_surface; |
||
| 677 | r600->context.surface_destroy = r600_surface_destroy; |
||
| 678 | } |