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4358 | Serge | 1 | #ifndef NVE4_COMPUTE_XML |
2 | #define NVE4_COMPUTE_XML |
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3 | |||
4 | /* Autogenerated file, DO NOT EDIT manually! |
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5 | |||
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
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8 | git clone git://0x04.net/rules-ng-ng |
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9 | |||
10 | The rules-ng-ng source files this header was generated from are: |
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11 | - nve4_compute.xml ( 10168 bytes, from 2013-03-31 20:05:20) |
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12 | - copyright.xml ( 6452 bytes, from 2011-08-11 18:25:12) |
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13 | - nvchipsets.xml ( 3954 bytes, from 2013-03-26 01:26:43) |
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14 | - nv_object.xml ( 14395 bytes, from 2013-03-31 20:05:20) |
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15 | - nv_defs.xml ( 4437 bytes, from 2011-08-11 18:25:12) |
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16 | - nv50_defs.xml ( 9613 bytes, from 2013-03-28 11:02:04) |
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17 | - nve4_p2mf.xml ( 2373 bytes, from 2013-03-31 20:05:20) |
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18 | |||
19 | Copyright (C) 2006-2013 by the following authors: |
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20 | - Artur Huillet |
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21 | - Ben Skeggs (darktama, darktama_) |
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22 | - B. R. |
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23 | - Carlos Martin |
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24 | - Christoph Bumiller |
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25 | - Dawid Gajownik |
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26 | - Dmitry Baryshkov |
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27 | - Dmitry Eremin-Solenikov |
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28 | - EdB |
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29 | - Erik Waling |
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30 | - Francisco Jerez |
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31 | - imirkin |
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32 | - jb17bsome |
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33 | - Jeremy Kolb |
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34 | - Laurent Carlier |
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35 | - Luca Barbieri |
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36 | - Maarten Maathuis |
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37 | - Marcin KoĆcielnicki |
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38 | - Mark Carey |
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39 | - Matthieu Castet |
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40 | - nvidiaman |
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41 | - Patrice Mandin |
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42 | - Pekka Paalanen |
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43 | - Peter Popov |
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44 | - Richard Hughes |
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45 | - Rudi Cilibrasi |
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46 | - Serge Martin |
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47 | - Simon Raffeiner |
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48 | - Stephane Loeuillet |
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49 | - Stephane Marchesin |
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50 | - sturmflut |
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51 | - Sylvain Munaut |
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52 | - Victor Stinner |
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53 | - Wladmir van der Laan |
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54 | - Younes Manton |
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55 | |||
56 | Permission is hereby granted, free of charge, to any person obtaining |
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57 | a copy of this software and associated documentation files (the |
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58 | "Software"), to deal in the Software without restriction, including |
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59 | without limitation the rights to use, copy, modify, merge, publish, |
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60 | distribute, sublicense, and/or sell copies of the Software, and to |
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61 | permit persons to whom the Software is furnished to do so, subject to |
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62 | the following conditions: |
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63 | |||
64 | The above copyright notice and this permission notice (including the |
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65 | next paragraph) shall be included in all copies or substantial |
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66 | portions of the Software. |
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67 | |||
68 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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69 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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70 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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71 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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72 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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73 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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74 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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75 | */ |
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76 | |||
77 | |||
78 | |||
79 | |||
80 | #define NVE4_COMPUTE_UNK0144 0x00000144 |
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81 | |||
82 | #define NVE4_COMPUTE_UPLOAD 0x00000000 |
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83 | |||
84 | #define NVE4_COMPUTE_UPLOAD_LINE_LENGTH_IN 0x00000180 |
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85 | |||
86 | #define NVE4_COMPUTE_UPLOAD_LINE_COUNT 0x00000184 |
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87 | |||
88 | #define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_HIGH 0x00000188 |
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89 | |||
90 | #define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_LOW 0x0000018c |
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91 | |||
92 | #define NVE4_COMPUTE_UPLOAD_DST_PITCH 0x00000190 |
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93 | |||
94 | #define NVE4_COMPUTE_UPLOAD_DST_TILE_MODE 0x00000194 |
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95 | |||
96 | #define NVE4_COMPUTE_UPLOAD_DST_WIDTH 0x00000198 |
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97 | |||
98 | #define NVE4_COMPUTE_UPLOAD_DST_HEIGHT 0x0000019c |
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99 | |||
100 | #define NVE4_COMPUTE_UPLOAD_DST_DEPTH 0x000001a0 |
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101 | |||
102 | #define NVE4_COMPUTE_UPLOAD_DST_Z 0x000001a4 |
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103 | |||
104 | #define NVE4_COMPUTE_UPLOAD_DST_X 0x000001a8 |
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105 | |||
106 | #define NVE4_COMPUTE_UPLOAD_DST_Y 0x000001ac |
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107 | |||
108 | #define NVE4_COMPUTE_UPLOAD_EXEC 0x000001b0 |
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109 | #define NVE4_COMPUTE_UPLOAD_EXEC_LINEAR 0x00000001 |
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110 | #define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__MASK 0x0000007e |
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111 | #define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__SHIFT 1 |
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112 | #define NVE4_COMPUTE_UPLOAD_EXEC_BUF_NOTIFY 0x00000300 |
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113 | #define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__MASK 0x0000f000 |
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114 | #define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__SHIFT 12 |
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115 | |||
116 | #define NVE4_COMPUTE_UPLOAD_DATA 0x000001b4 |
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117 | |||
118 | #define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_HIGH 0x000001dc |
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119 | |||
120 | #define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_LOW 0x000001e0 |
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121 | |||
122 | #define NVE4_COMPUTE_UPLOAD_QUERY_SEQUENCE 0x000001e4 |
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123 | |||
124 | #define NVE4_COMPUTE_UPLOAD_UNK01F0 0x000001f0 |
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125 | |||
126 | #define NVE4_COMPUTE_UPLOAD_UNK01F4 0x000001f4 |
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127 | |||
128 | #define NVE4_COMPUTE_UPLOAD_UNK01F8 0x000001f8 |
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129 | |||
130 | #define NVE4_COMPUTE_UPLOAD_UNK01FC 0x000001fc |
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131 | |||
132 | #define NVE4_COMPUTE_SHARED_BASE 0x00000214 |
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133 | |||
134 | #define NVE4_COMPUTE_MEM_BARRIER 0x0000021c |
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135 | #define NVE4_COMPUTE_MEM_BARRIER_UNK0__MASK 0x00000007 |
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136 | #define NVE4_COMPUTE_MEM_BARRIER_UNK0__SHIFT 0 |
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137 | #define NVE4_COMPUTE_MEM_BARRIER_UNK4 0x00000010 |
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138 | #define NVE4_COMPUTE_MEM_BARRIER_UNK12 0x00001000 |
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139 | |||
140 | #define NVE4_COMPUTE_UNK0240 0x00000240 |
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141 | |||
142 | #define NVE4_COMPUTE_UNK244_TIC_FLUSH 0x00000244 |
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143 | |||
144 | #define NVE4_COMPUTE_UNK0248 0x00000248 |
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145 | #define NVE4_COMPUTE_UNK0248_UNK0__MASK 0x0000003f |
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146 | #define NVE4_COMPUTE_UNK0248_UNK0__SHIFT 0 |
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147 | #define NVE4_COMPUTE_UNK0248_UNK8__MASK 0x00ffff00 |
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148 | #define NVE4_COMPUTE_UNK0248_UNK8__SHIFT 8 |
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149 | |||
150 | #define NVE4_COMPUTE_UNK0274 0x00000274 |
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151 | |||
152 | #define NVE4_COMPUTE_UNK0278 0x00000278 |
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153 | |||
154 | #define NVE4_COMPUTE_UNK027C 0x0000027c |
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155 | |||
156 | #define NVE4_COMPUTE_UNK0280 0x00000280 |
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157 | |||
158 | #define NVE4_COMPUTE_UNK0284 0x00000284 |
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159 | |||
160 | #define NVE4_COMPUTE_UNK0288 0x00000288 |
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161 | |||
162 | #define NVE4_COMPUTE_UNK0290 0x00000290 |
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163 | |||
164 | #define NVE4_COMPUTE_UNK02B0 0x000002b0 |
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165 | |||
166 | #define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS 0x000002b4 |
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167 | #define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS__SHR 8 |
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168 | |||
169 | #define NVE4_COMPUTE_UNK02B8 0x000002b8 |
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170 | |||
171 | #define NVE4_COMPUTE_LAUNCH 0x000002bc |
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172 | |||
173 | #define NVE4_COMPUTE_MP_TEMP_SIZE(i0) (0x000002e4 + 0xc*(i0)) |
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174 | #define NVE4_COMPUTE_MP_TEMP_SIZE__ESIZE 0x0000000c |
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175 | #define NVE4_COMPUTE_MP_TEMP_SIZE__LEN 0x00000002 |
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176 | |||
177 | #define NVE4_COMPUTE_MP_TEMP_SIZE_HIGH(i0) (0x000002e4 + 0xc*(i0)) |
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178 | |||
179 | #define NVE4_COMPUTE_MP_TEMP_SIZE_LOW(i0) (0x000002e8 + 0xc*(i0)) |
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180 | |||
181 | #define NVE4_COMPUTE_MP_TEMP_SIZE_MASK(i0) (0x000002ec + 0xc*(i0)) |
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182 | |||
183 | #define NVE4_COMPUTE_UNK0310 0x00000310 |
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184 | |||
185 | #define NVE4_COMPUTE_FIRMWARE(i0) (0x00000500 + 0x4*(i0)) |
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186 | #define NVE4_COMPUTE_FIRMWARE__ESIZE 0x00000004 |
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187 | #define NVE4_COMPUTE_FIRMWARE__LEN 0x00000020 |
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188 | |||
189 | #define NVE4_COMPUTE_LOCAL_BASE 0x0000077c |
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190 | |||
191 | #define NVE4_COMPUTE_TEMP_ADDRESS_HIGH 0x00000790 |
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192 | |||
193 | #define NVE4_COMPUTE_TEMP_ADDRESS_LOW 0x00000794 |
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194 | |||
195 | #define NVE4_COMPUTE_UNK0D94 0x00000d94 |
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196 | |||
197 | #define NVE4_COMPUTE_WATCHDOG_TIMER 0x00000de4 |
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198 | |||
199 | #define NVE4_COMPUTE_UNK0F44(i0) (0x00000f44 + 0x4*(i0)) |
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200 | #define NVE4_COMPUTE_UNK0F44__ESIZE 0x00000004 |
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201 | #define NVE4_COMPUTE_UNK0F44__LEN 0x00000004 |
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202 | |||
203 | #define NVE4_COMPUTE_UNK1040(i0) (0x00001040 + 0x4*(i0)) |
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204 | #define NVE4_COMPUTE_UNK1040__ESIZE 0x00000004 |
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205 | #define NVE4_COMPUTE_UNK1040__LEN 0x0000000c |
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206 | |||
207 | #define NVE4_COMPUTE_UNK1288_TIC_FLUSH 0x00001288 |
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208 | |||
209 | #define NVE4_COMPUTE_TSC_FLUSH 0x00001330 |
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210 | #define NVE4_COMPUTE_TSC_FLUSH_SPECIFIC 0x00000001 |
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211 | #define NVE4_COMPUTE_TSC_FLUSH_ENTRY__MASK 0x03fffff0 |
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212 | #define NVE4_COMPUTE_TSC_FLUSH_ENTRY__SHIFT 4 |
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213 | |||
214 | #define NVE4_COMPUTE_TIC_FLUSH 0x00001334 |
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215 | #define NVE4_COMPUTE_TIC_FLUSH_SPECIFIC 0x00000001 |
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216 | #define NVE4_COMPUTE_TIC_FLUSH_ENTRY__MASK 0x03fffff0 |
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217 | #define NVE4_COMPUTE_TIC_FLUSH_ENTRY__SHIFT 4 |
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218 | |||
219 | #define NVE4_COMPUTE_TEX_CACHE_CTL 0x00001338 |
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220 | #define NVE4_COMPUTE_TEX_CACHE_CTL_UNK0 0x00000001 |
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221 | #define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__MASK 0x03fffff0 |
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222 | #define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__SHIFT 4 |
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223 | |||
224 | #define NVE4_COMPUTE_UNK1424_TSC_FLUSH 0x00001424 |
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225 | |||
226 | #define NVE4_COMPUTE_COND_ADDRESS_HIGH 0x00001550 |
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227 | |||
228 | #define NVE4_COMPUTE_COND_ADDRESS_LOW 0x00001554 |
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229 | |||
230 | #define NVE4_COMPUTE_COND_MODE 0x00001558 |
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231 | #define NVE4_COMPUTE_COND_MODE_NEVER 0x00000000 |
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232 | #define NVE4_COMPUTE_COND_MODE_ALWAYS 0x00000001 |
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233 | #define NVE4_COMPUTE_COND_MODE_RES_NON_ZERO 0x00000002 |
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234 | #define NVE4_COMPUTE_COND_MODE_EQUAL 0x00000003 |
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235 | #define NVE4_COMPUTE_COND_MODE_NOT_EQUAL 0x00000004 |
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236 | |||
237 | #define NVE4_COMPUTE_TSC_ADDRESS_HIGH 0x0000155c |
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238 | |||
239 | #define NVE4_COMPUTE_TSC_ADDRESS_LOW 0x00001560 |
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240 | |||
241 | #define NVE4_COMPUTE_TSC_LIMIT 0x00001564 |
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242 | |||
243 | #define NVE4_COMPUTE_TIC_ADDRESS_HIGH 0x00001574 |
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244 | |||
245 | #define NVE4_COMPUTE_TIC_ADDRESS_LOW 0x00001578 |
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246 | |||
247 | #define NVE4_COMPUTE_TIC_LIMIT 0x0000157c |
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248 | |||
249 | #define NVE4_COMPUTE_CODE_ADDRESS_HIGH 0x00001608 |
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250 | |||
251 | #define NVE4_COMPUTE_CODE_ADDRESS_LOW 0x0000160c |
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252 | |||
253 | #define NVE4_COMPUTE_UNK1690 0x00001690 |
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254 | |||
255 | #define NVE4_COMPUTE_FLUSH 0x00001698 |
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256 | #define NVE4_COMPUTE_FLUSH_CODE 0x00000001 |
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257 | #define NVE4_COMPUTE_FLUSH_GLOBAL 0x00000010 |
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258 | #define NVE4_COMPUTE_FLUSH_CB 0x00001000 |
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259 | |||
260 | #define NVE4_COMPUTE_UNK1944 0x00001944 |
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261 | |||
262 | #define NVE4_COMPUTE_DELAY 0x00001a24 |
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263 | |||
264 | #define NVE4_COMPUTE_UNK1A2C(i0) (0x00001a2c + 0x4*(i0)) |
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265 | #define NVE4_COMPUTE_UNK1A2C__ESIZE 0x00000004 |
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266 | #define NVE4_COMPUTE_UNK1A2C__LEN 0x00000005 |
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267 | |||
268 | #define NVE4_COMPUTE_QUERY_ADDRESS_HIGH 0x00001b00 |
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269 | |||
270 | #define NVE4_COMPUTE_QUERY_ADDRESS_LOW 0x00001b04 |
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271 | |||
272 | #define NVE4_COMPUTE_QUERY_SEQUENCE 0x00001b08 |
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273 | |||
274 | #define NVE4_COMPUTE_QUERY_GET 0x00001b0c |
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275 | #define NVE4_COMPUTE_QUERY_GET_MODE__MASK 0x00000003 |
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276 | #define NVE4_COMPUTE_QUERY_GET_MODE__SHIFT 0 |
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277 | #define NVE4_COMPUTE_QUERY_GET_MODE_WRITE 0x00000000 |
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278 | #define NVE4_COMPUTE_QUERY_GET_MODE_WRITE_INTR_NRHOST 0x00000003 |
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279 | #define NVE4_COMPUTE_QUERY_GET_INTR 0x00100000 |
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280 | #define NVE4_COMPUTE_QUERY_GET_SHORT 0x10000000 |
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281 | |||
282 | #define NVE4_COMPUTE_TEX_CB_INDEX 0x00002608 |
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283 | |||
284 | #define NVE4_COMPUTE_UNK260C 0x0000260c |
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285 | |||
286 | #define NVE4_COMPUTE_MP_PM_SET(i0) (0x0000335c + 0x4*(i0)) |
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287 | #define NVE4_COMPUTE_MP_PM_SET__ESIZE 0x00000004 |
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288 | #define NVE4_COMPUTE_MP_PM_SET__LEN 0x00000008 |
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289 | |||
290 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL(i0) (0x0000337c + 0x4*(i0)) |
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291 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL__ESIZE 0x00000004 |
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292 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL__LEN 0x00000004 |
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293 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_NONE 0x00000000 |
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294 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_USER 0x00000001 |
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295 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LAUNCH 0x00000003 |
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296 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_EXEC 0x00000004 |
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297 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_ISSUE 0x00000005 |
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298 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LDST 0x0000001b |
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299 | #define NVE4_COMPUTE_MP_PM_A_SIGSEL_BRANCH 0x0000001c |
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300 | |||
301 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL(i0) (0x0000338c + 0x4*(i0)) |
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302 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL__ESIZE 0x00000004 |
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303 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL__LEN 0x00000004 |
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304 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL_NONE 0x00000000 |
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305 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL_WARP 0x00000002 |
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306 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL_L1 0x00000010 |
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307 | #define NVE4_COMPUTE_MP_PM_B_SIGSEL_MEM 0x00000011 |
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308 | |||
309 | #define NVE4_COMPUTE_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0)) |
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310 | #define NVE4_COMPUTE_MP_PM_SRCSEL__ESIZE 0x00000004 |
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311 | #define NVE4_COMPUTE_MP_PM_SRCSEL__LEN 0x00000008 |
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312 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__MASK 0x00000003 |
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313 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__SHIFT 0 |
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314 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__MASK 0x0000001c |
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315 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__SHIFT 2 |
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316 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__MASK 0x00000060 |
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317 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__SHIFT 5 |
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318 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__MASK 0x00000380 |
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319 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__SHIFT 7 |
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320 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__MASK 0x00000c00 |
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321 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__SHIFT 10 |
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322 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__MASK 0x00007000 |
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323 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__SHIFT 12 |
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324 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__MASK 0x00018000 |
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325 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__SHIFT 15 |
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326 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__MASK 0x000e0000 |
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327 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__SHIFT 17 |
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328 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__MASK 0x00300000 |
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329 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__SHIFT 20 |
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330 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__MASK 0x01c00000 |
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331 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__SHIFT 22 |
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332 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__MASK 0x06000000 |
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333 | #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__SHIFT 25 |
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334 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__MASK 0x38000000 |
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335 | #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__SHIFT 27 |
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336 | |||
337 | #define NVE4_COMPUTE_MP_PM_FUNC(i0) (0x000033bc + 0x4*(i0)) |
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338 | #define NVE4_COMPUTE_MP_PM_FUNC__ESIZE 0x00000004 |
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339 | #define NVE4_COMPUTE_MP_PM_FUNC__LEN 0x00000008 |
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340 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE__MASK 0x0000000f |
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341 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE__SHIFT 0 |
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342 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP 0x00000000 |
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343 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_PULSE 0x00000001 |
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344 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_B6 0x00000002 |
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345 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK3 0x00000003 |
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346 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6 0x00000004 |
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347 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6_PULSE 0x00000005 |
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348 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK6 0x00000006 |
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349 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK7 0x00000007 |
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350 | #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK8 0x00000008 |
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351 | #define NVE4_COMPUTE_MP_PM_FUNC_FUNC__MASK 0x000ffff0 |
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352 | #define NVE4_COMPUTE_MP_PM_FUNC_FUNC__SHIFT 4 |
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353 | |||
354 | #define NVE4_COMPUTE_MP_PM_UNK33DC 0x000033dc |
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355 | |||
356 | #define NVE4_COMPUTE_LAUNCH_DESC__SIZE 0x00000100 |
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357 | #define NVE4_COMPUTE_LAUNCH_DESC_6 0x00000018 |
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358 | #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__MASK 0x00000c00 |
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359 | #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__SHIFT 10 |
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360 | |||
361 | #define NVE4_COMPUTE_LAUNCH_DESC_PROG_START 0x00000020 |
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362 | |||
363 | #define NVE4_COMPUTE_LAUNCH_DESC_12 0x00000030 |
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364 | #define NVE4_COMPUTE_LAUNCH_DESC_12_GRIDDIM_X__MASK 0x7fffffff |
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365 | #define NVE4_COMPUTE_LAUNCH_DESC_12_GRIDDIM_X__SHIFT 0 |
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366 | |||
367 | #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ 0x00000034 |
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368 | #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Y__MASK 0x0000ffff |
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369 | #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Y__SHIFT 0 |
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370 | #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Z__MASK 0xffff0000 |
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371 | #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Z__SHIFT 16 |
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372 | |||
373 | #define NVE4_COMPUTE_LAUNCH_DESC_17 0x00000044 |
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374 | #define NVE4_COMPUTE_LAUNCH_DESC_17_SHARED_ALLOC__MASK 0x0000ffff |
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375 | #define NVE4_COMPUTE_LAUNCH_DESC_17_SHARED_ALLOC__SHIFT 0 |
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376 | |||
377 | #define NVE4_COMPUTE_LAUNCH_DESC_18 0x00000048 |
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378 | #define NVE4_COMPUTE_LAUNCH_DESC_18_BLOCKDIM_X__MASK 0xffff0000 |
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379 | #define NVE4_COMPUTE_LAUNCH_DESC_18_BLOCKDIM_X__SHIFT 16 |
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380 | |||
381 | #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ 0x0000004c |
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382 | #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Y__MASK 0x0000ffff |
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383 | #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Y__SHIFT 0 |
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384 | #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Z__MASK 0xffff0000 |
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385 | #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Z__SHIFT 16 |
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386 | |||
387 | #define NVE4_COMPUTE_LAUNCH_DESC_20 0x00000050 |
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388 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CB_VALID__MASK 0x000000ff |
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389 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CB_VALID__SHIFT 0 |
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390 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT__MASK 0x60000000 |
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391 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT__SHIFT 29 |
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392 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_16K_SHARED_48K_L1 0x20000000 |
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393 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_32K_SHARED_32K_L1 0x40000000 |
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394 | #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_48K_SHARED_16K_L1 0x60000000 |
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395 | |||
396 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0(i0) (0x00000074 + 0x8*(i0)) |
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397 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0__ESIZE 0x00000008 |
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398 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0__LEN 0x00000008 |
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399 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0_ADDRESS_LOW__MASK 0xffffffff |
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400 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0_ADDRESS_LOW__SHIFT 0 |
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401 | |||
402 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1(i0) (0x00000078 + 0x8*(i0)) |
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403 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1__ESIZE 0x00000008 |
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404 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1__LEN 0x00000008 |
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405 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_ADDRESS_HIGH__MASK 0x000000ff |
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406 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_ADDRESS_HIGH__SHIFT 0 |
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407 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_SIZE__MASK 0xffff8000 |
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408 | #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_SIZE__SHIFT 15 |
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409 | |||
410 | #define NVE4_COMPUTE_LAUNCH_DESC_45 0x000000b4 |
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411 | #define NVE4_COMPUTE_LAUNCH_DESC_45_LOCAL_POS_ALLOC__MASK 0x000fffff |
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412 | #define NVE4_COMPUTE_LAUNCH_DESC_45_LOCAL_POS_ALLOC__SHIFT 0 |
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413 | #define NVE4_COMPUTE_LAUNCH_DESC_45_BARRIER_ALLOC__MASK 0xf8000000 |
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414 | #define NVE4_COMPUTE_LAUNCH_DESC_45_BARRIER_ALLOC__SHIFT 27 |
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415 | |||
416 | #define NVE4_COMPUTE_LAUNCH_DESC_46 0x000000b8 |
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417 | #define NVE4_COMPUTE_LAUNCH_DESC_46_LOCAL_NEG_ALLOC__MASK 0x000fffff |
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418 | #define NVE4_COMPUTE_LAUNCH_DESC_46_LOCAL_NEG_ALLOC__SHIFT 0 |
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419 | #define NVE4_COMPUTE_LAUNCH_DESC_46_GPR_ALLOC__MASK 0x3f000000 |
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420 | #define NVE4_COMPUTE_LAUNCH_DESC_46_GPR_ALLOC__SHIFT 24 |
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421 | |||
422 | #define NVE4_COMPUTE_LAUNCH_DESC_47 0x000000bc |
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423 | #define NVE4_COMPUTE_LAUNCH_DESC_47_WARP_CSTACK_SIZE__MASK 0x000fffff |
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424 | #define NVE4_COMPUTE_LAUNCH_DESC_47_WARP_CSTACK_SIZE__SHIFT 0 |
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425 | |||
426 | |||
427 | #endif /* NVE4_COMPUTE_XML */ |