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Rev | Author | Line No. | Line |
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4358 | Serge | 1 | /* |
2 | * Copyright 2008 Ben Skeggs |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | */ |
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22 | |||
23 | #include "nv50_context.h" |
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24 | #include "nv50_resource.h" |
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25 | #include "nv50_texture.xml.h" |
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26 | #include "nv50_defs.xml.h" |
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27 | |||
28 | #include "util/u_format.h" |
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29 | |||
30 | #define NV50_TIC_0_SWIZZLE__MASK \ |
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31 | (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \ |
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32 | NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK) |
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33 | |||
34 | static INLINE uint32_t |
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35 | nv50_tic_swizzle(uint32_t tc, unsigned swz, boolean tex_int) |
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36 | { |
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37 | switch (swz) { |
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38 | case PIPE_SWIZZLE_RED: |
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39 | return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT; |
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40 | case PIPE_SWIZZLE_GREEN: |
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41 | return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT; |
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42 | case PIPE_SWIZZLE_BLUE: |
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43 | return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT; |
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44 | case PIPE_SWIZZLE_ALPHA: |
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45 | return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT; |
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46 | case PIPE_SWIZZLE_ONE: |
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47 | return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT; |
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48 | case PIPE_SWIZZLE_ZERO: |
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49 | default: |
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50 | return NV50_TIC_MAP_ZERO; |
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51 | } |
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52 | } |
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53 | |||
54 | struct pipe_sampler_view * |
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55 | nv50_create_sampler_view(struct pipe_context *pipe, |
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56 | struct pipe_resource *res, |
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57 | const struct pipe_sampler_view *templ) |
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58 | { |
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59 | uint32_t flags = 0; |
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60 | |||
61 | if (res->target == PIPE_TEXTURE_RECT || res->target == PIPE_BUFFER) |
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62 | flags |= NV50_TEXVIEW_SCALED_COORDS; |
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63 | |||
64 | return nv50_create_texture_view(pipe, res, templ, flags, res->target); |
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65 | } |
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66 | |||
67 | struct pipe_sampler_view * |
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68 | nv50_create_texture_view(struct pipe_context *pipe, |
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69 | struct pipe_resource *texture, |
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70 | const struct pipe_sampler_view *templ, |
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71 | uint32_t flags, |
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72 | enum pipe_texture_target target) |
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73 | { |
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74 | const struct util_format_description *desc; |
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75 | uint64_t addr; |
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76 | uint32_t *tic; |
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77 | uint32_t swz[4]; |
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78 | uint32_t depth; |
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79 | struct nv50_tic_entry *view; |
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80 | struct nv50_miptree *mt = nv50_miptree(texture); |
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81 | boolean tex_int; |
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82 | |||
83 | view = MALLOC_STRUCT(nv50_tic_entry); |
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84 | if (!view) |
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85 | return NULL; |
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86 | |||
87 | view->pipe = *templ; |
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88 | view->pipe.reference.count = 1; |
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89 | view->pipe.texture = NULL; |
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90 | view->pipe.context = pipe; |
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91 | |||
92 | view->id = -1; |
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93 | |||
94 | pipe_resource_reference(&view->pipe.texture, texture); |
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95 | |||
96 | tic = &view->tic[0]; |
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97 | |||
98 | desc = util_format_description(view->pipe.format); |
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99 | |||
100 | /* TIC[0] */ |
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101 | |||
102 | tic[0] = nv50_format_table[view->pipe.format].tic; |
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103 | |||
104 | tex_int = util_format_is_pure_integer(view->pipe.format); |
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105 | |||
106 | swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int); |
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107 | swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int); |
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108 | swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int); |
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109 | swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int); |
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110 | tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) | |
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111 | (swz[0] << NV50_TIC_0_MAPR__SHIFT) | |
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112 | (swz[1] << NV50_TIC_0_MAPG__SHIFT) | |
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113 | (swz[2] << NV50_TIC_0_MAPB__SHIFT) | |
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114 | (swz[3] << NV50_TIC_0_MAPA__SHIFT); |
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115 | |||
116 | addr = mt->base.address; |
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117 | |||
118 | if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY || |
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119 | mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) { |
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120 | addr += view->pipe.u.tex.first_layer * mt->layer_stride; |
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121 | depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1; |
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122 | } else { |
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123 | depth = mt->base.base.depth0; |
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124 | } |
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125 | |||
126 | tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER; |
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127 | |||
128 | if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) |
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129 | tic[2] |= NV50_TIC_2_COLORSPACE_SRGB; |
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130 | |||
131 | if (!(flags & NV50_TEXVIEW_SCALED_COORDS)) |
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132 | tic[2] |= NV50_TIC_2_NORMALIZED_COORDS; |
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133 | |||
134 | if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) { |
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135 | if (target == PIPE_BUFFER) { |
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136 | addr += view->pipe.u.buf.first_element * desc->block.bits / 8; |
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137 | tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER; |
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138 | tic[3] = 0; |
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139 | tic[4] = /* width */ |
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140 | view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1; |
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141 | tic[5] = 0; |
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142 | } else { |
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143 | tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT; |
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144 | tic[3] = mt->level[0].pitch; |
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145 | tic[4] = mt->base.base.width0; |
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146 | tic[5] = (1 << 16) | mt->base.base.height0; |
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147 | } |
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148 | tic[6] = |
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149 | tic[7] = 0; |
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150 | tic[1] = addr; |
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151 | tic[2] |= addr >> 32; |
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152 | return &view->pipe; |
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153 | } |
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154 | |||
155 | tic[1] = addr; |
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156 | tic[2] |= (addr >> 32) & 0xff; |
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157 | |||
158 | tic[2] |= |
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159 | ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) | |
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160 | ((mt->level[0].tile_mode & 0xf00) << (25 - 8)); |
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161 | |||
162 | switch (target) { |
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163 | case PIPE_TEXTURE_1D: |
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164 | tic[2] |= NV50_TIC_2_TARGET_1D; |
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165 | break; |
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166 | case PIPE_TEXTURE_2D: |
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167 | tic[2] |= NV50_TIC_2_TARGET_2D; |
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168 | break; |
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169 | case PIPE_TEXTURE_RECT: |
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170 | tic[2] |= NV50_TIC_2_TARGET_RECT; |
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171 | break; |
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172 | case PIPE_TEXTURE_3D: |
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173 | tic[2] |= NV50_TIC_2_TARGET_3D; |
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174 | break; |
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175 | case PIPE_TEXTURE_CUBE: |
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176 | depth /= 6; |
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177 | tic[2] |= NV50_TIC_2_TARGET_CUBE; |
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178 | break; |
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179 | case PIPE_TEXTURE_1D_ARRAY: |
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180 | tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY; |
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181 | break; |
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182 | case PIPE_TEXTURE_2D_ARRAY: |
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183 | tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY; |
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184 | break; |
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185 | case PIPE_TEXTURE_CUBE_ARRAY: |
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186 | depth /= 6; |
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187 | tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY; |
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188 | break; |
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189 | case PIPE_BUFFER: |
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190 | assert(0); /* should be linear and handled above ! */ |
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191 | tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR; |
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192 | break; |
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193 | default: |
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194 | NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target); |
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195 | return FALSE; |
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196 | } |
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197 | |||
198 | tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000; |
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199 | |||
200 | tic[4] = (1 << 31) | (mt->base.base.width0 << mt->ms_x); |
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201 | |||
202 | tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff; |
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203 | tic[5] |= depth << 16; |
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204 | tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT; |
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205 | |||
206 | tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */ |
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207 | |||
208 | tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level; |
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209 | |||
210 | if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS))) |
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211 | if (mt->base.base.last_level) |
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212 | tic[5] &= ~NV50_TIC_5_LAST_LEVEL__MASK; |
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213 | |||
214 | return &view->pipe; |
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215 | } |
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216 | |||
217 | static boolean |
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218 | nv50_validate_tic(struct nv50_context *nv50, int s) |
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219 | { |
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220 | struct nouveau_pushbuf *push = nv50->base.pushbuf; |
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221 | struct nouveau_bo *txc = nv50->screen->txc; |
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222 | unsigned i; |
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223 | boolean need_flush = FALSE; |
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224 | |||
225 | for (i = 0; i < nv50->num_textures[s]; ++i) { |
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226 | struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]); |
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227 | struct nv04_resource *res; |
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228 | |||
229 | if (!tic) { |
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230 | BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1); |
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231 | PUSH_DATA (push, (i << 1) | 0); |
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232 | continue; |
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233 | } |
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234 | res = &nv50_miptree(tic->pipe.texture)->base; |
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235 | |||
236 | if (tic->id < 0) { |
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237 | tic->id = nv50_screen_tic_alloc(nv50->screen, tic); |
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238 | |||
239 | BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2); |
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240 | PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM); |
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241 | PUSH_DATA (push, 1); |
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242 | BEGIN_NV04(push, NV50_2D(DST_PITCH), 5); |
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243 | PUSH_DATA (push, 262144); |
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244 | PUSH_DATA (push, 65536); |
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245 | PUSH_DATA (push, 1); |
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246 | PUSH_DATAh(push, txc->offset); |
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247 | PUSH_DATA (push, txc->offset); |
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248 | BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2); |
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249 | PUSH_DATA (push, 0); |
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250 | PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM); |
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251 | BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10); |
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252 | PUSH_DATA (push, 32); |
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253 | PUSH_DATA (push, 1); |
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254 | PUSH_DATA (push, 0); |
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255 | PUSH_DATA (push, 1); |
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256 | PUSH_DATA (push, 0); |
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257 | PUSH_DATA (push, 1); |
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258 | PUSH_DATA (push, 0); |
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259 | PUSH_DATA (push, tic->id * 32); |
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260 | PUSH_DATA (push, 0); |
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261 | PUSH_DATA (push, 0); |
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262 | BEGIN_NI04(push, NV50_2D(SIFC_DATA), 8); |
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263 | PUSH_DATAp(push, &tic->tic[0], 8); |
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264 | |||
265 | need_flush = TRUE; |
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266 | } else |
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267 | if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { |
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268 | BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1); |
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269 | PUSH_DATA (push, 0x20); |
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270 | } |
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271 | |||
272 | nv50->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32); |
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273 | |||
4401 | Serge | 274 | res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; |
4358 | Serge | 275 | res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING; |
276 | |||
277 | BCTX_REFN(nv50->bufctx_3d, TEXTURES, res, RD); |
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278 | |||
279 | BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1); |
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280 | PUSH_DATA (push, (tic->id << 9) | (i << 1) | 1); |
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281 | } |
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282 | for (; i < nv50->state.num_textures[s]; ++i) { |
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283 | BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1); |
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284 | PUSH_DATA (push, (i << 1) | 0); |
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285 | } |
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286 | nv50->state.num_textures[s] = nv50->num_textures[s]; |
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287 | |||
288 | return need_flush; |
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289 | } |
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290 | |||
291 | void nv50_validate_textures(struct nv50_context *nv50) |
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292 | { |
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293 | boolean need_flush; |
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294 | |||
295 | need_flush = nv50_validate_tic(nv50, 0); |
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296 | need_flush |= nv50_validate_tic(nv50, 2); |
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297 | |||
298 | if (need_flush) { |
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299 | BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TIC_FLUSH), 1); |
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300 | PUSH_DATA (nv50->base.pushbuf, 0); |
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301 | } |
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302 | } |
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303 | |||
304 | static boolean |
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305 | nv50_validate_tsc(struct nv50_context *nv50, int s) |
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306 | { |
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307 | struct nouveau_pushbuf *push = nv50->base.pushbuf; |
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308 | unsigned i; |
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309 | boolean need_flush = FALSE; |
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310 | |||
311 | for (i = 0; i < nv50->num_samplers[s]; ++i) { |
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312 | struct nv50_tsc_entry *tsc = nv50_tsc_entry(nv50->samplers[s][i]); |
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313 | |||
314 | if (!tsc) { |
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315 | BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1); |
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316 | PUSH_DATA (push, (i << 4) | 0); |
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317 | continue; |
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318 | } |
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319 | if (tsc->id < 0) { |
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320 | tsc->id = nv50_screen_tsc_alloc(nv50->screen, tsc); |
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321 | |||
322 | nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc, |
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323 | 65536 + tsc->id * 32, |
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324 | NOUVEAU_BO_VRAM, 32, tsc->tsc); |
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325 | need_flush = TRUE; |
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326 | } |
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327 | nv50->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32); |
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328 | |||
329 | BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1); |
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330 | PUSH_DATA (push, (tsc->id << 12) | (i << 4) | 1); |
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331 | } |
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332 | for (; i < nv50->state.num_samplers[s]; ++i) { |
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333 | BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1); |
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334 | PUSH_DATA (push, (i << 4) | 0); |
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335 | } |
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336 | nv50->state.num_samplers[s] = nv50->num_samplers[s]; |
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337 | |||
338 | return need_flush; |
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339 | } |
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340 | |||
341 | void nv50_validate_samplers(struct nv50_context *nv50) |
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342 | { |
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343 | boolean need_flush; |
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344 | |||
345 | need_flush = nv50_validate_tsc(nv50, 0); |
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346 | need_flush |= nv50_validate_tsc(nv50, 2); |
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347 | |||
348 | if (need_flush) { |
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349 | BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TSC_FLUSH), 1); |
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350 | PUSH_DATA (nv50->base.pushbuf, 0); |
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351 | } |
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352 | }><>>><>><>><>>><>>><>>><>><>><>>><>>><>><>><>><>><>><>><>><>><>><>><>><>><> |