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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4358 | Serge | 1 | /* |
| 2 | * Copyright 2010 Christoph Bumiller |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | */ |
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| 22 | |||
| 23 | #include "util/u_format.h" |
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| 24 | #include "util/u_format_s3tc.h" |
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| 25 | #include "pipe/p_screen.h" |
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| 26 | |||
| 27 | #include "nv50_context.h" |
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| 28 | #include "nv50_screen.h" |
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| 29 | |||
| 30 | #include "nouveau/nv_object.xml.h" |
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| 31 | #include |
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| 32 | |||
| 33 | #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS |
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| 34 | # define NOUVEAU_GETPARAM_GRAPH_UNITS 13 |
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| 35 | #endif |
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| 36 | |||
| 37 | /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */ |
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| 38 | #define LOCAL_WARPS_ALLOC 32 |
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| 39 | /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */ |
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| 40 | #define STACK_WARPS_ALLOC 32 |
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| 41 | |||
| 42 | #define THREADS_IN_WARP 32 |
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| 43 | |||
| 44 | #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float)) |
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| 45 | |||
| 46 | static boolean |
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| 47 | nv50_screen_is_format_supported(struct pipe_screen *pscreen, |
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| 48 | enum pipe_format format, |
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| 49 | enum pipe_texture_target target, |
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| 50 | unsigned sample_count, |
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| 51 | unsigned bindings) |
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| 52 | { |
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| 53 | if (sample_count > 8) |
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| 54 | return FALSE; |
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| 55 | if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ |
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| 56 | return FALSE; |
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| 57 | if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) |
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| 58 | return FALSE; |
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| 59 | |||
| 60 | if (!util_format_is_supported(format, bindings)) |
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| 61 | return FALSE; |
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| 62 | |||
| 63 | switch (format) { |
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| 64 | case PIPE_FORMAT_Z16_UNORM: |
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| 65 | if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS) |
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| 66 | return FALSE; |
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| 67 | break; |
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| 68 | default: |
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| 69 | break; |
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| 70 | } |
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| 71 | |||
| 72 | /* transfers & shared are always supported */ |
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| 73 | bindings &= ~(PIPE_BIND_TRANSFER_READ | |
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| 74 | PIPE_BIND_TRANSFER_WRITE | |
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| 75 | PIPE_BIND_SHARED); |
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| 76 | |||
| 77 | return (nv50_format_table[format].usage & bindings) == bindings; |
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| 78 | } |
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| 79 | |||
| 80 | static int |
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| 81 | nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) |
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| 82 | { |
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| 83 | const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; |
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| 84 | |||
| 85 | switch (param) { |
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| 86 | case PIPE_CAP_MAX_COMBINED_SAMPLERS: |
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| 87 | return 64; |
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| 88 | case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: |
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| 89 | return 14; |
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| 90 | case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: |
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| 91 | return 12; |
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| 92 | case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: |
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| 93 | return 14; |
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| 94 | case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: |
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| 95 | return 512; |
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| 96 | case PIPE_CAP_MIN_TEXEL_OFFSET: |
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| 97 | return -8; |
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| 98 | case PIPE_CAP_MAX_TEXEL_OFFSET: |
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| 99 | return 7; |
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| 100 | case PIPE_CAP_TEXTURE_MIRROR_CLAMP: |
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| 101 | case PIPE_CAP_TEXTURE_SWIZZLE: |
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| 102 | case PIPE_CAP_TEXTURE_SHADOW_MAP: |
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| 103 | case PIPE_CAP_NPOT_TEXTURES: |
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| 104 | case PIPE_CAP_ANISOTROPIC_FILTER: |
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| 105 | case PIPE_CAP_SCALED_RESOLVE: |
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| 106 | case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: |
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| 107 | return 1; |
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| 108 | case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: |
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| 109 | return 65536; |
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| 110 | case PIPE_CAP_SEAMLESS_CUBE_MAP: |
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| 111 | return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; |
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| 112 | case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: |
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| 113 | return 0; |
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| 114 | case PIPE_CAP_CUBE_MAP_ARRAY: |
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| 115 | return 0; |
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| 116 | /* |
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| 117 | return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS; |
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| 118 | */ |
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| 119 | case PIPE_CAP_TWO_SIDED_STENCIL: |
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| 120 | case PIPE_CAP_DEPTH_CLIP_DISABLE: |
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| 121 | case PIPE_CAP_POINT_SPRITE: |
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| 122 | return 1; |
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| 123 | case PIPE_CAP_SM3: |
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| 124 | return 1; |
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| 125 | case PIPE_CAP_GLSL_FEATURE_LEVEL: |
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| 126 | return 140; |
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| 127 | case PIPE_CAP_MAX_RENDER_TARGETS: |
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| 128 | return 8; |
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| 129 | case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: |
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| 130 | return 1; |
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| 131 | case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: |
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| 132 | case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: |
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| 133 | case PIPE_CAP_VERTEX_COLOR_CLAMPED: |
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| 134 | return 1; |
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| 135 | case PIPE_CAP_QUERY_TIMESTAMP: |
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| 136 | case PIPE_CAP_QUERY_TIME_ELAPSED: |
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| 137 | case PIPE_CAP_OCCLUSION_QUERY: |
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| 138 | return 1; |
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| 139 | case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: |
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| 140 | return 4; |
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| 141 | case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: |
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| 142 | case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: |
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| 143 | return 64; |
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| 144 | case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: |
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| 145 | return (class_3d >= NVA0_3D_CLASS) ? 1 : 0; |
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| 146 | case PIPE_CAP_BLEND_EQUATION_SEPARATE: |
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| 147 | case PIPE_CAP_INDEP_BLEND_ENABLE: |
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| 148 | return 1; |
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| 149 | case PIPE_CAP_INDEP_BLEND_FUNC: |
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| 150 | return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS; |
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| 151 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: |
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| 152 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: |
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| 153 | return 1; |
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| 154 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: |
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| 155 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: |
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| 156 | return 0; |
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| 157 | case PIPE_CAP_SHADER_STENCIL_EXPORT: |
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| 158 | return 0; |
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| 159 | case PIPE_CAP_PRIMITIVE_RESTART: |
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| 160 | case PIPE_CAP_TGSI_INSTANCEID: |
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| 161 | case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: |
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| 162 | case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: |
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| 163 | case PIPE_CAP_CONDITIONAL_RENDER: |
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| 164 | case PIPE_CAP_TEXTURE_BARRIER: |
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| 165 | case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: |
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| 166 | case PIPE_CAP_START_INSTANCE: |
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| 167 | return 1; |
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| 168 | case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: |
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| 169 | return 0; /* state trackers will know better */ |
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| 170 | case PIPE_CAP_USER_CONSTANT_BUFFERS: |
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| 171 | case PIPE_CAP_USER_INDEX_BUFFERS: |
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| 172 | case PIPE_CAP_USER_VERTEX_BUFFERS: |
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| 173 | return 1; |
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| 174 | case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: |
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| 175 | return 256; |
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| 176 | case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: |
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| 177 | return 1; /* 256 for binding as RT, but that's not possible in GL */ |
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| 178 | case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: |
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| 179 | return NOUVEAU_MIN_BUFFER_MAP_ALIGN; |
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| 180 | case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: |
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| 181 | case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: |
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| 182 | case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: |
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| 183 | case PIPE_CAP_TGSI_TEXCOORD: |
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| 184 | case PIPE_CAP_TEXTURE_MULTISAMPLE: |
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| 185 | return 0; |
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| 186 | case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: |
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| 187 | return 1; |
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| 188 | case PIPE_CAP_QUERY_PIPELINE_STATISTICS: |
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| 189 | return 0; |
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| 190 | case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: |
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| 191 | return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50; |
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| 192 | case PIPE_CAP_ENDIANNESS: |
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| 193 | return PIPE_ENDIAN_LITTLE; |
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| 194 | default: |
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| 195 | NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); |
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| 196 | return 0; |
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| 197 | } |
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| 198 | } |
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| 199 | |||
| 200 | static int |
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| 201 | nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, |
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| 202 | enum pipe_shader_cap param) |
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| 203 | { |
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| 204 | switch (shader) { |
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| 205 | case PIPE_SHADER_VERTEX: |
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| 206 | case PIPE_SHADER_GEOMETRY: |
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| 207 | case PIPE_SHADER_FRAGMENT: |
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| 208 | break; |
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| 209 | default: |
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| 210 | return 0; |
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| 211 | } |
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| 212 | |||
| 213 | switch (param) { |
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| 214 | case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: |
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| 215 | case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: |
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| 216 | case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: |
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| 217 | case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: |
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| 218 | return 16384; |
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| 219 | case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: |
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| 220 | return 4; |
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| 221 | case PIPE_SHADER_CAP_MAX_INPUTS: |
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| 222 | if (shader == PIPE_SHADER_VERTEX) |
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| 223 | return 32; |
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| 4401 | Serge | 224 | return 15; |
| 4358 | Serge | 225 | case PIPE_SHADER_CAP_MAX_CONSTS: |
| 226 | return 65536 / 16; |
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| 227 | case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: |
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| 228 | return NV50_MAX_PIPE_CONSTBUFS; |
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| 229 | case PIPE_SHADER_CAP_MAX_ADDRS: |
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| 230 | return 1; |
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| 231 | case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: |
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| 232 | case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: |
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| 233 | return shader != PIPE_SHADER_FRAGMENT; |
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| 234 | case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: |
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| 235 | case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: |
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| 236 | return 1; |
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| 237 | case PIPE_SHADER_CAP_MAX_PREDS: |
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| 238 | return 0; |
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| 239 | case PIPE_SHADER_CAP_MAX_TEMPS: |
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| 240 | return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE; |
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| 241 | case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: |
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| 242 | return 1; |
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| 243 | case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: |
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| 244 | return 0; |
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| 245 | case PIPE_SHADER_CAP_SUBROUTINES: |
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| 246 | return 0; /* please inline, or provide function declarations */ |
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| 247 | case PIPE_SHADER_CAP_INTEGERS: |
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| 248 | return 1; |
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| 249 | case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: |
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| 250 | return 32; |
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| 251 | default: |
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| 252 | NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); |
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| 253 | return 0; |
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| 254 | } |
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| 255 | } |
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| 256 | |||
| 257 | static float |
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| 258 | nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) |
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| 259 | { |
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| 260 | switch (param) { |
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| 261 | case PIPE_CAPF_MAX_LINE_WIDTH: |
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| 262 | case PIPE_CAPF_MAX_LINE_WIDTH_AA: |
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| 263 | return 10.0f; |
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| 264 | case PIPE_CAPF_MAX_POINT_WIDTH: |
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| 265 | case PIPE_CAPF_MAX_POINT_WIDTH_AA: |
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| 266 | return 64.0f; |
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| 267 | case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: |
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| 268 | return 16.0f; |
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| 269 | case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: |
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| 270 | return 4.0f; |
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| 271 | default: |
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| 272 | NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); |
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| 273 | return 0.0f; |
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| 274 | } |
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| 275 | } |
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| 276 | |||
| 277 | static void |
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| 278 | nv50_screen_destroy(struct pipe_screen *pscreen) |
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| 279 | { |
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| 280 | struct nv50_screen *screen = nv50_screen(pscreen); |
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| 281 | |||
| 282 | if (screen->base.fence.current) { |
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| 283 | nouveau_fence_wait(screen->base.fence.current); |
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| 284 | nouveau_fence_ref (NULL, &screen->base.fence.current); |
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| 285 | } |
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| 286 | if (screen->base.pushbuf) |
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| 287 | screen->base.pushbuf->user_priv = NULL; |
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| 288 | |||
| 289 | if (screen->blitter) |
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| 290 | nv50_blitter_destroy(screen); |
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| 291 | |||
| 292 | nouveau_bo_ref(NULL, &screen->code); |
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| 293 | nouveau_bo_ref(NULL, &screen->tls_bo); |
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| 294 | nouveau_bo_ref(NULL, &screen->stack_bo); |
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| 295 | nouveau_bo_ref(NULL, &screen->txc); |
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| 296 | nouveau_bo_ref(NULL, &screen->uniforms); |
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| 297 | nouveau_bo_ref(NULL, &screen->fence.bo); |
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| 298 | |||
| 299 | nouveau_heap_destroy(&screen->vp_code_heap); |
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| 300 | nouveau_heap_destroy(&screen->gp_code_heap); |
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| 301 | nouveau_heap_destroy(&screen->fp_code_heap); |
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| 302 | |||
| 303 | FREE(screen->tic.entries); |
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| 304 | |||
| 305 | nouveau_object_del(&screen->tesla); |
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| 306 | nouveau_object_del(&screen->eng2d); |
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| 307 | nouveau_object_del(&screen->m2mf); |
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| 308 | nouveau_object_del(&screen->sync); |
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| 309 | |||
| 310 | nouveau_screen_fini(&screen->base); |
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| 311 | |||
| 312 | FREE(screen); |
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| 313 | } |
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| 314 | |||
| 315 | static void |
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| 316 | nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) |
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| 317 | { |
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| 318 | struct nv50_screen *screen = nv50_screen(pscreen); |
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| 319 | struct nouveau_pushbuf *push = screen->base.pushbuf; |
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| 320 | |||
| 321 | /* we need to do it after possible flush in MARK_RING */ |
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| 322 | *sequence = ++screen->base.fence.sequence; |
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| 323 | |||
| 324 | PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4)); |
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| 325 | PUSH_DATAh(push, screen->fence.bo->offset); |
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| 326 | PUSH_DATA (push, screen->fence.bo->offset); |
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| 327 | PUSH_DATA (push, *sequence); |
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| 328 | PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | |
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| 329 | NV50_3D_QUERY_GET_UNK4 | |
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| 330 | NV50_3D_QUERY_GET_UNIT_CROP | |
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| 331 | NV50_3D_QUERY_GET_TYPE_QUERY | |
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| 332 | NV50_3D_QUERY_GET_QUERY_SELECT_ZERO | |
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| 333 | NV50_3D_QUERY_GET_SHORT); |
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| 334 | } |
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| 335 | |||
| 336 | static u32 |
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| 337 | nv50_screen_fence_update(struct pipe_screen *pscreen) |
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| 338 | { |
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| 339 | return nv50_screen(pscreen)->fence.map[0]; |
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| 340 | } |
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| 341 | |||
| 342 | static void |
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| 343 | nv50_screen_init_hwctx(struct nv50_screen *screen) |
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| 344 | { |
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| 345 | struct nouveau_pushbuf *push = screen->base.pushbuf; |
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| 346 | struct nv04_fifo *fifo; |
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| 347 | unsigned i; |
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| 348 | |||
| 349 | fifo = (struct nv04_fifo *)screen->base.channel->data; |
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| 350 | |||
| 351 | BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); |
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| 352 | PUSH_DATA (push, screen->m2mf->handle); |
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| 353 | BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3); |
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| 354 | PUSH_DATA (push, screen->sync->handle); |
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| 355 | PUSH_DATA (push, fifo->vram); |
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| 356 | PUSH_DATA (push, fifo->vram); |
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| 357 | |||
| 358 | BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); |
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| 359 | PUSH_DATA (push, screen->eng2d->handle); |
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| 360 | BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4); |
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| 361 | PUSH_DATA (push, screen->sync->handle); |
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| 362 | PUSH_DATA (push, fifo->vram); |
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| 363 | PUSH_DATA (push, fifo->vram); |
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| 364 | PUSH_DATA (push, fifo->vram); |
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| 365 | BEGIN_NV04(push, NV50_2D(OPERATION), 1); |
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| 366 | PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY); |
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| 367 | BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1); |
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| 368 | PUSH_DATA (push, 0); |
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| 369 | BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1); |
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| 370 | PUSH_DATA (push, 0); |
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| 371 | BEGIN_NV04(push, SUBC_2D(0x0888), 1); |
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| 372 | PUSH_DATA (push, 1); |
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| 373 | |||
| 374 | BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); |
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| 375 | PUSH_DATA (push, screen->tesla->handle); |
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| 376 | |||
| 377 | BEGIN_NV04(push, NV50_3D(COND_MODE), 1); |
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| 378 | PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS); |
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| 379 | |||
| 380 | BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1); |
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| 381 | PUSH_DATA (push, screen->sync->handle); |
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| 382 | BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11); |
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| 383 | for (i = 0; i < 11; ++i) |
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| 384 | PUSH_DATA(push, fifo->vram); |
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| 385 | BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN); |
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| 386 | for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i) |
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| 387 | PUSH_DATA(push, fifo->vram); |
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| 388 | |||
| 389 | BEGIN_NV04(push, NV50_3D(REG_MODE), 1); |
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| 390 | PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED); |
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| 391 | BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1); |
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| 392 | PUSH_DATA (push, 0xf); |
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| 393 | |||
| 394 | if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { |
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| 395 | BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1); |
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| 396 | PUSH_DATA (push, 0x18); |
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| 397 | } |
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| 398 | |||
| 399 | BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); |
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| 400 | PUSH_DATA (push, 1); |
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| 401 | |||
| 402 | BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1); |
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| 403 | PUSH_DATA (push, 0); |
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| 404 | BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1); |
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| 405 | PUSH_DATA (push, 0); |
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| 406 | BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1); |
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| 407 | PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1); |
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| 408 | BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1); |
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| 409 | PUSH_DATA (push, 0); |
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| 410 | BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1); |
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| 411 | PUSH_DATA (push, 0); |
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| 412 | BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1); |
||
| 413 | PUSH_DATA (push, 1); |
||
| 414 | |||
| 415 | if (screen->tesla->oclass >= NVA0_3D_CLASS) { |
||
| 416 | BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1); |
||
| 417 | PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); |
||
| 418 | } |
||
| 419 | |||
| 420 | BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1); |
||
| 421 | PUSH_DATA (push, 0); |
||
| 422 | BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2); |
||
| 423 | PUSH_DATA (push, 0); |
||
| 424 | PUSH_DATA (push, 0); |
||
| 425 | BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1); |
||
| 426 | PUSH_DATA (push, 0x3f); |
||
| 427 | |||
| 428 | BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2); |
||
| 429 | PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2)); |
||
| 430 | PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2)); |
||
| 431 | |||
| 432 | BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2); |
||
| 433 | PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2)); |
||
| 434 | PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2)); |
||
| 435 | |||
| 436 | BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2); |
||
| 437 | PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2)); |
||
| 438 | PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2)); |
||
| 439 | |||
| 440 | BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3); |
||
| 441 | PUSH_DATAh(push, screen->tls_bo->offset); |
||
| 442 | PUSH_DATA (push, screen->tls_bo->offset); |
||
| 443 | PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8)); |
||
| 444 | |||
| 445 | BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3); |
||
| 446 | PUSH_DATAh(push, screen->stack_bo->offset); |
||
| 447 | PUSH_DATA (push, screen->stack_bo->offset); |
||
| 448 | PUSH_DATA (push, 4); |
||
| 449 | |||
| 450 | BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); |
||
| 451 | PUSH_DATAh(push, screen->uniforms->offset + (0 << 16)); |
||
| 452 | PUSH_DATA (push, screen->uniforms->offset + (0 << 16)); |
||
| 453 | PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000); |
||
| 454 | |||
| 455 | BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); |
||
| 456 | PUSH_DATAh(push, screen->uniforms->offset + (1 << 16)); |
||
| 457 | PUSH_DATA (push, screen->uniforms->offset + (1 << 16)); |
||
| 458 | PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000); |
||
| 459 | |||
| 460 | BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); |
||
| 461 | PUSH_DATAh(push, screen->uniforms->offset + (2 << 16)); |
||
| 462 | PUSH_DATA (push, screen->uniforms->offset + (2 << 16)); |
||
| 463 | PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000); |
||
| 464 | |||
| 465 | BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); |
||
| 466 | PUSH_DATAh(push, screen->uniforms->offset + (3 << 16)); |
||
| 467 | PUSH_DATA (push, screen->uniforms->offset + (3 << 16)); |
||
| 468 | PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200); |
||
| 469 | |||
| 470 | BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3); |
||
| 471 | PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01); |
||
| 472 | PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21); |
||
| 473 | PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31); |
||
| 474 | |||
| 475 | /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */ |
||
| 476 | BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); |
||
| 477 | PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX); |
||
| 478 | BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4); |
||
| 479 | PUSH_DATAf(push, 0.0f); |
||
| 480 | PUSH_DATAf(push, 0.0f); |
||
| 481 | PUSH_DATAf(push, 0.0f); |
||
| 482 | PUSH_DATAf(push, 0.0f); |
||
| 483 | BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2); |
||
| 484 | PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9)); |
||
| 485 | PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9)); |
||
| 486 | |||
| 487 | /* max TIC (bits 4:8) & TSC bindings, per program type */ |
||
| 488 | for (i = 0; i < 3; ++i) { |
||
| 489 | BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1); |
||
| 490 | PUSH_DATA (push, 0x54); |
||
| 491 | } |
||
| 492 | |||
| 493 | BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3); |
||
| 494 | PUSH_DATAh(push, screen->txc->offset); |
||
| 495 | PUSH_DATA (push, screen->txc->offset); |
||
| 496 | PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1); |
||
| 497 | |||
| 498 | BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3); |
||
| 499 | PUSH_DATAh(push, screen->txc->offset + 65536); |
||
| 500 | PUSH_DATA (push, screen->txc->offset + 65536); |
||
| 501 | PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1); |
||
| 502 | |||
| 503 | BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1); |
||
| 504 | PUSH_DATA (push, 0); |
||
| 505 | |||
| 506 | BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1); |
||
| 507 | PUSH_DATA (push, 0); |
||
| 508 | BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1); |
||
| 509 | PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY); |
||
| 510 | BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2); |
||
| 511 | for (i = 0; i < 8 * 2; ++i) |
||
| 512 | PUSH_DATA(push, 0); |
||
| 513 | BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1); |
||
| 514 | PUSH_DATA (push, 0); |
||
| 515 | |||
| 516 | BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1); |
||
| 517 | PUSH_DATA (push, 1); |
||
| 518 | BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2); |
||
| 519 | PUSH_DATAf(push, 0.0f); |
||
| 520 | PUSH_DATAf(push, 1.0f); |
||
| 521 | |||
| 522 | BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1); |
||
| 523 | #ifdef NV50_SCISSORS_CLIPPING |
||
| 524 | PUSH_DATA (push, 0x0000); |
||
| 525 | #else |
||
| 526 | PUSH_DATA (push, 0x1080); |
||
| 527 | #endif |
||
| 528 | |||
| 529 | BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1); |
||
| 530 | PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT); |
||
| 531 | |||
| 532 | /* We use scissors instead of exact view volume clipping, |
||
| 533 | * so they're always enabled. |
||
| 534 | */ |
||
| 535 | BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3); |
||
| 536 | PUSH_DATA (push, 1); |
||
| 537 | PUSH_DATA (push, 8192 << 16); |
||
| 538 | PUSH_DATA (push, 8192 << 16); |
||
| 539 | |||
| 540 | BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1); |
||
| 541 | PUSH_DATA (push, 1); |
||
| 542 | BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1); |
||
| 543 | PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL); |
||
| 544 | BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1); |
||
| 545 | PUSH_DATA (push, 0x11111111); |
||
| 546 | BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1); |
||
| 547 | PUSH_DATA (push, 1); |
||
| 548 | |||
| 549 | PUSH_KICK (push); |
||
| 550 | } |
||
| 551 | |||
| 552 | static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space, |
||
| 553 | uint64_t *tls_size) |
||
| 554 | { |
||
| 555 | struct nouveau_device *dev = screen->base.device; |
||
| 556 | int ret; |
||
| 557 | |||
| 558 | screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) * |
||
| 559 | ONE_TEMP_SIZE; |
||
| 560 | if (nouveau_mesa_debug) |
||
| 561 | debug_printf("allocating space for %u temps\n", |
||
| 562 | util_next_power_of_two(tls_space / ONE_TEMP_SIZE)); |
||
| 563 | *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) * |
||
| 564 | screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP; |
||
| 565 | |||
| 566 | ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, |
||
| 567 | *tls_size, NULL, &screen->tls_bo); |
||
| 568 | if (ret) { |
||
| 569 | NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret); |
||
| 570 | return ret; |
||
| 571 | } |
||
| 572 | |||
| 573 | return 0; |
||
| 574 | } |
||
| 575 | |||
| 576 | int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space) |
||
| 577 | { |
||
| 578 | struct nouveau_pushbuf *push = screen->base.pushbuf; |
||
| 579 | int ret; |
||
| 580 | uint64_t tls_size; |
||
| 581 | |||
| 582 | if (tls_space < screen->cur_tls_space) |
||
| 583 | return 0; |
||
| 584 | if (tls_space > screen->max_tls_space) { |
||
| 585 | /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC / |
||
| 586 | * LOCAL_WARPS_NO_CLAMP) */ |
||
| 587 | NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n", |
||
| 588 | (unsigned)(tls_space / ONE_TEMP_SIZE), |
||
| 589 | (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE)); |
||
| 590 | return -ENOMEM; |
||
| 591 | } |
||
| 592 | |||
| 593 | nouveau_bo_ref(NULL, &screen->tls_bo); |
||
| 594 | ret = nv50_tls_alloc(screen, tls_space, &tls_size); |
||
| 595 | if (ret) |
||
| 596 | return ret; |
||
| 597 | |||
| 598 | BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3); |
||
| 599 | PUSH_DATAh(push, screen->tls_bo->offset); |
||
| 600 | PUSH_DATA (push, screen->tls_bo->offset); |
||
| 601 | PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8)); |
||
| 602 | |||
| 603 | return 1; |
||
| 604 | } |
||
| 605 | |||
| 606 | struct pipe_screen * |
||
| 607 | nv50_screen_create(struct nouveau_device *dev) |
||
| 608 | { |
||
| 609 | struct nv50_screen *screen; |
||
| 610 | struct pipe_screen *pscreen; |
||
| 611 | struct nouveau_object *chan; |
||
| 612 | uint64_t value; |
||
| 613 | uint32_t tesla_class; |
||
| 614 | unsigned stack_size; |
||
| 615 | int ret; |
||
| 616 | |||
| 617 | screen = CALLOC_STRUCT(nv50_screen); |
||
| 618 | if (!screen) |
||
| 619 | return NULL; |
||
| 620 | pscreen = &screen->base.base; |
||
| 621 | |||
| 622 | ret = nouveau_screen_init(&screen->base, dev); |
||
| 623 | if (ret) { |
||
| 624 | NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret); |
||
| 625 | goto fail; |
||
| 626 | } |
||
| 627 | |||
| 628 | /* TODO: Prevent FIFO prefetch before transfer of index buffers and |
||
| 629 | * admit them to VRAM. |
||
| 630 | */ |
||
| 631 | screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER | |
||
| 632 | PIPE_BIND_VERTEX_BUFFER; |
||
| 633 | screen->base.sysmem_bindings |= |
||
| 634 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER; |
||
| 635 | |||
| 636 | screen->base.pushbuf->user_priv = screen; |
||
| 637 | screen->base.pushbuf->rsvd_kick = 5; |
||
| 638 | |||
| 639 | chan = screen->base.channel; |
||
| 640 | |||
| 641 | pscreen->destroy = nv50_screen_destroy; |
||
| 642 | pscreen->context_create = nv50_create; |
||
| 643 | pscreen->is_format_supported = nv50_screen_is_format_supported; |
||
| 644 | pscreen->get_param = nv50_screen_get_param; |
||
| 645 | pscreen->get_shader_param = nv50_screen_get_shader_param; |
||
| 646 | pscreen->get_paramf = nv50_screen_get_paramf; |
||
| 647 | |||
| 648 | nv50_screen_init_resource_functions(pscreen); |
||
| 649 | |||
| 650 | if (screen->base.device->chipset < 0x84) { |
||
| 651 | /* PMPEG */ |
||
| 652 | nouveau_screen_init_vdec(&screen->base); |
||
| 653 | } else if (screen->base.device->chipset < 0x98 || |
||
| 654 | screen->base.device->chipset == 0xa0) { |
||
| 655 | /* VP2 */ |
||
| 656 | screen->base.base.get_video_param = nv84_screen_get_video_param; |
||
| 657 | screen->base.base.is_video_format_supported = nv84_screen_video_supported; |
||
| 658 | } else { |
||
| 659 | /* Unsupported, but need to init pointers. */ |
||
| 660 | nouveau_screen_init_vdec(&screen->base); |
||
| 661 | } |
||
| 662 | |||
| 663 | ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, |
||
| 664 | NULL, &screen->fence.bo); |
||
| 665 | if (ret) { |
||
| 666 | NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret); |
||
| 667 | goto fail; |
||
| 668 | } |
||
| 669 | |||
| 670 | nouveau_bo_map(screen->fence.bo, 0, NULL); |
||
| 671 | screen->fence.map = screen->fence.bo->map; |
||
| 672 | screen->base.fence.emit = nv50_screen_fence_emit; |
||
| 673 | screen->base.fence.update = nv50_screen_fence_update; |
||
| 674 | |||
| 675 | ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS, |
||
| 676 | &(struct nv04_notify){ .length = 32 }, |
||
| 677 | sizeof(struct nv04_notify), &screen->sync); |
||
| 678 | if (ret) { |
||
| 679 | NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret); |
||
| 680 | goto fail; |
||
| 681 | } |
||
| 682 | |||
| 683 | ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS, |
||
| 684 | NULL, 0, &screen->m2mf); |
||
| 685 | if (ret) { |
||
| 686 | NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret); |
||
| 687 | goto fail; |
||
| 688 | } |
||
| 689 | |||
| 690 | ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS, |
||
| 691 | NULL, 0, &screen->eng2d); |
||
| 692 | if (ret) { |
||
| 693 | NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret); |
||
| 694 | goto fail; |
||
| 695 | } |
||
| 696 | |||
| 697 | switch (dev->chipset & 0xf0) { |
||
| 698 | case 0x50: |
||
| 699 | tesla_class = NV50_3D_CLASS; |
||
| 700 | break; |
||
| 701 | case 0x80: |
||
| 702 | case 0x90: |
||
| 703 | tesla_class = NV84_3D_CLASS; |
||
| 704 | break; |
||
| 705 | case 0xa0: |
||
| 706 | switch (dev->chipset) { |
||
| 707 | case 0xa0: |
||
| 708 | case 0xaa: |
||
| 709 | case 0xac: |
||
| 710 | tesla_class = NVA0_3D_CLASS; |
||
| 711 | break; |
||
| 712 | case 0xaf: |
||
| 713 | tesla_class = NVAF_3D_CLASS; |
||
| 714 | break; |
||
| 715 | default: |
||
| 716 | tesla_class = NVA3_3D_CLASS; |
||
| 717 | break; |
||
| 718 | } |
||
| 719 | break; |
||
| 720 | default: |
||
| 721 | NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset); |
||
| 722 | goto fail; |
||
| 723 | } |
||
| 724 | screen->base.class_3d = tesla_class; |
||
| 725 | |||
| 726 | ret = nouveau_object_new(chan, 0xbeef5097, tesla_class, |
||
| 727 | NULL, 0, &screen->tesla); |
||
| 728 | if (ret) { |
||
| 729 | NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret); |
||
| 730 | goto fail; |
||
| 731 | } |
||
| 732 | |||
| 733 | ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, |
||
| 734 | 3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code); |
||
| 735 | if (ret) { |
||
| 736 | NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret); |
||
| 737 | goto fail; |
||
| 738 | } |
||
| 739 | |||
| 740 | nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); |
||
| 741 | nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); |
||
| 742 | nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); |
||
| 743 | |||
| 744 | nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value); |
||
| 745 | |||
| 746 | screen->TPs = util_bitcount(value & 0xffff); |
||
| 747 | screen->MPsInTP = util_bitcount((value >> 24) & 0xf); |
||
| 748 | |||
| 749 | stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP * |
||
| 750 | STACK_WARPS_ALLOC * 64 * 8; |
||
| 751 | |||
| 752 | ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL, |
||
| 753 | &screen->stack_bo); |
||
| 754 | if (ret) { |
||
| 755 | NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret); |
||
| 756 | goto fail; |
||
| 757 | } |
||
| 758 | |||
| 759 | uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) * |
||
| 760 | screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP * |
||
| 761 | ONE_TEMP_SIZE; |
||
| 762 | screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE; |
||
| 763 | screen->max_tls_space /= 2; /* half of vram */ |
||
| 764 | |||
| 765 | /* hw can address max 64 KiB */ |
||
| 766 | screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10); |
||
| 767 | |||
| 768 | uint64_t tls_size; |
||
| 769 | unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE; |
||
| 770 | ret = nv50_tls_alloc(screen, tls_space, &tls_size); |
||
| 771 | if (ret) |
||
| 772 | goto fail; |
||
| 773 | |||
| 774 | if (nouveau_mesa_debug) |
||
| 775 | debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n", |
||
| 776 | screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10); |
||
| 777 | |||
| 778 | ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL, |
||
| 779 | &screen->uniforms); |
||
| 780 | if (ret) { |
||
| 781 | NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret); |
||
| 782 | goto fail; |
||
| 783 | } |
||
| 784 | |||
| 785 | ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL, |
||
| 786 | &screen->txc); |
||
| 787 | if (ret) { |
||
| 788 | NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret); |
||
| 789 | goto fail; |
||
| 790 | } |
||
| 791 | |||
| 792 | screen->tic.entries = CALLOC(4096, sizeof(void *)); |
||
| 793 | screen->tsc.entries = screen->tic.entries + 2048; |
||
| 794 | |||
| 795 | if (!nv50_blitter_create(screen)) |
||
| 796 | goto fail; |
||
| 797 | |||
| 798 | nv50_screen_init_hwctx(screen); |
||
| 799 | |||
| 800 | nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); |
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| 801 | |||
| 802 | return pscreen; |
||
| 803 | |||
| 804 | fail: |
||
| 805 | nv50_screen_destroy(pscreen); |
||
| 806 | return NULL; |
||
| 807 | } |
||
| 808 | |||
| 809 | int |
||
| 810 | nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry) |
||
| 811 | { |
||
| 812 | int i = screen->tic.next; |
||
| 813 | |||
| 814 | while (screen->tic.lock[i / 32] & (1 << (i % 32))) |
||
| 815 | i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); |
||
| 816 | |||
| 817 | screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); |
||
| 818 | |||
| 819 | if (screen->tic.entries[i]) |
||
| 820 | nv50_tic_entry(screen->tic.entries[i])->id = -1; |
||
| 821 | |||
| 822 | screen->tic.entries[i] = entry; |
||
| 823 | return i; |
||
| 824 | } |
||
| 825 | |||
| 826 | int |
||
| 827 | nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry) |
||
| 828 | { |
||
| 829 | int i = screen->tsc.next; |
||
| 830 | |||
| 831 | while (screen->tsc.lock[i / 32] & (1 << (i % 32))) |
||
| 832 | i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); |
||
| 833 | |||
| 834 | screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); |
||
| 835 | |||
| 836 | if (screen->tsc.entries[i]) |
||
| 837 | nv50_tsc_entry(screen->tsc.entries[i])->id = -1; |
||
| 838 | |||
| 839 | screen->tsc.entries[i] = entry; |
||
| 840 | return i; |
||
| 841 | } |