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| 4358 | Serge | 1 | /* |
| 2 | * Copyright (c) 2013 Rob Clark |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 21 | * SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #ifndef IR3_H_ |
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| 25 | #define IR3_H_ |
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| 26 | |||
| 27 | #include |
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| 28 | #include |
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| 29 | |||
| 30 | #include "instr-a3xx.h" |
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| 31 | |||
| 32 | /* low level intermediate representation of an adreno shader program */ |
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| 33 | |||
| 34 | struct ir3_shader; |
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| 35 | |||
| 36 | struct ir3_shader * fd_asm_parse(const char *src); |
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| 37 | |||
| 38 | struct ir3_shader_info { |
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| 39 | uint16_t sizedwords; |
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| 40 | /* NOTE: max_reg, etc, does not include registers not touched |
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| 41 | * by the shader (ie. vertex fetched via VFD_DECODE but not |
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| 42 | * touched by shader) |
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| 43 | */ |
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| 44 | int8_t max_reg; /* highest GPR # used by shader */ |
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| 45 | int8_t max_half_reg; |
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| 46 | int8_t max_const; |
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| 47 | }; |
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| 48 | |||
| 49 | struct ir3_register { |
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| 50 | enum { |
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| 51 | IR3_REG_CONST = 0x001, |
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| 52 | IR3_REG_IMMED = 0x002, |
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| 53 | IR3_REG_HALF = 0x004, |
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| 54 | IR3_REG_RELATIV= 0x008, |
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| 55 | IR3_REG_R = 0x010, |
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| 56 | IR3_REG_NEGATE = 0x020, |
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| 57 | IR3_REG_ABS = 0x040, |
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| 58 | IR3_REG_EVEN = 0x080, |
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| 59 | IR3_REG_POS_INF= 0x100, |
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| 60 | /* (ei) flag, end-input? Set on last bary, presumably to signal |
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| 61 | * that the shader needs no more input: |
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| 62 | */ |
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| 63 | IR3_REG_EI = 0x200, |
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| 64 | } flags; |
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| 65 | union { |
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| 66 | /* normal registers: */ |
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| 67 | struct { |
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| 68 | /* the component is in the low two bits of the reg #, so |
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| 69 | * rN.x becomes: (n << 2) | x |
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| 70 | */ |
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| 71 | int num; |
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| 72 | int wrmask; |
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| 73 | }; |
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| 74 | /* immediate: */ |
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| 75 | int iim_val; |
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| 76 | float fim_val; |
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| 77 | /* relative: */ |
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| 78 | int offset; |
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| 79 | }; |
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| 80 | }; |
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| 81 | |||
| 82 | struct ir3_instruction { |
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| 83 | struct ir3_shader *shader; |
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| 84 | int category; |
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| 85 | opc_t opc; |
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| 86 | enum { |
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| 87 | /* (sy) flag is set on first instruction, and after sample |
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| 88 | * instructions (probably just on RAW hazard). |
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| 89 | */ |
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| 90 | IR3_INSTR_SY = 0x001, |
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| 91 | /* (ss) flag is set on first instruction, and first instruction |
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| 92 | * to depend on the result of "long" instructions (RAW hazard): |
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| 93 | * |
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| 94 | * rcp, rsq, log2, exp2, sin, cos, sqrt |
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| 95 | * |
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| 96 | * It seems to synchronize until all in-flight instructions are |
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| 97 | * completed, for example: |
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| 98 | * |
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| 99 | * rsq hr1.w, hr1.w |
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| 100 | * add.f hr2.z, (neg)hr2.z, hc0.y |
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| 101 | * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y |
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| 102 | * rsq hr2.x, hr2.x |
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| 103 | * (rpt1)nop |
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| 104 | * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w |
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| 105 | * nop |
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| 106 | * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w |
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| 107 | * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w |
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| 108 | * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x |
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| 109 | * |
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| 110 | * The last mul.f does not have (ss) set, presumably because the |
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| 111 | * (ss) on the previous instruction does the job. |
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| 112 | * |
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| 113 | * The blob driver also seems to set it on WAR hazards, although |
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| 114 | * not really clear if this is needed or just blob compiler being |
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| 115 | * sloppy. So far I haven't found a case where removing the (ss) |
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| 116 | * causes problems for WAR hazard, but I could just be getting |
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| 117 | * lucky: |
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| 118 | * |
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| 119 | * rcp r1.y, r3.y |
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| 120 | * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z |
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| 121 | * |
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| 122 | */ |
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| 123 | IR3_INSTR_SS = 0x002, |
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| 124 | /* (jp) flag is set on jump targets: |
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| 125 | */ |
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| 126 | IR3_INSTR_JP = 0x004, |
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| 127 | IR3_INSTR_UL = 0x008, |
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| 128 | IR3_INSTR_3D = 0x010, |
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| 129 | IR3_INSTR_A = 0x020, |
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| 130 | IR3_INSTR_O = 0x040, |
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| 131 | IR3_INSTR_P = 0x080, |
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| 132 | IR3_INSTR_S = 0x100, |
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| 133 | IR3_INSTR_S2EN = 0x200, |
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| 134 | } flags; |
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| 135 | int repeat; |
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| 136 | unsigned regs_count; |
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| 137 | struct ir3_register *regs[4]; |
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| 138 | union { |
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| 139 | struct { |
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| 140 | char inv; |
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| 141 | char comp; |
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| 142 | int immed; |
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| 143 | } cat0; |
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| 144 | struct { |
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| 145 | type_t src_type, dst_type; |
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| 146 | } cat1; |
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| 147 | struct { |
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| 148 | enum { |
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| 149 | IR3_COND_LT = 0, |
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| 150 | IR3_COND_LE = 1, |
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| 151 | IR3_COND_GT = 2, |
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| 152 | IR3_COND_GE = 3, |
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| 153 | IR3_COND_EQ = 4, |
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| 154 | IR3_COND_NE = 5, |
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| 155 | } condition; |
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| 156 | } cat2; |
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| 157 | struct { |
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| 158 | unsigned samp, tex; |
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| 159 | type_t type; |
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| 160 | } cat5; |
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| 161 | struct { |
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| 162 | type_t type; |
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| 163 | int offset; |
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| 164 | int iim_val; |
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| 165 | } cat6; |
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| 166 | }; |
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| 167 | }; |
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| 168 | |||
| 4401 | Serge | 169 | #define MAX_INSTRS 1024 |
| 4358 | Serge | 170 | |
| 171 | struct ir3_shader { |
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| 172 | unsigned instrs_count; |
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| 173 | struct ir3_instruction *instrs[MAX_INSTRS]; |
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| 174 | uint32_t heap[128 * MAX_INSTRS]; |
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| 175 | unsigned heap_idx; |
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| 176 | }; |
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| 177 | |||
| 178 | struct ir3_shader * ir3_shader_create(void); |
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| 179 | void ir3_shader_destroy(struct ir3_shader *shader); |
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| 180 | void * ir3_shader_assemble(struct ir3_shader *shader, |
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| 181 | struct ir3_shader_info *info); |
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| 182 | |||
| 183 | struct ir3_instruction * ir3_instr_create(struct ir3_shader *shader, int category, opc_t opc); |
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| 184 | struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr); |
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| 185 | |||
| 186 | struct ir3_register * ir3_reg_create(struct ir3_instruction *instr, |
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| 187 | int num, int flags); |
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| 188 | |||
| 189 | #endif /* IR3_H_ */ |