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4358 | Serge | 1 | /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ |
2 | |||
3 | /* |
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4 | * Copyright (C) 2013 Rob Clark |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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23 | * SOFTWARE. |
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24 | * |
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25 | * Authors: |
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26 | * Rob Clark |
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27 | */ |
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28 | |||
29 | #include "pipe/p_state.h" |
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30 | #include "util/u_string.h" |
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31 | #include "util/u_memory.h" |
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32 | #include "util/u_helpers.h" |
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33 | #include "util/u_format.h" |
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34 | |||
35 | #include "freedreno_resource.h" |
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36 | |||
37 | #include "fd3_emit.h" |
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38 | #include "fd3_blend.h" |
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39 | #include "fd3_context.h" |
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40 | #include "fd3_program.h" |
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41 | #include "fd3_rasterizer.h" |
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42 | #include "fd3_texture.h" |
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43 | #include "fd3_util.h" |
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44 | #include "fd3_zsa.h" |
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45 | |||
46 | /* regid: base const register |
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47 | * prsc or dwords: buffer containing constant values |
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48 | * sizedwords: size of const value buffer |
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49 | */ |
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50 | void |
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51 | fd3_emit_constant(struct fd_ringbuffer *ring, |
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52 | enum adreno_state_block sb, |
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53 | uint32_t regid, uint32_t offset, uint32_t sizedwords, |
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54 | const uint32_t *dwords, struct pipe_resource *prsc) |
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55 | { |
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56 | uint32_t i, sz; |
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57 | enum adreno_state_src src; |
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58 | |||
59 | if (prsc) { |
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60 | sz = 0; |
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61 | src = SS_INDIRECT; |
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62 | } else { |
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63 | sz = sizedwords; |
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64 | src = SS_DIRECT; |
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65 | } |
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66 | |||
67 | /* we have this sometimes, not others.. perhaps we could be clever |
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68 | * and figure out actually when we need to invalidate cache: |
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69 | */ |
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70 | OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2); |
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71 | OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0)); |
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72 | OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) | |
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73 | A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) | |
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74 | A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE); |
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75 | |||
76 | OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz); |
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77 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) | |
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78 | CP_LOAD_STATE_0_STATE_SRC(src) | |
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79 | CP_LOAD_STATE_0_STATE_BLOCK(sb) | |
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80 | CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2)); |
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81 | if (prsc) { |
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82 | struct fd_bo *bo = fd_resource(prsc)->bo; |
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83 | OUT_RELOC(ring, bo, offset, |
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4401 | Serge | 84 | CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0); |
4358 | Serge | 85 | } else { |
86 | OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) | |
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87 | CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS)); |
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88 | dwords = (uint32_t *)&((uint8_t *)dwords)[offset]; |
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89 | } |
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90 | for (i = 0; i < sz; i++) { |
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91 | OUT_RING(ring, dwords[i]); |
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92 | } |
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93 | } |
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94 | |||
95 | static void |
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96 | emit_constants(struct fd_ringbuffer *ring, |
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97 | enum adreno_state_block sb, |
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98 | struct fd_constbuf_stateobj *constbuf, |
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99 | struct fd3_shader_stateobj *shader) |
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100 | { |
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101 | uint32_t enabled_mask = constbuf->enabled_mask; |
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102 | uint32_t base = 0; |
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103 | unsigned i; |
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104 | |||
105 | // XXX TODO only emit dirty consts.. but we need to keep track if |
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106 | // they are clobbered by a clear, gmem2mem, or mem2gmem.. |
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107 | constbuf->dirty_mask = enabled_mask; |
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108 | |||
109 | /* emit user constants: */ |
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110 | while (enabled_mask) { |
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111 | unsigned index = ffs(enabled_mask) - 1; |
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112 | struct pipe_constant_buffer *cb = &constbuf->cb[index]; |
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113 | unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */ |
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114 | |||
115 | // I expect that size should be a multiple of vec4's: |
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116 | assert(size == align(size, 4)); |
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117 | |||
118 | /* gallium could have const-buffer still bound, even though the |
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119 | * shader is not using it. Writing consts above constlen (or |
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120 | * rather, HLSQ_{VS,FS}_CONTROL_REG.CONSTLENGTH) will cause a |
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121 | * hang. |
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122 | */ |
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123 | if ((base / 4) >= shader->constlen) |
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124 | break; |
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125 | |||
126 | if (constbuf->dirty_mask & (1 << index)) { |
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127 | fd3_emit_constant(ring, sb, base, |
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128 | cb->buffer_offset, size, |
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129 | cb->user_buffer, cb->buffer); |
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130 | constbuf->dirty_mask &= ~(1 << index); |
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131 | } |
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132 | |||
133 | base += size; |
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134 | enabled_mask &= ~(1 << index); |
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135 | } |
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136 | |||
137 | /* emit shader immediates: */ |
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138 | if (shader) { |
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139 | for (i = 0; i < shader->immediates_count; i++) { |
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140 | fd3_emit_constant(ring, sb, |
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141 | 4 * (shader->first_immediate + i), |
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142 | 0, 4, shader->immediates[i].val, NULL); |
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143 | } |
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144 | } |
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145 | } |
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146 | |||
147 | #define VERT_TEX_OFF 0 |
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148 | #define FRAG_TEX_OFF 16 |
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149 | #define BASETABLE_SZ 14 |
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150 | |||
151 | static void |
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152 | emit_textures(struct fd_ringbuffer *ring, |
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153 | enum adreno_state_block sb, |
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154 | struct fd_texture_stateobj *tex) |
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155 | { |
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156 | static const unsigned tex_off[] = { |
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157 | [SB_VERT_TEX] = VERT_TEX_OFF, |
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158 | [SB_FRAG_TEX] = FRAG_TEX_OFF, |
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159 | }; |
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160 | static const enum adreno_state_block mipaddr[] = { |
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161 | [SB_VERT_TEX] = SB_VERT_MIPADDR, |
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162 | [SB_FRAG_TEX] = SB_FRAG_MIPADDR, |
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163 | }; |
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164 | unsigned i, j; |
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165 | |||
166 | assert(tex->num_samplers == tex->num_textures); // TODO check.. |
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167 | |||
168 | if (!tex->num_samplers) |
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169 | return; |
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170 | |||
171 | /* output sampler state: */ |
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172 | OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers)); |
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173 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) | |
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174 | CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) | |
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175 | CP_LOAD_STATE_0_STATE_BLOCK(sb) | |
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176 | CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers)); |
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177 | OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) | |
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178 | CP_LOAD_STATE_1_EXT_SRC_ADDR(0)); |
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179 | for (i = 0; i < tex->num_samplers; i++) { |
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180 | struct fd3_sampler_stateobj *sampler = |
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181 | fd3_sampler_stateobj(tex->samplers[i]); |
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182 | OUT_RING(ring, sampler->texsamp0); |
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183 | OUT_RING(ring, sampler->texsamp1); |
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184 | } |
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185 | |||
186 | /* emit texture state: */ |
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187 | OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures)); |
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188 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) | |
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189 | CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) | |
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190 | CP_LOAD_STATE_0_STATE_BLOCK(sb) | |
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191 | CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures)); |
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192 | OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) | |
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193 | CP_LOAD_STATE_1_EXT_SRC_ADDR(0)); |
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194 | for (i = 0; i < tex->num_textures; i++) { |
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195 | struct fd3_pipe_sampler_view *view = |
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196 | fd3_pipe_sampler_view(tex->textures[i]); |
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197 | OUT_RING(ring, view->texconst0); |
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198 | OUT_RING(ring, view->texconst1); |
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199 | OUT_RING(ring, view->texconst2 | |
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200 | A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i)); |
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201 | OUT_RING(ring, view->texconst3); |
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202 | } |
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203 | |||
204 | /* emit mipaddrs: */ |
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205 | OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures)); |
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206 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) | |
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207 | CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) | |
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208 | CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) | |
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209 | CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures)); |
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210 | OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) | |
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211 | CP_LOAD_STATE_1_EXT_SRC_ADDR(0)); |
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212 | for (i = 0; i < tex->num_textures; i++) { |
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213 | struct fd3_pipe_sampler_view *view = |
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214 | fd3_pipe_sampler_view(tex->textures[i]); |
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4401 | Serge | 215 | OUT_RELOC(ring, view->tex_resource->bo, 0, 0, 0); |
4358 | Serge | 216 | /* I think each entry is a ptr to mipmap level.. for now, just |
217 | * pad w/ null's until I get around to actually implementing |
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218 | * mipmap support.. |
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219 | */ |
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220 | for (j = 1; j < BASETABLE_SZ; j++) { |
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221 | OUT_RING(ring, 0x00000000); |
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222 | } |
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223 | } |
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224 | } |
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225 | |||
226 | static void |
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227 | emit_cache_flush(struct fd_ringbuffer *ring) |
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228 | { |
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229 | OUT_PKT3(ring, CP_EVENT_WRITE, 1); |
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230 | OUT_RING(ring, CACHE_FLUSH); |
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231 | |||
232 | OUT_PKT3(ring, CP_DRAW_INDX, 3); |
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233 | OUT_RING(ring, 0x00000000); |
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234 | OUT_RING(ring, DRAW(DI_PT_POINTLIST, DI_SRC_SEL_AUTO_INDEX, |
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235 | INDEX_SIZE_IGN, IGNORE_VISIBILITY)); |
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236 | OUT_RING(ring, 0); /* NumIndices */ |
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237 | |||
238 | OUT_PKT3(ring, CP_NOP, 4); |
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239 | OUT_RING(ring, 0x00000000); |
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240 | OUT_RING(ring, 0x00000000); |
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241 | OUT_RING(ring, 0x00000000); |
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242 | OUT_RING(ring, 0x00000000); |
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243 | |||
244 | OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); |
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245 | OUT_RING(ring, 0x00000000); |
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246 | } |
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247 | |||
248 | /* emit texture state for mem->gmem restore operation.. eventually it would |
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249 | * be good to get rid of this and use normal CSO/etc state for more of these |
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250 | * special cases, but for now the compiler is not sufficient.. |
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251 | */ |
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252 | void |
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253 | fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf) |
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254 | { |
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255 | struct fd_resource *rsc = fd_resource(psurf->texture); |
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256 | |||
257 | /* output sampler state: */ |
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258 | OUT_PKT3(ring, CP_LOAD_STATE, 4); |
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259 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) | |
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260 | CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) | |
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261 | CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) | |
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262 | CP_LOAD_STATE_0_NUM_UNIT(1)); |
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263 | OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) | |
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264 | CP_LOAD_STATE_1_EXT_SRC_ADDR(0)); |
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265 | OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) | |
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266 | A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) | |
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267 | A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) | |
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268 | A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) | |
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269 | A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT)); |
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270 | OUT_RING(ring, 0x00000000); |
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271 | |||
272 | /* emit texture state: */ |
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273 | OUT_PKT3(ring, CP_LOAD_STATE, 6); |
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274 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) | |
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275 | CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) | |
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276 | CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) | |
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277 | CP_LOAD_STATE_0_NUM_UNIT(1)); |
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278 | OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) | |
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279 | CP_LOAD_STATE_1_EXT_SRC_ADDR(0)); |
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280 | OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) | |
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281 | 0x40000000 | // XXX |
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4401 | Serge | 282 | fd3_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN, |
283 | PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA)); |
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284 | OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) | |
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4358 | Serge | 285 | A3XX_TEX_CONST_1_WIDTH(psurf->width) | |
286 | A3XX_TEX_CONST_1_HEIGHT(psurf->height)); |
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287 | OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->pitch * rsc->cpp) | |
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288 | A3XX_TEX_CONST_2_INDX(0)); |
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289 | OUT_RING(ring, 0x00000000); |
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290 | |||
291 | /* emit mipaddrs: */ |
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292 | OUT_PKT3(ring, CP_LOAD_STATE, 3); |
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293 | OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) | |
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294 | CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) | |
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295 | CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) | |
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296 | CP_LOAD_STATE_0_NUM_UNIT(1)); |
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297 | OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) | |
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298 | CP_LOAD_STATE_1_EXT_SRC_ADDR(0)); |
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4401 | Serge | 299 | OUT_RELOC(ring, rsc->bo, 0, 0, 0); |
4358 | Serge | 300 | } |
301 | |||
302 | void |
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303 | fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, |
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304 | struct fd_program_stateobj *prog, |
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305 | struct fd3_vertex_buf *vbufs, uint32_t n) |
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306 | { |
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307 | struct fd3_shader_stateobj *vp = prog->vp; |
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308 | uint32_t i; |
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309 | |||
310 | n = MIN2(n, vp->inputs_count); |
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311 | |||
312 | for (i = 0; i < n; i++) { |
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313 | struct pipe_resource *prsc = vbufs[i].prsc; |
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314 | struct fd_resource *rsc = fd_resource(prsc); |
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315 | enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(vbufs[i].format); |
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316 | bool switchnext = (i != (n - 1)); |
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317 | uint32_t fs = util_format_get_blocksize(vbufs[i].format); |
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318 | |||
319 | OUT_PKT0(ring, REG_A3XX_VFD_FETCH(i), 2); |
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320 | OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) | |
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321 | A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) | |
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322 | COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) | |
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323 | A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) | |
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324 | A3XX_VFD_FETCH_INSTR_0_STEPRATE(1)); |
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4401 | Serge | 325 | OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0); |
4358 | Serge | 326 | |
327 | OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1); |
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328 | OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL | |
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329 | A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) | |
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330 | A3XX_VFD_DECODE_INSTR_FORMAT(fmt) | |
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331 | A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) | |
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332 | A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) | |
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333 | A3XX_VFD_DECODE_INSTR_LASTCOMPVALID | |
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334 | COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT)); |
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335 | } |
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336 | } |
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337 | |||
338 | void |
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339 | fd3_emit_state(struct fd_context *ctx, uint32_t dirty) |
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340 | { |
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341 | struct fd_ringbuffer *ring = ctx->ring; |
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342 | |||
343 | if (dirty & FD_DIRTY_SAMPLE_MASK) { |
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344 | OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); |
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345 | OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE | |
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346 | A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) | |
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347 | A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask)); |
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348 | } |
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349 | |||
350 | if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) { |
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351 | struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa); |
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352 | struct pipe_stencil_ref *sr = &ctx->stencil_ref; |
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353 | |||
354 | fd3_emit_rbrc_draw_state(ring, zsa->rb_render_control); |
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355 | |||
356 | OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1); |
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357 | OUT_RING(ring, zsa->rb_depth_control); |
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358 | |||
359 | OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1); |
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360 | OUT_RING(ring, zsa->rb_stencil_control); |
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361 | |||
362 | OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2); |
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363 | OUT_RING(ring, zsa->rb_stencilrefmask | |
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364 | A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); |
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365 | OUT_RING(ring, zsa->rb_stencilrefmask_bf | |
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366 | A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1])); |
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367 | } |
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368 | |||
369 | if (dirty & FD_DIRTY_RASTERIZER) { |
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370 | struct fd3_rasterizer_stateobj *rasterizer = |
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371 | fd3_rasterizer_stateobj(ctx->rasterizer); |
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372 | |||
373 | OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1); |
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374 | OUT_RING(ring, rasterizer->gras_su_mode_control); |
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375 | |||
376 | OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2); |
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377 | OUT_RING(ring, rasterizer->gras_su_point_minmax); |
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378 | OUT_RING(ring, rasterizer->gras_su_point_size); |
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379 | |||
380 | OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2); |
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381 | OUT_RING(ring, rasterizer->gras_su_poly_offset_scale); |
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382 | OUT_RING(ring, rasterizer->gras_su_poly_offset_offset); |
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383 | |||
384 | OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1); |
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385 | OUT_RING(ring, rasterizer->gras_cl_clip_cntl); |
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386 | } |
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387 | |||
388 | if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) { |
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389 | struct fd3_rasterizer_stateobj *rasterizer = |
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390 | fd3_rasterizer_stateobj(ctx->rasterizer); |
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391 | struct fd3_shader_stateobj *fp = ctx->prog.fp; |
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392 | uint32_t stride_in_vpc; |
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393 | |||
394 | stride_in_vpc = align(fp->total_in, 4) / 4; |
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395 | if (stride_in_vpc > 0) |
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396 | stride_in_vpc = MAX2(stride_in_vpc, 2); |
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397 | |||
398 | OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1); |
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399 | OUT_RING(ring, rasterizer->pc_prim_vtx_cntl | |
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400 | A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc)); |
||
401 | } |
||
402 | |||
403 | if (dirty & FD_DIRTY_SCISSOR) { |
||
404 | struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); |
||
405 | |||
406 | OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2); |
||
407 | OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) | |
||
408 | A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny)); |
||
409 | OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) | |
||
410 | A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1)); |
||
411 | |||
412 | ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx); |
||
413 | ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny); |
||
414 | ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx); |
||
415 | ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy); |
||
416 | } |
||
417 | |||
418 | if (dirty & FD_DIRTY_VIEWPORT) { |
||
419 | OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6); |
||
420 | OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5)); |
||
421 | OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0])); |
||
422 | OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5)); |
||
423 | OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1])); |
||
424 | OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2])); |
||
425 | OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2])); |
||
426 | } |
||
427 | |||
428 | if (dirty & FD_DIRTY_PROG) |
||
429 | fd3_program_emit(ring, &ctx->prog); |
||
430 | |||
431 | if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) { |
||
432 | struct fd_program_stateobj *prog = &ctx->prog; |
||
433 | |||
434 | emit_constants(ring, SB_VERT_SHADER, |
||
435 | &ctx->constbuf[PIPE_SHADER_VERTEX], |
||
436 | (prog->dirty & FD_SHADER_DIRTY_VP) ? prog->vp : NULL); |
||
437 | emit_constants(ring, SB_FRAG_SHADER, |
||
438 | &ctx->constbuf[PIPE_SHADER_FRAGMENT], |
||
439 | (prog->dirty & FD_SHADER_DIRTY_FP) ? prog->fp : NULL); |
||
440 | } |
||
441 | |||
442 | if (dirty & FD_DIRTY_BLEND) { |
||
443 | struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend); |
||
444 | uint32_t i; |
||
445 | |||
446 | for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) { |
||
447 | OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1); |
||
448 | OUT_RING(ring, blend->rb_mrt[i].control); |
||
449 | |||
450 | OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1); |
||
451 | OUT_RING(ring, blend->rb_mrt[i].blend_control); |
||
452 | } |
||
453 | } |
||
454 | |||
455 | if (dirty & FD_DIRTY_VERTTEX) |
||
456 | emit_textures(ring, SB_VERT_TEX, &ctx->verttex); |
||
457 | |||
458 | if (dirty & FD_DIRTY_FRAGTEX) |
||
459 | emit_textures(ring, SB_FRAG_TEX, &ctx->fragtex); |
||
460 | |||
461 | ctx->dirty &= ~dirty; |
||
462 | } |
||
463 | |||
464 | /* emit setup at begin of new cmdstream buffer (don't rely on previous |
||
465 | * state, there could have been a context switch between ioctls): |
||
466 | */ |
||
467 | void |
||
468 | fd3_emit_restore(struct fd_context *ctx) |
||
469 | { |
||
470 | struct fd3_context *fd3_ctx = fd3_context(ctx); |
||
471 | struct fd_ringbuffer *ring = ctx->ring; |
||
472 | int i; |
||
473 | |||
474 | OUT_PKT3(ring, CP_REG_RMW, 3); |
||
475 | OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL); |
||
476 | OUT_RING(ring, 0xfffcffff); |
||
477 | OUT_RING(ring, 0x00000000); |
||
478 | |||
479 | OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); |
||
480 | OUT_RING(ring, 0x00007fff); |
||
481 | |||
482 | OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG, 3); |
||
483 | OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */ |
||
4401 | Serge | 484 | OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */ |
4358 | Serge | 485 | OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */ |
486 | |||
487 | OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG, 3); |
||
488 | OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */ |
||
4401 | Serge | 489 | OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */ |
4358 | Serge | 490 | OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */ |
491 | |||
492 | OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1); |
||
493 | OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */ |
||
494 | |||
495 | OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); |
||
496 | OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) | |
||
497 | A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) | |
||
498 | A3XX_GRAS_SC_CONTROL_RASTER_MODE(0)); |
||
499 | |||
500 | OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2); |
||
501 | OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE | |
||
502 | A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) | |
||
503 | A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff)); |
||
504 | OUT_RING(ring, 0x00000000); /* UNKNOWN_20C3 */ |
||
505 | |||
506 | OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1); |
||
507 | OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) | |
||
508 | A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0)); |
||
509 | |||
510 | OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C81, 1); |
||
511 | OUT_RING(ring, 0x00000001); /* UNKNOWN_0C81 */ |
||
512 | |||
513 | OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1); |
||
514 | OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) | |
||
515 | A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) | |
||
516 | A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF)); |
||
517 | |||
518 | OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1); |
||
519 | OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) | |
||
520 | A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) | |
||
521 | A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF)); |
||
522 | |||
523 | OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2); |
||
524 | OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */ |
||
525 | OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */ |
||
526 | |||
527 | OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1); |
||
528 | OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */ |
||
529 | |||
530 | OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1); |
||
531 | OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */ |
||
532 | |||
533 | OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1); |
||
534 | OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */ |
||
535 | |||
536 | OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1); |
||
537 | OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */ |
||
538 | |||
4401 | Serge | 539 | OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1); |
540 | OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */ |
||
4358 | Serge | 541 | |
542 | OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2); |
||
543 | OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) | |
||
544 | A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0)); |
||
545 | OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) | |
||
546 | A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0)); |
||
547 | |||
548 | OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 1); |
||
549 | OUT_RING(ring, 0x00000001); /* UCHE_CACHE_MODE_CONTROL_REG */ |
||
550 | |||
551 | OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1); |
||
4401 | Serge | 552 | OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */ |
4358 | Serge | 553 | |
554 | OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1); |
||
555 | OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */ |
||
556 | |||
557 | OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2); |
||
558 | OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */ |
||
559 | OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */ |
||
560 | |||
561 | OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1); |
||
562 | OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */ |
||
563 | |||
564 | OUT_PKT0(ring, REG_A3XX_PA_SC_WINDOW_OFFSET, 1); |
||
565 | OUT_RING(ring, A3XX_PA_SC_WINDOW_OFFSET_X(0) | |
||
566 | A3XX_PA_SC_WINDOW_OFFSET_Y(0)); |
||
567 | |||
568 | OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4); |
||
569 | OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */ |
||
570 | OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */ |
||
571 | OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */ |
||
572 | OUT_RING(ring, 0x3c0000ff); /* RB_BLEND_ALPHA */ |
||
573 | |||
574 | for (i = 0; i < 6; i++) { |
||
575 | OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4); |
||
576 | OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */ |
||
577 | OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */ |
||
578 | OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */ |
||
579 | OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */ |
||
580 | } |
||
581 | |||
582 | emit_cache_flush(ring); |
||
583 | }>>>>>>>>><>><>><>> |