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5563 serge 1
/*
2
 * Copyright 2008 Corbin Simpson 
3
 * Copyright 2009 Marek Olšák 
4
 *
5
 * Permission is hereby granted, free of charge, to any person obtaining a
6
 * copy of this software and associated documentation files (the "Software"),
7
 * to deal in the Software without restriction, including without limitation
8
 * on the rights to use, copy, modify, merge, publish, distribute, sub
9
 * license, and/or sell copies of the Software, and to permit persons to whom
10
 * the Software is furnished to do so, subject to the following conditions:
11
 *
12
 * The above copyright notice and this permission notice (including the next
13
 * paragraph) shall be included in all copies or substantial portions of the
14
 * Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22
 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
 
24
/* r300_emit: Functions for emitting state. */
25
 
26
#include "util/u_format.h"
27
#include "util/u_math.h"
28
#include "util/u_mm.h"
29
 
30
#include "r300_context.h"
31
#include "r300_cb.h"
32
#include "r300_cs.h"
33
#include "r300_emit.h"
34
#include "r300_fs.h"
35
#include "r300_screen.h"
36
#include "r300_screen_buffer.h"
37
#include "r300_vs.h"
38
 
39
void r300_emit_blend_state(struct r300_context* r300,
40
                           unsigned size, void* state)
41
{
42
    struct r300_blend_state* blend = (struct r300_blend_state*)state;
43
    struct pipe_framebuffer_state* fb =
44
        (struct pipe_framebuffer_state*)r300->fb_state.state;
45
    CS_LOCALS(r300);
46
 
47
    if (fb->nr_cbufs) {
48
        if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) {
49
            WRITE_CS_TABLE(blend->cb_noclamp, size);
50
        } else if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16X16_FLOAT) {
51
            WRITE_CS_TABLE(blend->cb_noclamp_noalpha, size);
52
        } else {
53
            unsigned swz = r300_surface(fb->cbufs[0])->colormask_swizzle;
54
            WRITE_CS_TABLE(blend->cb_clamp[swz], size);
55
        }
56
    } else {
57
        WRITE_CS_TABLE(blend->cb_no_readwrite, size);
58
    }
59
}
60
 
61
void r300_emit_blend_color_state(struct r300_context* r300,
62
                                 unsigned size, void* state)
63
{
64
    struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65
    CS_LOCALS(r300);
66
 
67
    WRITE_CS_TABLE(bc->cb, size);
68
}
69
 
70
void r300_emit_clip_state(struct r300_context* r300,
71
                          unsigned size, void* state)
72
{
73
    struct r300_clip_state* clip = (struct r300_clip_state*)state;
74
    CS_LOCALS(r300);
75
 
76
    WRITE_CS_TABLE(clip->cb, size);
77
}
78
 
79
void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
80
{
81
    struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
82
    struct pipe_framebuffer_state* fb =
83
        (struct pipe_framebuffer_state*)r300->fb_state.state;
84
    boolean is_r500 = r300->screen->caps.is_r500;
85
    CS_LOCALS(r300);
86
    uint32_t alpha_func = dsa->alpha_function;
87
 
88
    /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
89
     * 16-bit (FG_ALPHA_VALUE). */
90
    if (is_r500 && (alpha_func & R300_FG_ALPHA_FUNC_ENABLE)) {
91
        if (fb->nr_cbufs &&
92
            (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
93
             fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16X16_FLOAT)) {
94
            alpha_func |= R500_FG_ALPHA_FUNC_FP16_ENABLE;
95
        } else {
96
            alpha_func |= R500_FG_ALPHA_FUNC_8BIT;
97
        }
98
    }
99
 
100
    /* Setup alpha-to-coverage. */
101
    if (r300->alpha_to_coverage && r300->msaa_enable) {
102
        /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
103
        alpha_func |= R300_FG_ALPHA_FUNC_MASK_ENABLE |
104
                      R300_FG_ALPHA_FUNC_CFG_3_OF_6;
105
    }
106
 
107
    BEGIN_CS(size);
108
    OUT_CS_REG(R300_FG_ALPHA_FUNC, alpha_func);
109
    OUT_CS_TABLE(fb->zsbuf ? &dsa->cb_begin : dsa->cb_zb_no_readwrite, size-2);
110
    END_CS;
111
}
112
 
113
static void get_rc_constant_state(
114
    float vec[4],
115
    struct r300_context * r300,
116
    struct rc_constant * constant)
117
{
118
    struct r300_textures_state* texstate = r300->textures_state.state;
119
    struct r300_resource *tex;
120
 
121
    assert(constant->Type == RC_CONSTANT_STATE);
122
 
123
    /* vec should either be (0, 0, 0, 1), which should be a relatively safe
124
     * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
125
     * state factors. */
126
 
127
    switch (constant->u.State[0]) {
128
        /* Factor for converting rectangle coords to
129
         * normalized coords. Should only show up on non-r500. */
130
        case RC_STATE_R300_TEXRECT_FACTOR:
131
            tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
132
            vec[0] = 1.0 / tex->tex.width0;
133
            vec[1] = 1.0 / tex->tex.height0;
134
            vec[2] = 0;
135
            vec[3] = 1;
136
            break;
137
 
138
        case RC_STATE_R300_TEXSCALE_FACTOR:
139
            tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
140
            /* Add a small number to the texture size to work around rounding errors in hw. */
141
            vec[0] = tex->b.b.width0  / (tex->tex.width0  + 0.001f);
142
            vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f);
143
            vec[2] = tex->b.b.depth0  / (tex->tex.depth0  + 0.001f);
144
            vec[3] = 1;
145
            break;
146
 
147
        case RC_STATE_R300_VIEWPORT_SCALE:
148
            vec[0] = r300->viewport.scale[0];
149
            vec[1] = r300->viewport.scale[1];
150
            vec[2] = r300->viewport.scale[2];
151
            vec[3] = 1;
152
            break;
153
 
154
        case RC_STATE_R300_VIEWPORT_OFFSET:
155
            vec[0] = r300->viewport.translate[0];
156
            vec[1] = r300->viewport.translate[1];
157
            vec[2] = r300->viewport.translate[2];
158
            vec[3] = 1;
159
            break;
160
 
161
        default:
162
            fprintf(stderr, "r300: Implementation error: "
163
                "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
164
            vec[0] = 0;
165
            vec[1] = 0;
166
            vec[2] = 0;
167
            vec[3] = 1;
168
    }
169
}
170
 
171
/* Convert a normal single-precision float into the 7.16 format
172
 * used by the R300 fragment shader.
173
 */
174
uint32_t pack_float24(float f)
175
{
176
    union {
177
        float fl;
178
        uint32_t u;
179
    } u;
180
    float mantissa;
181
    int exponent;
182
    uint32_t float24 = 0;
183
 
184
    if (f == 0.0)
185
        return 0;
186
 
187
    u.fl = f;
188
 
189
    mantissa = frexpf(f, &exponent);
190
 
191
    /* Handle -ve */
192
    if (mantissa < 0) {
193
        float24 |= (1 << 23);
194
        mantissa = mantissa * -1.0;
195
    }
196
    /* Handle exponent, bias of 63 */
197
    exponent += 62;
198
    float24 |= (exponent << 16);
199
    /* Kill 7 LSB of mantissa */
200
    float24 |= (u.u & 0x7FFFFF) >> 7;
201
 
202
    return float24;
203
}
204
 
205
void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
206
{
207
    struct r300_fragment_shader *fs = r300_fs(r300);
208
    CS_LOCALS(r300);
209
 
210
    WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
211
}
212
 
213
void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
214
{
215
    struct r300_fragment_shader *fs = r300_fs(r300);
216
    struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
217
    unsigned count = fs->shader->externals_count;
218
    unsigned i, j;
219
    CS_LOCALS(r300);
220
 
221
    if (count == 0)
222
        return;
223
 
224
    BEGIN_CS(size);
225
    OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
226
    if (buf->remap_table){
227
        for (i = 0; i < count; i++) {
228
            float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
229
            for (j = 0; j < 4; j++)
230
                OUT_CS(pack_float24(data[j]));
231
        }
232
    } else {
233
        for (i = 0; i < count; i++)
234
            for (j = 0; j < 4; j++)
235
                OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
236
    }
237
 
238
    END_CS;
239
}
240
 
241
void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
242
{
243
    struct r300_fragment_shader *fs = r300_fs(r300);
244
    struct rc_constant_list *constants = &fs->shader->code.constants;
245
    unsigned i;
246
    unsigned count = fs->shader->rc_state_count;
247
    unsigned first = fs->shader->externals_count;
248
    unsigned end = constants->Count;
249
    unsigned j;
250
    CS_LOCALS(r300);
251
 
252
    if (count == 0)
253
        return;
254
 
255
    BEGIN_CS(size);
256
    for(i = first; i < end; ++i) {
257
        if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
258
            float data[4];
259
 
260
            get_rc_constant_state(data, r300, &constants->Constants[i]);
261
 
262
            OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
263
            for (j = 0; j < 4; j++)
264
                OUT_CS(pack_float24(data[j]));
265
        }
266
    }
267
    END_CS;
268
}
269
 
270
void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
271
{
272
    struct r300_fragment_shader *fs = r300_fs(r300);
273
    CS_LOCALS(r300);
274
 
275
    WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
276
}
277
 
278
void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
279
{
280
    struct r300_fragment_shader *fs = r300_fs(r300);
281
    struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
282
    unsigned count = fs->shader->externals_count;
283
    CS_LOCALS(r300);
284
 
285
    if (count == 0)
286
        return;
287
 
288
    BEGIN_CS(size);
289
    OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
290
    OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
291
    if (buf->remap_table){
292
        for (unsigned i = 0; i < count; i++) {
293
            uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
294
            OUT_CS_TABLE(data, 4);
295
        }
296
    } else {
297
        OUT_CS_TABLE(buf->ptr, count * 4);
298
    }
299
    END_CS;
300
}
301
 
302
void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
303
{
304
    struct r300_fragment_shader *fs = r300_fs(r300);
305
    struct rc_constant_list *constants = &fs->shader->code.constants;
306
    unsigned i;
307
    unsigned count = fs->shader->rc_state_count;
308
    unsigned first = fs->shader->externals_count;
309
    unsigned end = constants->Count;
310
    CS_LOCALS(r300);
311
 
312
    if (count == 0)
313
        return;
314
 
315
    BEGIN_CS(size);
316
    for(i = first; i < end; ++i) {
317
        if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
318
            float data[4];
319
 
320
            get_rc_constant_state(data, r300, &constants->Constants[i]);
321
 
322
            OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
323
                       R500_GA_US_VECTOR_INDEX_TYPE_CONST |
324
                       (i & R500_GA_US_VECTOR_INDEX_MASK));
325
            OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
326
            OUT_CS_TABLE(data, 4);
327
        }
328
    }
329
    END_CS;
330
}
331
 
332
void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
333
{
334
    struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
335
    struct pipe_framebuffer_state* fb =
336
            (struct pipe_framebuffer_state*)r300->fb_state.state;
337
    uint32_t height = fb->height;
338
    uint32_t width = fb->width;
339
    CS_LOCALS(r300);
340
 
341
    if (r300->cbzb_clear) {
342
        struct r300_surface *surf = r300_surface(fb->cbufs[0]);
343
 
344
        height = surf->cbzb_height;
345
        width = surf->cbzb_width;
346
    }
347
 
348
    DBG(r300, DBG_SCISSOR,
349
	"r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
350
	width, height, r300->cbzb_clear ? "YES" : "NO");
351
 
352
    BEGIN_CS(size);
353
 
354
    /* Set up scissors.
355
     * By writing to the SC registers, SC & US assert idle. */
356
    OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
357
    if (r300->screen->caps.is_r500) {
358
        OUT_CS(0);
359
        OUT_CS(((width  - 1) << R300_SCISSORS_X_SHIFT) |
360
               ((height - 1) << R300_SCISSORS_Y_SHIFT));
361
    } else {
362
        OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
363
               (1440 << R300_SCISSORS_Y_SHIFT));
364
        OUT_CS(((width  + 1440-1) << R300_SCISSORS_X_SHIFT) |
365
               ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
366
    }
367
 
368
    /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
369
    OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
370
    END_CS;
371
}
372
 
373
void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
374
{
375
    struct r300_aa_state *aa = (struct r300_aa_state*)state;
376
    CS_LOCALS(r300);
377
 
378
    BEGIN_CS(size);
379
    OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
380
 
381
    if (aa->dest) {
382
        OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 3);
383
        OUT_CS(aa->dest->offset);
384
        OUT_CS(aa->dest->pitch & R300_RB3D_AARESOLVE_PITCH_MASK);
385
        OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE |
386
               R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE);
387
        OUT_CS_RELOC(aa->dest);
388
    } else {
389
        OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0);
390
    }
391
 
392
    END_CS;
393
}
394
 
395
void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
396
{
397
    struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
398
    struct r300_surface* surf;
399
    unsigned i;
400
    uint32_t rb3d_cctl = 0;
401
 
402
    CS_LOCALS(r300);
403
 
404
    BEGIN_CS(size);
405
 
406
    if (r300->screen->caps.is_r500) {
407
        rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
408
    }
409
    /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */
410
    if (fb->nr_cbufs && r300->fb_multiwrite) {
411
        rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
412
    }
413
    if (r300->cmask_in_use) {
414
        rb3d_cctl |= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE |
415
                     R300_RB3D_CCTL_CMASK_ENABLE;
416
    }
417
 
418
    OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
419
 
420
    /* Set up colorbuffers. */
421
    for (i = 0; i < fb->nr_cbufs; i++) {
422
        surf = r300_surface(fb->cbufs[i]);
423
 
424
        OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
425
        OUT_CS_RELOC(surf);
426
 
427
        OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
428
        OUT_CS_RELOC(surf);
429
 
430
        if (r300->cmask_in_use && i == 0) {
431
            OUT_CS_REG(R300_RB3D_CMASK_OFFSET0, 0);
432
            OUT_CS_REG(R300_RB3D_CMASK_PITCH0, surf->pitch_cmask);
433
            OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE, r300->color_clear_value);
434
            if (r300->screen->caps.is_r500 && r300->screen->info.drm_minor >= 29) {
435
                OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
436
                OUT_CS(r300->color_clear_value_ar);
437
                OUT_CS(r300->color_clear_value_gb);
438
            }
439
        }
440
    }
441
 
442
    /* Set up the ZB part of the CBZB clear. */
443
    if (r300->cbzb_clear) {
444
        surf = r300_surface(fb->cbufs[0]);
445
 
446
        OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
447
 
448
        OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
449
        OUT_CS_RELOC(surf);
450
 
451
        OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
452
        OUT_CS_RELOC(surf);
453
 
454
        DBG(r300, DBG_CBZB,
455
            "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
456
            surf->cbzb_pitch);
457
    }
458
    /* Set up a zbuffer. */
459
    else if (fb->zsbuf) {
460
        surf = r300_surface(fb->zsbuf);
461
 
462
        OUT_CS_REG(R300_ZB_FORMAT, surf->format);
463
 
464
        OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
465
        OUT_CS_RELOC(surf);
466
 
467
        OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
468
        OUT_CS_RELOC(surf);
469
 
470
        if (r300->hyperz_enabled) {
471
            /* HiZ RAM. */
472
            OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
473
            OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
474
            /* Z Mask RAM. (compressed zbuffer) */
475
            OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
476
            OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
477
        }
478
    }
479
 
480
    END_CS;
481
}
482
 
483
void r300_emit_hyperz_state(struct r300_context *r300,
484
                            unsigned size, void *state)
485
{
486
    struct r300_hyperz_state *z = state;
487
    CS_LOCALS(r300);
488
 
489
    if (z->flush)
490
        WRITE_CS_TABLE(&z->cb_flush_begin, size);
491
    else
492
        WRITE_CS_TABLE(&z->cb_begin, size - 2);
493
}
494
 
495
void r300_emit_hyperz_end(struct r300_context *r300)
496
{
497
    struct r300_hyperz_state z =
498
            *(struct r300_hyperz_state*)r300->hyperz_state.state;
499
 
500
    z.flush = 1;
501
    z.zb_bw_cntl = 0;
502
    z.zb_depthclearvalue = 0;
503
    z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
504
    z.gb_z_peq_config = 0;
505
 
506
    r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
507
}
508
 
509
#define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x)  \
510
    (((x0) & 0xf) | (((y0) & 0xf) << 4) |		   \
511
    (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) |	   \
512
    (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) |	   \
513
    (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
514
 
515
static unsigned r300_get_mspos(int index, unsigned *p)
516
{
517
    unsigned reg, i, distx, disty, dist;
518
 
519
    if (index == 0) {
520
        /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
521
         * followed by a (Y,X) pair containing the minimum distance from the pixel
522
         * edge:
523
         *     X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
524
         *
525
         * There is a quirk when setting D0_X. The value represents the distance
526
         * from the left edge of the pixel quad to the first sample in subpixels.
527
         * All values less than eight should use the actual value, but „7‟ should
528
         * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
529
         */
530
        distx = 11;
531
        for (i = 0; i < 12; i += 2) {
532
            if (p[i] < distx)
533
                distx = p[i];
534
        }
535
 
536
        disty = 11;
537
        for (i = 1; i < 12; i += 2) {
538
            if (p[i] < disty)
539
                disty = p[i];
540
        }
541
 
542
        if (distx == 8)
543
            distx = 7;
544
 
545
        reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx);
546
    } else {
547
        /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
548
         * followed by the minimum distance from the pixel edge (not sure if X or Y):
549
         *     X3, Y3, X4, Y4, X5, Y5, D1
550
         */
551
        dist = 11;
552
        for (i = 0; i < 12; i++) {
553
            if (p[i] < dist)
554
                dist = p[i];
555
        }
556
 
557
        reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0);
558
    }
559
    return reg;
560
}
561
 
562
void r300_emit_fb_state_pipelined(struct r300_context *r300,
563
                                  unsigned size, void *state)
564
{
565
    /* The sample coordinates are in the range [0,11], because
566
     * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
567
     *
568
     * Some sample coordinates reach to neighboring pixels and should not be used.
569
     * (e.g. Y=11)
570
     *
571
     * The unused samples must be set to the positions of other valid samples. */
572
    static unsigned sample_locs_1x[12] = {
573
        6,6,  6,6,  6,6,  6,6,  6,6,  6,6
574
    };
575
    static unsigned sample_locs_2x[12] = {
576
        3,9,  9,3,  9,3,  9,3,  9,3,  9,3
577
    };
578
    static unsigned sample_locs_4x[12] = {
579
        4,4,  8,8,  2,10,  10,2,  10,2,  10,2
580
    };
581
    static unsigned sample_locs_6x[12] = {
582
        3,1,  7,3,  11,5,  1,7,  5,9,  9,10
583
    };
584
 
585
    struct pipe_framebuffer_state* fb =
586
            (struct pipe_framebuffer_state*)r300->fb_state.state;
587
    unsigned i, num_cbufs = fb->nr_cbufs;
588
    unsigned mspos0, mspos1;
589
    CS_LOCALS(r300);
590
 
591
    /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
592
     * marked as UNUSED in the US block. */
593
    if (r300->fb_multiwrite) {
594
        num_cbufs = MIN2(num_cbufs, 1);
595
    }
596
 
597
    BEGIN_CS(size);
598
 
599
    /* Colorbuffer format in the US block.
600
     * (must be written after unpipelined regs) */
601
    OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
602
    for (i = 0; i < num_cbufs; i++) {
603
        OUT_CS(r300_surface(fb->cbufs[i])->format);
604
    }
605
    for (; i < 1; i++) {
606
        OUT_CS(R300_US_OUT_FMT_C4_8 |
607
               R300_C0_SEL_B | R300_C1_SEL_G |
608
               R300_C2_SEL_R | R300_C3_SEL_A);
609
    }
610
    for (; i < 4; i++) {
611
        OUT_CS(R300_US_OUT_FMT_UNUSED);
612
    }
613
 
614
    /* Set sample positions. It depends on the framebuffer sample count.
615
     * These are pipelined regs and as such cannot be moved to the AA state.
616
     */
617
    switch (r300->num_samples) {
618
    default:
619
        mspos0 = r300_get_mspos(0, sample_locs_1x);
620
        mspos1 = r300_get_mspos(1, sample_locs_1x);
621
        break;
622
    case 2:
623
        mspos0 = r300_get_mspos(0, sample_locs_2x);
624
        mspos1 = r300_get_mspos(1, sample_locs_2x);
625
        break;
626
    case 4:
627
        mspos0 = r300_get_mspos(0, sample_locs_4x);
628
        mspos1 = r300_get_mspos(1, sample_locs_4x);
629
        break;
630
    case 6:
631
        mspos0 = r300_get_mspos(0, sample_locs_6x);
632
        mspos1 = r300_get_mspos(1, sample_locs_6x);
633
        break;
634
    }
635
 
636
    OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
637
    OUT_CS(mspos0);
638
    OUT_CS(mspos1);
639
    END_CS;
640
}
641
 
642
void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
643
{
644
    struct r300_query *query = r300->query_current;
645
    CS_LOCALS(r300);
646
 
647
    if (!query)
648
	return;
649
 
650
    BEGIN_CS(size);
651
    if (r300->screen->caps.family == CHIP_RV530) {
652
        OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
653
    } else {
654
        OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
655
    }
656
    OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
657
    END_CS;
658
    query->begin_emitted = TRUE;
659
}
660
 
661
static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
662
                                           struct r300_query *query)
663
{
664
    struct r300_capabilities* caps = &r300->screen->caps;
665
    uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes;
666
    CS_LOCALS(r300);
667
 
668
    assert(gb_pipes);
669
 
670
    BEGIN_CS(6 * gb_pipes + 2);
671
    /* I'm not so sure I like this switch, but it's hard to be elegant
672
     * when there's so many special cases...
673
     *
674
     * So here's the basic idea. For each pipe, enable writes to it only,
675
     * then put out the relocation for ZPASS_ADDR, taking into account a
676
     * 4-byte offset for each pipe. RV380 and older are special; they have
677
     * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
678
     * so there's a chipset cap for that. */
679
    switch (gb_pipes) {
680
        case 4:
681
            /* pipe 3 only */
682
            OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
683
            OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
684
            OUT_CS_RELOC(r300->query_current);
685
        case 3:
686
            /* pipe 2 only */
687
            OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
688
            OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
689
            OUT_CS_RELOC(r300->query_current);
690
        case 2:
691
            /* pipe 1 only */
692
            /* As mentioned above, accomodate RV380 and older. */
693
            OUT_CS_REG(R300_SU_REG_DEST,
694
                    1 << (caps->high_second_pipe ? 3 : 1));
695
            OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
696
            OUT_CS_RELOC(r300->query_current);
697
        case 1:
698
            /* pipe 0 only */
699
            OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
700
            OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
701
            OUT_CS_RELOC(r300->query_current);
702
            break;
703
        default:
704
            fprintf(stderr, "r300: Implementation error: Chipset reports %d"
705
                    " pixel pipes!\n", gb_pipes);
706
            abort();
707
    }
708
 
709
    /* And, finally, reset it to normal... */
710
    OUT_CS_REG(R300_SU_REG_DEST, 0xF);
711
    END_CS;
712
}
713
 
714
static void rv530_emit_query_end_single_z(struct r300_context *r300,
715
                                          struct r300_query *query)
716
{
717
    CS_LOCALS(r300);
718
 
719
    BEGIN_CS(8);
720
    OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
721
    OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
722
    OUT_CS_RELOC(r300->query_current);
723
    OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
724
    END_CS;
725
}
726
 
727
static void rv530_emit_query_end_double_z(struct r300_context *r300,
728
                                          struct r300_query *query)
729
{
730
    CS_LOCALS(r300);
731
 
732
    BEGIN_CS(14);
733
    OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
734
    OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
735
    OUT_CS_RELOC(r300->query_current);
736
    OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
737
    OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
738
    OUT_CS_RELOC(r300->query_current);
739
    OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
740
    END_CS;
741
}
742
 
743
void r300_emit_query_end(struct r300_context* r300)
744
{
745
    struct r300_capabilities *caps = &r300->screen->caps;
746
    struct r300_query *query = r300->query_current;
747
 
748
    if (!query)
749
	return;
750
 
751
    if (query->begin_emitted == FALSE)
752
        return;
753
 
754
    if (caps->family == CHIP_RV530) {
755
        if (r300->screen->info.r300_num_z_pipes == 2)
756
            rv530_emit_query_end_double_z(r300, query);
757
        else
758
            rv530_emit_query_end_single_z(r300, query);
759
    } else
760
        r300_emit_query_end_frag_pipes(r300, query);
761
 
762
    query->begin_emitted = FALSE;
763
    query->num_results += query->num_pipes;
764
 
765
    /* XXX grab all the results and reset the counter. */
766
    if (query->num_results >= query->buf->size / 4 - 4) {
767
        query->num_results = (query->buf->size / 4) / 2;
768
        fprintf(stderr, "r300: Rewinding OQBO...\n");
769
    }
770
}
771
 
772
void r300_emit_invariant_state(struct r300_context *r300,
773
                               unsigned size, void *state)
774
{
775
    CS_LOCALS(r300);
776
    WRITE_CS_TABLE(state, size);
777
}
778
 
779
void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
780
{
781
    struct r300_rs_state* rs = state;
782
    CS_LOCALS(r300);
783
 
784
    BEGIN_CS(size);
785
    OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
786
    if (rs->polygon_offset_enable) {
787
        if (r300->zbuffer_bpp == 16) {
788
            OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
789
        } else {
790
            OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
791
        }
792
    }
793
    END_CS;
794
}
795
 
796
void r300_emit_rs_block_state(struct r300_context* r300,
797
                              unsigned size, void* state)
798
{
799
    struct r300_rs_block* rs = (struct r300_rs_block*)state;
800
    unsigned i;
801
    /* It's the same for both INST and IP tables */
802
    unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
803
    CS_LOCALS(r300);
804
 
805
    if (DBG_ON(r300, DBG_RS_BLOCK)) {
806
        r500_dump_rs_block(rs);
807
 
808
        fprintf(stderr, "r300: RS emit:\n");
809
 
810
        for (i = 0; i < count; i++)
811
            fprintf(stderr, "    : ip %d: 0x%08x\n", i, rs->ip[i]);
812
 
813
        for (i = 0; i < count; i++)
814
            fprintf(stderr, "    : inst %d: 0x%08x\n", i, rs->inst[i]);
815
 
816
        fprintf(stderr, "    : count: 0x%08x inst_count: 0x%08x\n",
817
            rs->count, rs->inst_count);
818
    }
819
 
820
    BEGIN_CS(size);
821
    OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
822
    OUT_CS(rs->vap_vtx_state_cntl);
823
    OUT_CS(rs->vap_vsm_vtx_assm);
824
    OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
825
    OUT_CS(rs->vap_out_vtx_fmt[0]);
826
    OUT_CS(rs->vap_out_vtx_fmt[1]);
827
    OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
828
    OUT_CS(rs->gb_enable);
829
 
830
    if (r300->screen->caps.is_r500) {
831
        OUT_CS_REG_SEQ(R500_RS_IP_0, count);
832
    } else {
833
        OUT_CS_REG_SEQ(R300_RS_IP_0, count);
834
    }
835
    OUT_CS_TABLE(rs->ip, count);
836
 
837
    OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
838
    OUT_CS(rs->count);
839
    OUT_CS(rs->inst_count);
840
 
841
    if (r300->screen->caps.is_r500) {
842
        OUT_CS_REG_SEQ(R500_RS_INST_0, count);
843
    } else {
844
        OUT_CS_REG_SEQ(R300_RS_INST_0, count);
845
    }
846
    OUT_CS_TABLE(rs->inst, count);
847
    END_CS;
848
}
849
 
850
void r300_emit_sample_mask(struct r300_context *r300,
851
                           unsigned size, void *state)
852
{
853
    unsigned mask = (*(unsigned*)state) & ((1 << 6)-1);
854
    CS_LOCALS(r300);
855
 
856
    BEGIN_CS(size);
857
    OUT_CS_REG(R300_SC_SCREENDOOR,
858
               mask | (mask << 6) | (mask << 12) | (mask << 18));
859
    END_CS;
860
}
861
 
862
void r300_emit_scissor_state(struct r300_context* r300,
863
                             unsigned size, void* state)
864
{
865
    struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
866
    CS_LOCALS(r300);
867
 
868
    BEGIN_CS(size);
869
    OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
870
    if (r300->screen->caps.is_r500) {
871
        OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
872
               (scissor->miny << R300_CLIPRECT_Y_SHIFT));
873
        OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
874
               ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
875
    } else {
876
        OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
877
               ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
878
        OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
879
               ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
880
    }
881
    END_CS;
882
}
883
 
884
void r300_emit_textures_state(struct r300_context *r300,
885
                              unsigned size, void *state)
886
{
887
    struct r300_textures_state *allstate = (struct r300_textures_state*)state;
888
    struct r300_texture_sampler_state *texstate;
889
    struct r300_resource *tex;
890
    unsigned i;
891
    boolean has_us_format = r300->screen->caps.has_us_format;
892
    CS_LOCALS(r300);
893
 
894
    BEGIN_CS(size);
895
    OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
896
 
897
    for (i = 0; i < allstate->count; i++) {
898
        if ((1 << i) & allstate->tx_enable) {
899
            texstate = &allstate->regs[i];
900
            tex = r300_resource(allstate->sampler_views[i]->base.texture);
901
 
902
            OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
903
            OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
904
            OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
905
                       texstate->border_color);
906
 
907
            OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
908
            OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
909
            OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
910
 
911
            OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
912
            OUT_CS_RELOC(tex);
913
 
914
            if (has_us_format) {
915
                OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4),
916
                           texstate->format.us_format0);
917
            }
918
        }
919
    }
920
    END_CS;
921
}
922
 
923
void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
924
                             boolean indexed, int instance_id)
925
{
926
    struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
927
    struct pipe_vertex_element *velem = r300->velems->velem;
928
    struct r300_resource *buf;
929
    int i;
930
    unsigned vertex_array_count = r300->velems->count;
931
    unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
932
    struct pipe_vertex_buffer *vb1, *vb2;
933
    unsigned *hw_format_size = r300->velems->format_size;
934
    unsigned size1, size2, offset1, offset2, stride1, stride2;
935
    CS_LOCALS(r300);
936
 
937
    BEGIN_CS(2 + packet_size + vertex_array_count * 2);
938
    OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
939
    OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
940
 
941
    if (instance_id == -1) {
942
        /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
943
        for (i = 0; i < vertex_array_count - 1; i += 2) {
944
            vb1 = &vbuf[velem[i].vertex_buffer_index];
945
            vb2 = &vbuf[velem[i+1].vertex_buffer_index];
946
            size1 = hw_format_size[i];
947
            size2 = hw_format_size[i+1];
948
 
949
            OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
950
                   R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
951
            OUT_CS(vb1->buffer_offset + velem[i].src_offset   + offset * vb1->stride);
952
            OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
953
        }
954
 
955
        if (vertex_array_count & 1) {
956
            vb1 = &vbuf[velem[i].vertex_buffer_index];
957
            size1 = hw_format_size[i];
958
 
959
            OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
960
            OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
961
        }
962
 
963
        for (i = 0; i < vertex_array_count; i++) {
964
            buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
965
            OUT_CS_RELOC(buf);
966
        }
967
    } else {
968
        /* Instanced arrays. */
969
        for (i = 0; i < vertex_array_count - 1; i += 2) {
970
            vb1 = &vbuf[velem[i].vertex_buffer_index];
971
            vb2 = &vbuf[velem[i+1].vertex_buffer_index];
972
            size1 = hw_format_size[i];
973
            size2 = hw_format_size[i+1];
974
 
975
            if (velem[i].instance_divisor) {
976
                stride1 = 0;
977
                offset1 = vb1->buffer_offset + velem[i].src_offset +
978
                          (instance_id / velem[i].instance_divisor) * vb1->stride;
979
            } else {
980
                stride1 = vb1->stride;
981
                offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
982
            }
983
            if (velem[i+1].instance_divisor) {
984
                stride2 = 0;
985
                offset2 = vb2->buffer_offset + velem[i+1].src_offset +
986
                          (instance_id / velem[i+1].instance_divisor) * vb2->stride;
987
            } else {
988
                stride2 = vb2->stride;
989
                offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride;
990
            }
991
 
992
            OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
993
                   R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
994
            OUT_CS(offset1);
995
            OUT_CS(offset2);
996
        }
997
 
998
        if (vertex_array_count & 1) {
999
            vb1 = &vbuf[velem[i].vertex_buffer_index];
1000
            size1 = hw_format_size[i];
1001
 
1002
            if (velem[i].instance_divisor) {
1003
                stride1 = 0;
1004
                offset1 = vb1->buffer_offset + velem[i].src_offset +
1005
                          (instance_id / velem[i].instance_divisor) * vb1->stride;
1006
            } else {
1007
                stride1 = vb1->stride;
1008
                offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
1009
            }
1010
 
1011
            OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
1012
            OUT_CS(offset1);
1013
        }
1014
 
1015
        for (i = 0; i < vertex_array_count; i++) {
1016
            buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
1017
            OUT_CS_RELOC(buf);
1018
        }
1019
    }
1020
    END_CS;
1021
}
1022
 
1023
void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
1024
{
1025
    CS_LOCALS(r300);
1026
 
1027
    DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
1028
            "vertex size %d\n", r300->vbo,
1029
            r300->vertex_info.size);
1030
    /* Set the pointer to our vertex buffer. The emitted values are this:
1031
     * PACKET3 [3D_LOAD_VBPNTR]
1032
     * COUNT   [1]
1033
     * FORMAT  [size | stride << 8]
1034
     * OFFSET  [offset into BO]
1035
     * VBPNTR  [relocated BO]
1036
     */
1037
    BEGIN_CS(7);
1038
    OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
1039
    OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
1040
    OUT_CS(r300->vertex_info.size |
1041
            (r300->vertex_info.size << 8));
1042
    OUT_CS(r300->draw_vbo_offset);
1043
    OUT_CS(0);
1044
 
1045
    assert(r300->vbo_cs);
1046
    cs_winsys->cs_write_reloc(cs_copy, r300->vbo_cs);
1047
    CS_USED_DW(2);
1048
    END_CS;
1049
}
1050
 
1051
void r300_emit_vertex_stream_state(struct r300_context* r300,
1052
                                   unsigned size, void* state)
1053
{
1054
    struct r300_vertex_stream_state *streams =
1055
        (struct r300_vertex_stream_state*)state;
1056
    unsigned i;
1057
    CS_LOCALS(r300);
1058
 
1059
    if (DBG_ON(r300, DBG_PSC)) {
1060
        fprintf(stderr, "r300: PSC emit:\n");
1061
 
1062
        for (i = 0; i < streams->count; i++) {
1063
            fprintf(stderr, "    : prog_stream_cntl%d: 0x%08x\n", i,
1064
                   streams->vap_prog_stream_cntl[i]);
1065
        }
1066
 
1067
        for (i = 0; i < streams->count; i++) {
1068
            fprintf(stderr, "    : prog_stream_cntl_ext%d: 0x%08x\n", i,
1069
                   streams->vap_prog_stream_cntl_ext[i]);
1070
        }
1071
    }
1072
 
1073
    BEGIN_CS(size);
1074
    OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
1075
    OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
1076
    OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
1077
    OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
1078
    END_CS;
1079
}
1080
 
1081
void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
1082
{
1083
    CS_LOCALS(r300);
1084
 
1085
    BEGIN_CS(size);
1086
    OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1087
    END_CS;
1088
}
1089
 
1090
void r300_emit_vap_invariant_state(struct r300_context *r300,
1091
                                   unsigned size, void *state)
1092
{
1093
    CS_LOCALS(r300);
1094
    WRITE_CS_TABLE(state, size);
1095
}
1096
 
1097
void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
1098
{
1099
    struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
1100
    struct r300_vertex_program_code* code = &vs->code;
1101
    struct r300_screen* r300screen = r300->screen;
1102
    unsigned instruction_count = code->length / 4;
1103
 
1104
    unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
1105
    unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
1106
    unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
1107
    unsigned temp_count = MAX2(code->num_temporaries, 1);
1108
 
1109
    unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
1110
                                  vtx_mem_size / output_count, 10);
1111
    unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
1112
 
1113
    CS_LOCALS(r300);
1114
 
1115
    BEGIN_CS(size);
1116
 
1117
    /* R300_VAP_PVS_CODE_CNTL_0
1118
     * R300_VAP_PVS_CONST_CNTL
1119
     * R300_VAP_PVS_CODE_CNTL_1
1120
     * See the r5xx docs for instructions on how to use these. */
1121
    OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1122
	       R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1123
	       R300_PVS_LAST_INST(instruction_count - 1));
1124
    OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1125
 
1126
    OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1127
    OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1128
    OUT_CS_TABLE(code->body.d, code->length);
1129
 
1130
    OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1131
            R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1132
            R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1133
            R300_PVS_VF_MAX_VTX_NUM(12) |
1134
            (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1135
 
1136
    /* Emit flow control instructions.  Even if there are no fc instructions,
1137
     * we still need to write the registers to make sure they are cleared. */
1138
    OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1139
    if (r300screen->caps.is_r500) {
1140
        OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2);
1141
        OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2);
1142
    } else {
1143
        OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS);
1144
        OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS);
1145
    }
1146
    OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS);
1147
    OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS);
1148
 
1149
    END_CS;
1150
}
1151
 
1152
void r300_emit_vs_constants(struct r300_context* r300,
1153
                            unsigned size, void *state)
1154
{
1155
    unsigned count =
1156
        ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1157
    struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1158
    struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1159
    unsigned i;
1160
    int imm_first = vs->externals_count;
1161
    int imm_end = vs->code.constants.Count;
1162
    int imm_count = vs->immediates_count;
1163
    CS_LOCALS(r300);
1164
 
1165
    BEGIN_CS(size);
1166
    OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1167
               R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1168
               R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1169
    if (vs->externals_count) {
1170
        OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1171
                   (r300->screen->caps.is_r500 ?
1172
                   R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1173
        OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1174
        if (buf->remap_table){
1175
            for (i = 0; i < count; i++) {
1176
                uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1177
                OUT_CS_TABLE(data, 4);
1178
            }
1179
        } else {
1180
            OUT_CS_TABLE(buf->ptr, count * 4);
1181
        }
1182
    }
1183
 
1184
    /* Emit immediates. */
1185
    if (imm_count) {
1186
        OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1187
                   (r300->screen->caps.is_r500 ?
1188
                   R500_PVS_CONST_START : R300_PVS_CONST_START) +
1189
                   buf->buffer_base + imm_first);
1190
        OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1191
        for (i = imm_first; i < imm_end; i++) {
1192
            const float *data = vs->code.constants.Constants[i].u.Immediate;
1193
            OUT_CS_TABLE(data, 4);
1194
        }
1195
    }
1196
    END_CS;
1197
}
1198
 
1199
void r300_emit_viewport_state(struct r300_context* r300,
1200
                              unsigned size, void* state)
1201
{
1202
    struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1203
    CS_LOCALS(r300);
1204
 
1205
    BEGIN_CS(size);
1206
    OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1207
    OUT_CS_TABLE(&viewport->xscale, 6);
1208
    OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1209
    END_CS;
1210
}
1211
 
1212
void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1213
{
1214
    struct pipe_framebuffer_state *fb =
1215
        (struct pipe_framebuffer_state*)r300->fb_state.state;
1216
    struct r300_resource* tex;
1217
    CS_LOCALS(r300);
1218
 
1219
    tex = r300_resource(fb->zsbuf->texture);
1220
 
1221
    BEGIN_CS(size);
1222
    OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1223
    OUT_CS(0);
1224
    OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1225
    OUT_CS(r300->hiz_clear_value);
1226
    END_CS;
1227
 
1228
    /* Mark the current zbuffer's hiz ram as in use. */
1229
    r300->hiz_in_use = TRUE;
1230
    r300->hiz_func = HIZ_FUNC_NONE;
1231
    r300_mark_atom_dirty(r300, &r300->hyperz_state);
1232
}
1233
 
1234
void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1235
{
1236
    struct pipe_framebuffer_state *fb =
1237
        (struct pipe_framebuffer_state*)r300->fb_state.state;
1238
    struct r300_resource *tex;
1239
    CS_LOCALS(r300);
1240
 
1241
    tex = r300_resource(fb->zsbuf->texture);
1242
 
1243
    BEGIN_CS(size);
1244
    OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1245
    OUT_CS(0);
1246
    OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1247
    OUT_CS(0);
1248
    END_CS;
1249
 
1250
    /* Mark the current zbuffer's zmask as in use. */
1251
    r300->zmask_in_use = TRUE;
1252
    r300_mark_atom_dirty(r300, &r300->hyperz_state);
1253
}
1254
 
1255
void r300_emit_cmask_clear(struct r300_context *r300, unsigned size, void *state)
1256
{
1257
    struct pipe_framebuffer_state *fb =
1258
        (struct pipe_framebuffer_state*)r300->fb_state.state;
1259
    struct r300_resource *tex;
1260
    CS_LOCALS(r300);
1261
 
1262
    tex = r300_resource(fb->cbufs[0]->texture);
1263
 
1264
    BEGIN_CS(size);
1265
    OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK, 2);
1266
    OUT_CS(0);
1267
    OUT_CS(tex->tex.cmask_dwords);
1268
    OUT_CS(0);
1269
    END_CS;
1270
 
1271
    /* Mark the current zbuffer's zmask as in use. */
1272
    r300->cmask_in_use = TRUE;
1273
    r300_mark_fb_state_dirty(r300, R300_CHANGED_CMASK_ENABLE);
1274
}
1275
 
1276
void r300_emit_ztop_state(struct r300_context* r300,
1277
                          unsigned size, void* state)
1278
{
1279
    struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1280
    CS_LOCALS(r300);
1281
 
1282
    BEGIN_CS(size);
1283
    OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1284
    END_CS;
1285
}
1286
 
1287
void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1288
{
1289
    CS_LOCALS(r300);
1290
 
1291
    BEGIN_CS(size);
1292
    OUT_CS_REG(R300_TX_INVALTAGS, 0);
1293
    END_CS;
1294
}
1295
 
1296
boolean r300_emit_buffer_validate(struct r300_context *r300,
1297
                                  boolean do_validate_vertex_buffers,
1298
                                  struct pipe_resource *index_buffer)
1299
{
1300
    struct pipe_framebuffer_state *fb =
1301
        (struct pipe_framebuffer_state*)r300->fb_state.state;
1302
    struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
1303
    struct r300_textures_state *texstate =
1304
        (struct r300_textures_state*)r300->textures_state.state;
1305
    struct r300_resource *tex;
1306
    unsigned i;
1307
    boolean flushed = FALSE;
1308
 
1309
validate:
1310
    if (r300->fb_state.dirty) {
1311
        /* Color buffers... */
1312
        for (i = 0; i < fb->nr_cbufs; i++) {
1313
            tex = r300_resource(fb->cbufs[i]->texture);
1314
            assert(tex && tex->buf && "cbuf is marked, but NULL!");
1315
            r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
1316
                                    RADEON_USAGE_READWRITE,
1317
                                    r300_surface(fb->cbufs[i])->domain);
1318
        }
1319
        /* ...depth buffer... */
1320
        if (fb->zsbuf) {
1321
            tex = r300_resource(fb->zsbuf->texture);
1322
            assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1323
            r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
1324
                                    RADEON_USAGE_READWRITE,
1325
                                    r300_surface(fb->zsbuf)->domain);
1326
        }
1327
    }
1328
    /* The AA resolve buffer. */
1329
    if (r300->aa_state.dirty) {
1330
        if (aa->dest) {
1331
            r300->rws->cs_add_reloc(r300->cs, aa->dest->cs_buf,
1332
                                    RADEON_USAGE_WRITE,
1333
                                    aa->dest->domain);
1334
        }
1335
    }
1336
    if (r300->textures_state.dirty) {
1337
        /* ...textures... */
1338
        for (i = 0; i < texstate->count; i++) {
1339
            if (!(texstate->tx_enable & (1 << i))) {
1340
                continue;
1341
            }
1342
 
1343
            tex = r300_resource(texstate->sampler_views[i]->base.texture);
1344
            r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, RADEON_USAGE_READ,
1345
                                    tex->domain);
1346
        }
1347
    }
1348
    /* ...occlusion query buffer... */
1349
    if (r300->query_current)
1350
        r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf,
1351
                                RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1352
    /* ...vertex buffer for SWTCL path... */
1353
    if (r300->vbo_cs)
1354
        r300->rws->cs_add_reloc(r300->cs, r300->vbo_cs,
1355
                                RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1356
    /* ...vertex buffers for HWTCL path... */
1357
    if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1358
        struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1359
        struct pipe_vertex_buffer *last = r300->vertex_buffer +
1360
                                      r300->nr_vertex_buffers;
1361
        struct pipe_resource *buf;
1362
 
1363
        for (; vbuf != last; vbuf++) {
1364
            buf = vbuf->buffer;
1365
            if (!buf)
1366
                continue;
1367
 
1368
            r300->rws->cs_add_reloc(r300->cs, r300_resource(buf)->cs_buf,
1369
                                    RADEON_USAGE_READ,
1370
                                    r300_resource(buf)->domain);
1371
        }
1372
    }
1373
    /* ...and index buffer for HWTCL path. */
1374
    if (index_buffer)
1375
        r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
1376
                                RADEON_USAGE_READ,
1377
                                r300_resource(index_buffer)->domain);
1378
 
1379
    /* Now do the validation (flush is called inside cs_validate on failure). */
1380
    if (!r300->rws->cs_validate(r300->cs)) {
1381
        /* Ooops, an infinite loop, give up. */
1382
        if (flushed)
1383
            return FALSE;
1384
 
1385
        flushed = TRUE;
1386
        goto validate;
1387
    }
1388
 
1389
    return TRUE;
1390
}
1391
 
1392
unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1393
{
1394
    struct r300_atom* atom;
1395
    unsigned dwords = 0;
1396
 
1397
    foreach_dirty_atom(r300, atom) {
1398
        if (atom->dirty) {
1399
            dwords += atom->size;
1400
        }
1401
    }
1402
 
1403
    /* let's reserve some more, just in case */
1404
    dwords += 32;
1405
 
1406
    return dwords;
1407
}
1408
 
1409
unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1410
{
1411
    unsigned dwords = 0;
1412
 
1413
    /* Emitted in flush. */
1414
    dwords += 26; /* emit_query_end */
1415
    dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1416
    if (r300->screen->caps.is_r500)
1417
        dwords += 2; /* emit_index_bias */
1418
    if (r300->screen->info.drm_minor >= 6)
1419
        dwords += 3; /* MSPOS */
1420
 
1421
    return dwords;
1422
}
1423
 
1424
/* Emit all dirty state. */
1425
void r300_emit_dirty_state(struct r300_context* r300)
1426
{
1427
    struct r300_atom *atom;
1428
 
1429
    foreach_dirty_atom(r300, atom) {
1430
        if (atom->dirty) {
1431
            atom->emit(r300, atom->size, atom->state);
1432
            atom->dirty = FALSE;
1433
        }
1434
    }
1435
 
1436
    r300->first_dirty = NULL;
1437
    r300->last_dirty = NULL;
1438
    r300->dirty_hw++;
1439
}