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5564 | serge | 1 | /************************************************************************** |
2 | |||
3 | Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and |
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4 | VA Linux Systems Inc., Fremont, California. |
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5 | |||
6 | All Rights Reserved. |
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7 | |||
8 | Permission is hereby granted, free of charge, to any person obtaining |
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9 | a copy of this software and associated documentation files (the |
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10 | "Software"), to deal in the Software without restriction, including |
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11 | without limitation the rights to use, copy, modify, merge, publish, |
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12 | distribute, sublicense, and/or sell copies of the Software, and to |
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13 | permit persons to whom the Software is furnished to do so, subject to |
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14 | the following conditions: |
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15 | |||
16 | The above copyright notice and this permission notice (including the |
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17 | next paragraph) shall be included in all copies or substantial |
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18 | portions of the Software. |
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19 | |||
20 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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21 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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23 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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24 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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25 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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26 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | |||
28 | **************************************************************************/ |
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29 | |||
30 | /** |
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31 | * \file radeon_screen.c |
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32 | * Screen initialization functions for the Radeon driver. |
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33 | * |
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34 | * \author Kevin E. Martin |
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35 | * \author Gareth Hughes |
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36 | */ |
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37 | |||
38 | #include |
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39 | #include "main/glheader.h" |
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40 | #include "main/imports.h" |
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41 | #include "main/mtypes.h" |
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42 | #include "main/framebuffer.h" |
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43 | #include "main/renderbuffer.h" |
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44 | #include "main/fbobject.h" |
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45 | #include "swrast/s_renderbuffer.h" |
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46 | |||
47 | #include "radeon_chipset.h" |
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48 | #include "radeon_screen.h" |
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49 | #include "radeon_common.h" |
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50 | #include "radeon_common_context.h" |
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51 | #if defined(RADEON_R100) |
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52 | #include "radeon_context.h" |
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53 | #include "radeon_tex.h" |
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54 | #elif defined(RADEON_R200) |
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55 | #include "r200_context.h" |
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56 | #include "r200_tex.h" |
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57 | #endif |
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58 | |||
59 | #include "utils.h" |
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60 | |||
61 | #include "GL/internal/dri_interface.h" |
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62 | |||
63 | /* Radeon configuration |
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64 | */ |
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65 | #include "xmlpool.h" |
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66 | |||
67 | #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ |
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68 | DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ |
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69 | DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ |
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70 | DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ |
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71 | DRI_CONF_OPT_END |
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72 | |||
73 | #if defined(RADEON_R100) /* R100 */ |
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74 | static const __DRIconfigOptionsExtension radeon_config_options = { |
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75 | .base = { __DRI_CONFIG_OPTIONS, 1 }, |
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76 | .xml = |
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77 | DRI_CONF_BEGIN |
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78 | DRI_CONF_SECTION_PERFORMANCE |
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79 | DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) |
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80 | DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) |
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81 | DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) |
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82 | DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) |
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83 | DRI_CONF_HYPERZ("false") |
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84 | DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) |
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85 | DRI_CONF_SECTION_END |
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86 | DRI_CONF_SECTION_QUALITY |
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87 | DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) |
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88 | DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") |
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89 | DRI_CONF_NO_NEG_LOD_BIAS("false") |
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90 | DRI_CONF_FORCE_S3TC_ENABLE("false") |
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91 | DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) |
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92 | DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) |
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93 | DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) |
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94 | DRI_CONF_SECTION_END |
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95 | DRI_CONF_SECTION_DEBUG |
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96 | DRI_CONF_NO_RAST("false") |
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97 | DRI_CONF_SECTION_END |
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98 | DRI_CONF_END |
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99 | }; |
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100 | |||
101 | #elif defined(RADEON_R200) |
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102 | static const __DRIconfigOptionsExtension radeon_config_options = { |
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103 | .base = { __DRI_CONFIG_OPTIONS, 1 }, |
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104 | .xml = |
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105 | DRI_CONF_BEGIN |
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106 | DRI_CONF_SECTION_PERFORMANCE |
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107 | DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) |
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108 | DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) |
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109 | DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) |
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110 | DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) |
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111 | DRI_CONF_HYPERZ("false") |
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112 | DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) |
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113 | DRI_CONF_SECTION_END |
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114 | DRI_CONF_SECTION_QUALITY |
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115 | DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) |
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116 | DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") |
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117 | DRI_CONF_NO_NEG_LOD_BIAS("false") |
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118 | DRI_CONF_FORCE_S3TC_ENABLE("false") |
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119 | DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) |
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120 | DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) |
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121 | DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) |
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122 | DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") |
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123 | DRI_CONF_SECTION_END |
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124 | DRI_CONF_SECTION_DEBUG |
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125 | DRI_CONF_NO_RAST("false") |
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126 | DRI_CONF_SECTION_END |
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127 | DRI_CONF_END |
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128 | }; |
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129 | #endif |
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130 | |||
131 | #ifndef RADEON_INFO_TILE_CONFIG |
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132 | #define RADEON_INFO_TILE_CONFIG 0x6 |
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133 | #endif |
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134 | |||
135 | static int |
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136 | radeonGetParam(__DRIscreen *sPriv, int param, void *value) |
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137 | { |
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138 | int ret; |
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139 | drm_radeon_getparam_t gp = { 0 }; |
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140 | struct drm_radeon_info info = { 0 }; |
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141 | |||
142 | if (sPriv->drm_version.major >= 2) { |
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143 | info.value = (uint64_t)(uintptr_t)value; |
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144 | switch (param) { |
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145 | case RADEON_PARAM_DEVICE_ID: |
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146 | info.request = RADEON_INFO_DEVICE_ID; |
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147 | break; |
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148 | case RADEON_PARAM_NUM_GB_PIPES: |
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149 | info.request = RADEON_INFO_NUM_GB_PIPES; |
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150 | break; |
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151 | case RADEON_PARAM_NUM_Z_PIPES: |
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152 | info.request = RADEON_INFO_NUM_Z_PIPES; |
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153 | break; |
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154 | case RADEON_INFO_TILE_CONFIG: |
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155 | info.request = RADEON_INFO_TILE_CONFIG; |
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156 | break; |
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157 | default: |
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158 | return -EINVAL; |
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159 | } |
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160 | ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); |
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161 | } else { |
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162 | gp.param = param; |
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163 | gp.value = value; |
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164 | |||
165 | ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); |
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166 | } |
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167 | return ret; |
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168 | } |
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169 | |||
170 | #if defined(RADEON_R100) |
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171 | static const __DRItexBufferExtension radeonTexBufferExtension = { |
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172 | .base = { __DRI_TEX_BUFFER, 3 }, |
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173 | |||
174 | .setTexBuffer = radeonSetTexBuffer, |
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175 | .setTexBuffer2 = radeonSetTexBuffer2, |
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176 | .releaseTexBuffer = NULL, |
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177 | }; |
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178 | #elif defined(RADEON_R200) |
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179 | static const __DRItexBufferExtension r200TexBufferExtension = { |
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180 | .base = { __DRI_TEX_BUFFER, 3 }, |
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181 | |||
182 | .setTexBuffer = r200SetTexBuffer, |
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183 | .setTexBuffer2 = r200SetTexBuffer2, |
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184 | .releaseTexBuffer = NULL, |
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185 | }; |
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186 | #endif |
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187 | |||
188 | static void |
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189 | radeonDRI2Flush(__DRIdrawable *drawable) |
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190 | { |
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191 | radeonContextPtr rmesa; |
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192 | |||
193 | rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; |
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194 | radeonFlush(&rmesa->glCtx); |
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195 | } |
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196 | |||
197 | static const struct __DRI2flushExtensionRec radeonFlushExtension = { |
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198 | .base = { __DRI2_FLUSH, 3 }, |
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199 | |||
200 | .flush = radeonDRI2Flush, |
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201 | .invalidate = dri2InvalidateDrawable, |
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202 | }; |
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203 | |||
204 | static __DRIimage * |
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205 | radeon_create_image_from_name(__DRIscreen *screen, |
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206 | int width, int height, int format, |
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207 | int name, int pitch, void *loaderPrivate) |
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208 | { |
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209 | __DRIimage *image; |
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210 | radeonScreenPtr radeonScreen = screen->driverPrivate; |
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211 | |||
212 | if (name == 0) |
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213 | return NULL; |
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214 | |||
215 | image = calloc(1, sizeof *image); |
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216 | if (image == NULL) |
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217 | return NULL; |
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218 | |||
219 | switch (format) { |
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220 | case __DRI_IMAGE_FORMAT_RGB565: |
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221 | image->format = MESA_FORMAT_B5G6R5_UNORM; |
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222 | image->internal_format = GL_RGB; |
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223 | image->data_type = GL_UNSIGNED_BYTE; |
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224 | break; |
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225 | case __DRI_IMAGE_FORMAT_XRGB8888: |
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226 | image->format = MESA_FORMAT_B8G8R8X8_UNORM; |
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227 | image->internal_format = GL_RGB; |
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228 | image->data_type = GL_UNSIGNED_BYTE; |
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229 | break; |
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230 | case __DRI_IMAGE_FORMAT_ARGB8888: |
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231 | image->format = MESA_FORMAT_B8G8R8A8_UNORM; |
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232 | image->internal_format = GL_RGBA; |
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233 | image->data_type = GL_UNSIGNED_BYTE; |
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234 | break; |
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235 | default: |
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236 | free(image); |
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237 | return NULL; |
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238 | } |
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239 | |||
240 | image->data = loaderPrivate; |
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241 | image->cpp = _mesa_get_format_bytes(image->format); |
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242 | image->width = width; |
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243 | image->pitch = pitch; |
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244 | image->height = height; |
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245 | |||
246 | image->bo = radeon_bo_open(radeonScreen->bom, |
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247 | (uint32_t)name, |
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248 | image->pitch * image->height * image->cpp, |
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249 | 0, |
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250 | RADEON_GEM_DOMAIN_VRAM, |
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251 | 0); |
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252 | |||
253 | if (image->bo == NULL) { |
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254 | free(image); |
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255 | return NULL; |
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256 | } |
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257 | |||
258 | return image; |
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259 | } |
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260 | |||
261 | static __DRIimage * |
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262 | radeon_create_image_from_renderbuffer(__DRIcontext *context, |
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263 | int renderbuffer, void *loaderPrivate) |
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264 | { |
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265 | __DRIimage *image; |
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266 | radeonContextPtr radeon = context->driverPrivate; |
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267 | struct gl_renderbuffer *rb; |
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268 | struct radeon_renderbuffer *rrb; |
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269 | |||
270 | rb = _mesa_lookup_renderbuffer(&radeon->glCtx, renderbuffer); |
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271 | if (!rb) { |
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272 | _mesa_error(&radeon->glCtx, |
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273 | GL_INVALID_OPERATION, "glRenderbufferExternalMESA"); |
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274 | return NULL; |
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275 | } |
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276 | |||
277 | rrb = radeon_renderbuffer(rb); |
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278 | image = calloc(1, sizeof *image); |
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279 | if (image == NULL) |
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280 | return NULL; |
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281 | |||
282 | image->internal_format = rb->InternalFormat; |
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283 | image->format = rb->Format; |
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284 | image->cpp = rrb->cpp; |
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285 | image->data_type = GL_UNSIGNED_BYTE; |
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286 | image->data = loaderPrivate; |
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287 | radeon_bo_ref(rrb->bo); |
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288 | image->bo = rrb->bo; |
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289 | |||
290 | image->width = rb->Width; |
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291 | image->height = rb->Height; |
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292 | image->pitch = rrb->pitch / image->cpp; |
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293 | |||
294 | return image; |
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295 | } |
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296 | |||
297 | static void |
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298 | radeon_destroy_image(__DRIimage *image) |
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299 | { |
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300 | radeon_bo_unref(image->bo); |
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301 | free(image); |
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302 | } |
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303 | |||
304 | static __DRIimage * |
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305 | radeon_create_image(__DRIscreen *screen, |
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306 | int width, int height, int format, |
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307 | unsigned int use, |
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308 | void *loaderPrivate) |
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309 | { |
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310 | __DRIimage *image; |
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311 | radeonScreenPtr radeonScreen = screen->driverPrivate; |
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312 | |||
313 | image = calloc(1, sizeof *image); |
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314 | if (image == NULL) |
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315 | return NULL; |
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316 | |||
317 | image->dri_format = format; |
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318 | |||
319 | switch (format) { |
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320 | case __DRI_IMAGE_FORMAT_RGB565: |
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321 | image->format = MESA_FORMAT_B5G6R5_UNORM; |
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322 | image->internal_format = GL_RGB; |
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323 | image->data_type = GL_UNSIGNED_BYTE; |
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324 | break; |
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325 | case __DRI_IMAGE_FORMAT_XRGB8888: |
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326 | image->format = MESA_FORMAT_B8G8R8X8_UNORM; |
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327 | image->internal_format = GL_RGB; |
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328 | image->data_type = GL_UNSIGNED_BYTE; |
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329 | break; |
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330 | case __DRI_IMAGE_FORMAT_ARGB8888: |
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331 | image->format = MESA_FORMAT_B8G8R8A8_UNORM; |
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332 | image->internal_format = GL_RGBA; |
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333 | image->data_type = GL_UNSIGNED_BYTE; |
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334 | break; |
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335 | default: |
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336 | free(image); |
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337 | return NULL; |
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338 | } |
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339 | |||
340 | image->data = loaderPrivate; |
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341 | image->cpp = _mesa_get_format_bytes(image->format); |
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342 | image->width = width; |
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343 | image->height = height; |
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344 | image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp; |
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345 | |||
346 | image->bo = radeon_bo_open(radeonScreen->bom, |
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347 | 0, |
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348 | image->pitch * image->height * image->cpp, |
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349 | 0, |
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350 | RADEON_GEM_DOMAIN_VRAM, |
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351 | 0); |
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352 | |||
353 | if (image->bo == NULL) { |
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354 | free(image); |
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355 | return NULL; |
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356 | } |
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357 | |||
358 | return image; |
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359 | } |
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360 | |||
361 | static GLboolean |
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362 | radeon_query_image(__DRIimage *image, int attrib, int *value) |
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363 | { |
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364 | switch (attrib) { |
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365 | case __DRI_IMAGE_ATTRIB_STRIDE: |
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366 | *value = image->pitch * image->cpp; |
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367 | return GL_TRUE; |
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368 | case __DRI_IMAGE_ATTRIB_HANDLE: |
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369 | *value = image->bo->handle; |
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370 | return GL_TRUE; |
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371 | case __DRI_IMAGE_ATTRIB_NAME: |
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372 | radeon_gem_get_kernel_name(image->bo, (uint32_t *) value); |
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373 | return GL_TRUE; |
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374 | default: |
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375 | return GL_FALSE; |
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376 | } |
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377 | } |
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378 | |||
379 | static const __DRIimageExtension radeonImageExtension = { |
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380 | .base = { __DRI_IMAGE, 1 }, |
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381 | |||
382 | .createImageFromName = radeon_create_image_from_name, |
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383 | .createImageFromRenderbuffer = radeon_create_image_from_renderbuffer, |
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384 | .destroyImage = radeon_destroy_image, |
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385 | .createImage = radeon_create_image, |
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386 | .queryImage = radeon_query_image |
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387 | }; |
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388 | |||
389 | static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) |
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390 | { |
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391 | screen->device_id = device_id; |
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392 | screen->chip_flags = 0; |
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393 | switch ( device_id ) { |
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394 | #if defined(RADEON_R100) |
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395 | case PCI_CHIP_RN50_515E: |
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396 | case PCI_CHIP_RN50_5969: |
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397 | return -1; |
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398 | |||
399 | case PCI_CHIP_RADEON_LY: |
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400 | case PCI_CHIP_RADEON_LZ: |
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401 | case PCI_CHIP_RADEON_QY: |
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402 | case PCI_CHIP_RADEON_QZ: |
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403 | screen->chip_family = CHIP_FAMILY_RV100; |
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404 | break; |
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405 | |||
406 | case PCI_CHIP_RS100_4136: |
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407 | case PCI_CHIP_RS100_4336: |
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408 | screen->chip_family = CHIP_FAMILY_RS100; |
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409 | break; |
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410 | |||
411 | case PCI_CHIP_RS200_4137: |
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412 | case PCI_CHIP_RS200_4337: |
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413 | case PCI_CHIP_RS250_4237: |
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414 | case PCI_CHIP_RS250_4437: |
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415 | screen->chip_family = CHIP_FAMILY_RS200; |
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416 | break; |
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417 | |||
418 | case PCI_CHIP_RADEON_QD: |
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419 | case PCI_CHIP_RADEON_QE: |
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420 | case PCI_CHIP_RADEON_QF: |
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421 | case PCI_CHIP_RADEON_QG: |
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422 | /* all original radeons (7200) presumably have a stencil op bug */ |
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423 | screen->chip_family = CHIP_FAMILY_R100; |
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424 | screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED; |
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425 | break; |
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426 | |||
427 | case PCI_CHIP_RV200_QW: |
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428 | case PCI_CHIP_RV200_QX: |
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429 | case PCI_CHIP_RADEON_LW: |
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430 | case PCI_CHIP_RADEON_LX: |
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431 | screen->chip_family = CHIP_FAMILY_RV200; |
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432 | screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED; |
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433 | break; |
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434 | |||
435 | #elif defined(RADEON_R200) |
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436 | case PCI_CHIP_R200_BB: |
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437 | case PCI_CHIP_R200_QH: |
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438 | case PCI_CHIP_R200_QL: |
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439 | case PCI_CHIP_R200_QM: |
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440 | screen->chip_family = CHIP_FAMILY_R200; |
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441 | screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED; |
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442 | break; |
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443 | |||
444 | case PCI_CHIP_RV250_If: |
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445 | case PCI_CHIP_RV250_Ig: |
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446 | case PCI_CHIP_RV250_Ld: |
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447 | case PCI_CHIP_RV250_Lf: |
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448 | case PCI_CHIP_RV250_Lg: |
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449 | screen->chip_family = CHIP_FAMILY_RV250; |
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450 | screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED; |
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451 | break; |
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452 | |||
453 | case PCI_CHIP_RV280_4C6E: |
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454 | case PCI_CHIP_RV280_5960: |
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455 | case PCI_CHIP_RV280_5961: |
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456 | case PCI_CHIP_RV280_5962: |
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457 | case PCI_CHIP_RV280_5964: |
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458 | case PCI_CHIP_RV280_5965: |
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459 | case PCI_CHIP_RV280_5C61: |
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460 | case PCI_CHIP_RV280_5C63: |
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461 | screen->chip_family = CHIP_FAMILY_RV280; |
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462 | screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED; |
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463 | break; |
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464 | |||
465 | case PCI_CHIP_RS300_5834: |
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466 | case PCI_CHIP_RS300_5835: |
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467 | case PCI_CHIP_RS350_7834: |
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468 | case PCI_CHIP_RS350_7835: |
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469 | screen->chip_family = CHIP_FAMILY_RS300; |
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470 | screen->chip_flags = RADEON_CHIPSET_DEPTH_ALWAYS_TILED; |
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471 | break; |
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472 | #endif |
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473 | |||
474 | default: |
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475 | fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", |
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476 | device_id); |
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477 | return -1; |
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478 | } |
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479 | |||
480 | return 0; |
||
481 | } |
||
482 | |||
483 | static int |
||
484 | radeonQueryRendererInteger(__DRIscreen *psp, int param, |
||
485 | unsigned int *value) |
||
486 | { |
||
487 | radeonScreenPtr screen = (radeonScreenPtr)psp->driverPrivate; |
||
488 | |||
489 | switch (param) { |
||
490 | case __DRI2_RENDERER_VENDOR_ID: |
||
491 | value[0] = 0x1002; |
||
492 | return 0; |
||
493 | case __DRI2_RENDERER_DEVICE_ID: |
||
494 | value[0] = screen->device_id; |
||
495 | return 0; |
||
496 | case __DRI2_RENDERER_ACCELERATED: |
||
497 | value[0] = 1; |
||
498 | return 0; |
||
499 | case __DRI2_RENDERER_VIDEO_MEMORY: { |
||
500 | struct drm_radeon_gem_info gem_info; |
||
501 | int retval; |
||
502 | memset(&gem_info, 0, sizeof(gem_info)); |
||
503 | |||
504 | /* Get GEM info. */ |
||
505 | retval = drmCommandWriteRead(psp->fd, DRM_RADEON_GEM_INFO, &gem_info, |
||
506 | sizeof(gem_info)); |
||
507 | |||
508 | if (retval) { |
||
509 | fprintf(stderr, "radeon: Failed to get MM info, error number %d\n", |
||
510 | retval); |
||
511 | return -1; |
||
512 | |||
513 | } |
||
514 | /* XXX: Do we want to return vram_size or vram_visible ? */ |
||
515 | value[0] = gem_info.vram_size >> 20; |
||
516 | return 0; |
||
517 | } |
||
518 | case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE: |
||
519 | value[0] = 0; |
||
520 | return 0; |
||
521 | default: |
||
522 | return driQueryRendererIntegerCommon(psp, param, value); |
||
523 | } |
||
524 | } |
||
525 | |||
526 | static int |
||
527 | radeonQueryRendererString(__DRIscreen *psp, int param, const char **value) |
||
528 | { |
||
529 | radeonScreenPtr screen = (radeonScreenPtr)psp->driverPrivate; |
||
530 | |||
531 | switch (param) { |
||
532 | case __DRI2_RENDERER_VENDOR_ID: |
||
533 | value[0] = radeonVendorString; |
||
534 | return 0; |
||
535 | case __DRI2_RENDERER_DEVICE_ID: |
||
536 | value[0] = radeonGetRendererString(screen); |
||
537 | return 0; |
||
538 | default: |
||
539 | return -1; |
||
540 | } |
||
541 | } |
||
542 | |||
543 | static const __DRI2rendererQueryExtension radeonRendererQueryExtension = { |
||
544 | .base = { __DRI2_RENDERER_QUERY, 1 }, |
||
545 | |||
546 | .queryInteger = radeonQueryRendererInteger, |
||
547 | .queryString = radeonQueryRendererString |
||
548 | }; |
||
549 | |||
550 | |||
551 | static const __DRIextension *radeon_screen_extensions[] = { |
||
552 | &dri2ConfigQueryExtension.base, |
||
553 | #if defined(RADEON_R100) |
||
554 | &radeonTexBufferExtension.base, |
||
555 | #elif defined(RADEON_R200) |
||
556 | &r200TexBufferExtension.base, |
||
557 | #endif |
||
558 | &radeonFlushExtension.base, |
||
559 | &radeonImageExtension.base, |
||
560 | &radeonRendererQueryExtension.base, |
||
561 | NULL |
||
562 | }; |
||
563 | |||
564 | static radeonScreenPtr |
||
565 | radeonCreateScreen2(__DRIscreen *sPriv) |
||
566 | { |
||
567 | radeonScreenPtr screen; |
||
568 | int ret; |
||
569 | uint32_t device_id = 0; |
||
570 | |||
571 | /* Allocate the private area */ |
||
572 | screen = calloc(1, sizeof(*screen)); |
||
573 | if ( !screen ) { |
||
574 | fprintf(stderr, "%s: Could not allocate memory for screen structure", __func__); |
||
575 | fprintf(stderr, "leaving here\n"); |
||
576 | return NULL; |
||
577 | } |
||
578 | |||
579 | radeon_init_debug(); |
||
580 | |||
581 | /* parse information in __driConfigOptions */ |
||
582 | driParseOptionInfo (&screen->optionCache, radeon_config_options.xml); |
||
583 | |||
584 | screen->chip_flags = 0; |
||
585 | |||
586 | screen->irq = 1; |
||
587 | |||
588 | ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); |
||
589 | if (ret) { |
||
590 | free( screen ); |
||
591 | fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); |
||
592 | return NULL; |
||
593 | } |
||
594 | |||
595 | ret = radeon_set_screen_flags(screen, device_id); |
||
596 | if (ret == -1) { |
||
597 | free(screen); |
||
598 | return NULL; |
||
599 | } |
||
600 | |||
601 | if (getenv("RADEON_NO_TCL")) |
||
602 | screen->chip_flags &= ~RADEON_CHIPSET_TCL; |
||
603 | |||
604 | sPriv->extensions = radeon_screen_extensions; |
||
605 | |||
606 | screen->driScreen = sPriv; |
||
607 | screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); |
||
608 | if (screen->bom == NULL) { |
||
609 | free(screen); |
||
610 | return NULL; |
||
611 | } |
||
612 | return screen; |
||
613 | } |
||
614 | |||
615 | /* Destroy the device specific screen private data struct. |
||
616 | */ |
||
617 | static void |
||
618 | radeonDestroyScreen( __DRIscreen *sPriv ) |
||
619 | { |
||
620 | radeonScreenPtr screen = (radeonScreenPtr)sPriv->driverPrivate; |
||
621 | |||
622 | if (!screen) |
||
623 | return; |
||
624 | |||
625 | #ifdef RADEON_BO_TRACK |
||
626 | radeon_tracker_print(&screen->bom->tracker, stderr); |
||
627 | #endif |
||
628 | radeon_bo_manager_gem_dtor(screen->bom); |
||
629 | |||
630 | /* free all option information */ |
||
631 | driDestroyOptionInfo (&screen->optionCache); |
||
632 | |||
633 | free( screen ); |
||
634 | sPriv->driverPrivate = NULL; |
||
635 | } |
||
636 | |||
637 | |||
638 | /* Initialize the driver specific screen private data. |
||
639 | */ |
||
640 | static GLboolean |
||
641 | radeonInitDriver( __DRIscreen *sPriv ) |
||
642 | { |
||
643 | sPriv->driverPrivate = (void *) radeonCreateScreen2( sPriv ); |
||
644 | if ( !sPriv->driverPrivate ) { |
||
645 | radeonDestroyScreen( sPriv ); |
||
646 | return GL_FALSE; |
||
647 | } |
||
648 | |||
649 | return GL_TRUE; |
||
650 | } |
||
651 | |||
652 | |||
653 | |||
654 | /** |
||
655 | * Create the Mesa framebuffer and renderbuffers for a given window/drawable. |
||
656 | * |
||
657 | * \todo This function (and its interface) will need to be updated to support |
||
658 | * pbuffers. |
||
659 | */ |
||
660 | static GLboolean |
||
661 | radeonCreateBuffer( __DRIscreen *driScrnPriv, |
||
662 | __DRIdrawable *driDrawPriv, |
||
663 | const struct gl_config *mesaVis, |
||
664 | GLboolean isPixmap ) |
||
665 | { |
||
666 | radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->driverPrivate; |
||
667 | |||
668 | const GLboolean swDepth = GL_FALSE; |
||
669 | const GLboolean swAlpha = GL_FALSE; |
||
670 | const GLboolean swAccum = mesaVis->accumRedBits > 0; |
||
671 | const GLboolean swStencil = mesaVis->stencilBits > 0 && |
||
672 | mesaVis->depthBits != 24; |
||
673 | mesa_format rgbFormat; |
||
674 | struct radeon_framebuffer *rfb; |
||
675 | |||
676 | if (isPixmap) |
||
677 | return GL_FALSE; /* not implemented */ |
||
678 | |||
679 | rfb = CALLOC_STRUCT(radeon_framebuffer); |
||
680 | if (!rfb) |
||
681 | return GL_FALSE; |
||
682 | |||
683 | _mesa_initialize_window_framebuffer(&rfb->base, mesaVis); |
||
684 | |||
685 | if (mesaVis->redBits == 5) |
||
686 | rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B5G6R5_UNORM : MESA_FORMAT_R5G6B5_UNORM; |
||
687 | else if (mesaVis->alphaBits == 0) |
||
688 | rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B8G8R8X8_UNORM : MESA_FORMAT_X8R8G8B8_UNORM; |
||
689 | else |
||
690 | rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B8G8R8A8_UNORM : MESA_FORMAT_A8R8G8B8_UNORM; |
||
691 | |||
692 | /* front color renderbuffer */ |
||
693 | rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); |
||
694 | _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base); |
||
695 | rfb->color_rb[0]->has_surface = 1; |
||
696 | |||
697 | /* back color renderbuffer */ |
||
698 | if (mesaVis->doubleBufferMode) { |
||
699 | rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); |
||
700 | _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base); |
||
701 | rfb->color_rb[1]->has_surface = 1; |
||
702 | } |
||
703 | |||
704 | if (mesaVis->depthBits == 24) { |
||
705 | if (mesaVis->stencilBits == 8) { |
||
706 | struct radeon_renderbuffer *depthStencilRb = |
||
707 | radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT, driDrawPriv); |
||
708 | _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base); |
||
709 | _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base.Base); |
||
710 | depthStencilRb->has_surface = screen->depthHasSurface; |
||
711 | } else { |
||
712 | /* depth renderbuffer */ |
||
713 | struct radeon_renderbuffer *depth = |
||
714 | radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT, driDrawPriv); |
||
715 | _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base); |
||
716 | depth->has_surface = screen->depthHasSurface; |
||
717 | } |
||
718 | } else if (mesaVis->depthBits == 16) { |
||
719 | /* just 16-bit depth buffer, no hw stencil */ |
||
720 | struct radeon_renderbuffer *depth = |
||
721 | radeon_create_renderbuffer(MESA_FORMAT_Z_UNORM16, driDrawPriv); |
||
722 | _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base); |
||
723 | depth->has_surface = screen->depthHasSurface; |
||
724 | } |
||
725 | |||
726 | _swrast_add_soft_renderbuffers(&rfb->base, |
||
727 | GL_FALSE, /* color */ |
||
728 | swDepth, |
||
729 | swStencil, |
||
730 | swAccum, |
||
731 | swAlpha, |
||
732 | GL_FALSE /* aux */); |
||
733 | driDrawPriv->driverPrivate = (void *) rfb; |
||
734 | |||
735 | return (driDrawPriv->driverPrivate != NULL); |
||
736 | } |
||
737 | |||
738 | |||
739 | static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) |
||
740 | { |
||
741 | struct radeon_renderbuffer *rb; |
||
742 | |||
743 | rb = rfb->color_rb[0]; |
||
744 | if (rb && rb->bo) { |
||
745 | radeon_bo_unref(rb->bo); |
||
746 | rb->bo = NULL; |
||
747 | } |
||
748 | rb = rfb->color_rb[1]; |
||
749 | if (rb && rb->bo) { |
||
750 | radeon_bo_unref(rb->bo); |
||
751 | rb->bo = NULL; |
||
752 | } |
||
753 | rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); |
||
754 | if (rb && rb->bo) { |
||
755 | radeon_bo_unref(rb->bo); |
||
756 | rb->bo = NULL; |
||
757 | } |
||
758 | } |
||
759 | |||
760 | void |
||
761 | radeonDestroyBuffer(__DRIdrawable *driDrawPriv) |
||
762 | { |
||
763 | struct radeon_framebuffer *rfb; |
||
764 | if (!driDrawPriv) |
||
765 | return; |
||
766 | |||
767 | rfb = (void*)driDrawPriv->driverPrivate; |
||
768 | if (!rfb) |
||
769 | return; |
||
770 | radeon_cleanup_renderbuffers(rfb); |
||
771 | _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL); |
||
772 | } |
||
773 | |||
774 | /** |
||
775 | * This is the driver specific part of the createNewScreen entry point. |
||
776 | * Called when using DRI2. |
||
777 | * |
||
778 | * \return the struct gl_config supported by this driver |
||
779 | */ |
||
780 | static const |
||
781 | __DRIconfig **radeonInitScreen2(__DRIscreen *psp) |
||
782 | { |
||
783 | static const mesa_format formats[3] = { |
||
784 | MESA_FORMAT_B5G6R5_UNORM, |
||
785 | MESA_FORMAT_B8G8R8X8_UNORM, |
||
786 | MESA_FORMAT_B8G8R8A8_UNORM |
||
787 | }; |
||
788 | /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't |
||
789 | * support pageflipping at all. |
||
790 | */ |
||
791 | static const GLenum back_buffer_modes[] = { |
||
792 | GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ |
||
793 | }; |
||
794 | uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; |
||
795 | int color; |
||
796 | __DRIconfig **configs = NULL; |
||
797 | |||
798 | psp->max_gl_compat_version = 13; |
||
799 | psp->max_gl_es1_version = 11; |
||
800 | |||
801 | if (!radeonInitDriver(psp)) { |
||
802 | return NULL; |
||
803 | } |
||
804 | depth_bits[0] = 0; |
||
805 | stencil_bits[0] = 0; |
||
806 | depth_bits[1] = 16; |
||
807 | stencil_bits[1] = 0; |
||
808 | depth_bits[2] = 24; |
||
809 | stencil_bits[2] = 0; |
||
810 | depth_bits[3] = 24; |
||
811 | stencil_bits[3] = 8; |
||
812 | |||
813 | msaa_samples_array[0] = 0; |
||
814 | |||
815 | for (color = 0; color < ARRAY_SIZE(formats); color++) { |
||
816 | __DRIconfig **new_configs; |
||
817 | |||
818 | new_configs = driCreateConfigs(formats[color], |
||
819 | depth_bits, |
||
820 | stencil_bits, |
||
821 | ARRAY_SIZE(depth_bits), |
||
822 | back_buffer_modes, |
||
823 | ARRAY_SIZE(back_buffer_modes), |
||
824 | msaa_samples_array, |
||
825 | ARRAY_SIZE(msaa_samples_array), |
||
826 | GL_TRUE); |
||
827 | configs = driConcatConfigs(configs, new_configs); |
||
828 | } |
||
829 | |||
830 | if (configs == NULL) { |
||
831 | fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, |
||
832 | __LINE__); |
||
833 | return NULL; |
||
834 | } |
||
835 | |||
836 | return (const __DRIconfig **)configs; |
||
837 | } |
||
838 | |||
839 | static const struct __DriverAPIRec radeon_driver_api = { |
||
840 | .InitScreen = radeonInitScreen2, |
||
841 | .DestroyScreen = radeonDestroyScreen, |
||
842 | #if defined(RADEON_R200) |
||
843 | .CreateContext = r200CreateContext, |
||
844 | .DestroyContext = r200DestroyContext, |
||
845 | #else |
||
846 | .CreateContext = r100CreateContext, |
||
847 | .DestroyContext = radeonDestroyContext, |
||
848 | #endif |
||
849 | .CreateBuffer = radeonCreateBuffer, |
||
850 | .DestroyBuffer = radeonDestroyBuffer, |
||
851 | .MakeCurrent = radeonMakeCurrent, |
||
852 | .UnbindContext = radeonUnbindContext, |
||
853 | }; |
||
854 | |||
855 | static const struct __DRIDriverVtableExtensionRec radeon_vtable = { |
||
856 | .base = { __DRI_DRIVER_VTABLE, 1 }, |
||
857 | .vtable = &radeon_driver_api, |
||
858 | }; |
||
859 | |||
860 | /* This is the table of extensions that the loader will dlsym() for. */ |
||
861 | static const __DRIextension *radeon_driver_extensions[] = { |
||
862 | &driCoreExtension.base, |
||
863 | &driDRI2Extension.base, |
||
864 | &radeon_config_options.base, |
||
865 | &radeon_vtable.base, |
||
866 | NULL |
||
867 | }; |
||
868 | |||
869 | #ifdef RADEON_R200 |
||
870 | PUBLIC const __DRIextension **__driDriverGetExtensions_r200(void) |
||
871 | { |
||
872 | globalDriverAPI = &radeon_driver_api; |
||
873 | |||
874 | return radeon_driver_extensions; |
||
875 | } |
||
876 | #else |
||
877 | PUBLIC const __DRIextension **__driDriverGetExtensions_radeon(void) |
||
878 | { |
||
879 | globalDriverAPI = &radeon_driver_api; |
||
880 | |||
881 | return radeon_driver_extensions; |
||
882 | } |
||
883 | #endif> |