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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5564 | serge | 1 | /************************************************************************** |
| 2 | |||
| 3 | Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and |
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| 4 | VMware, Inc. |
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| 5 | |||
| 6 | All Rights Reserved. |
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| 7 | |||
| 8 | Permission is hereby granted, free of charge, to any person obtaining |
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| 9 | a copy of this software and associated documentation files (the |
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| 10 | "Software"), to deal in the Software without restriction, including |
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| 11 | without limitation the rights to use, copy, modify, merge, publish, |
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| 12 | distribute, sublicense, and/or sell copies of the Software, and to |
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| 13 | permit persons to whom the Software is furnished to do so, subject to |
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| 14 | the following conditions: |
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| 15 | |||
| 16 | The above copyright notice and this permission notice (including the |
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| 17 | next paragraph) shall be included in all copies or substantial |
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| 18 | portions of the Software. |
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| 19 | |||
| 20 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 21 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 22 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 23 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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| 24 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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| 25 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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| 26 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 27 | |||
| 28 | **************************************************************************/ |
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| 29 | |||
| 30 | /* |
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| 31 | * Authors: |
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| 32 | * Keith Whitwell |
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| 33 | */ |
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| 34 | |||
| 35 | #include "main/glheader.h" |
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| 36 | #include "main/imports.h" |
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| 37 | #include "main/mtypes.h" |
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| 38 | #include "main/state.h" |
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| 39 | |||
| 40 | #include "vbo/vbo.h" |
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| 41 | #include "math/m_translate.h" |
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| 42 | #include "tnl/tnl.h" |
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| 43 | #include "tnl/t_pipeline.h" |
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| 44 | #include "radeon_context.h" |
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| 45 | #include "radeon_state.h" |
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| 46 | #include "radeon_ioctl.h" |
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| 47 | #include "radeon_tex.h" |
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| 48 | #include "radeon_tcl.h" |
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| 49 | #include "radeon_swtcl.h" |
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| 50 | #include "radeon_maos.h" |
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| 51 | #include "radeon_fog.h" |
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| 52 | |||
| 53 | #define RADEON_TCL_MAX_SETUP 19 |
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| 54 | |||
| 55 | union emit_union { float f; GLuint ui; radeon_color_t rgba; }; |
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| 56 | |||
| 57 | static struct { |
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| 58 | void (*emit)( struct gl_context *, GLuint, GLuint, void * ); |
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| 59 | GLuint vertex_size; |
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| 60 | GLuint vertex_format; |
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| 61 | } setup_tab[RADEON_TCL_MAX_SETUP]; |
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| 62 | |||
| 63 | #define DO_W (IND & RADEON_CP_VC_FRMT_W0) |
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| 64 | #define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR) |
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| 65 | #define DO_SPEC_OR_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC) |
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| 66 | #define DO_SPEC ((IND & RADEON_CP_VC_FRMT_PKSPEC) && \ |
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| 67 | _mesa_need_secondary_color(ctx)) |
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| 68 | #define DO_FOG ((IND & RADEON_CP_VC_FRMT_PKSPEC) && ctx->Fog.Enabled && \ |
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| 69 | (ctx->Fog.FogCoordinateSource == GL_FOG_COORD)) |
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| 70 | #define DO_TEX0 ((IND & RADEON_CP_VC_FRMT_ST0) != 0) |
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| 71 | #define DO_TEX1 ((IND & RADEON_CP_VC_FRMT_ST1) != 0) |
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| 72 | #define DO_TEX2 ((IND & RADEON_CP_VC_FRMT_ST2) != 0) |
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| 73 | #define DO_PTEX ((IND & RADEON_CP_VC_FRMT_Q0) != 0) |
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| 74 | #define DO_NORM ((IND & RADEON_CP_VC_FRMT_N0) != 0) |
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| 75 | |||
| 76 | #define DO_TEX3 0 |
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| 77 | |||
| 78 | #define GET_TEXSOURCE(n) n |
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| 79 | |||
| 80 | /*********************************************************************** |
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| 81 | * Generate vertex emit functions * |
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| 82 | ***********************************************************************/ |
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| 83 | |||
| 84 | |||
| 85 | /* Defined in order of increasing vertex size: |
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| 86 | */ |
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| 87 | #define IDX 0 |
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| 88 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 89 | RADEON_CP_VC_FRMT_Z| \ |
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| 90 | RADEON_CP_VC_FRMT_PKCOLOR) |
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| 91 | #define TAG(x) x##_rgba |
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| 92 | #include "radeon_maos_vbtmp.h" |
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| 93 | |||
| 94 | #define IDX 1 |
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| 95 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 96 | RADEON_CP_VC_FRMT_Z| \ |
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| 97 | RADEON_CP_VC_FRMT_N0) |
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| 98 | #define TAG(x) x##_n |
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| 99 | #include "radeon_maos_vbtmp.h" |
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| 100 | |||
| 101 | #define IDX 2 |
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| 102 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 103 | RADEON_CP_VC_FRMT_Z| \ |
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| 104 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 105 | RADEON_CP_VC_FRMT_ST0) |
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| 106 | #define TAG(x) x##_rgba_st |
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| 107 | #include "radeon_maos_vbtmp.h" |
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| 108 | |||
| 109 | #define IDX 3 |
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| 110 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 111 | RADEON_CP_VC_FRMT_Z| \ |
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| 112 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 113 | RADEON_CP_VC_FRMT_N0) |
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| 114 | #define TAG(x) x##_rgba_n |
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| 115 | #include "radeon_maos_vbtmp.h" |
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| 116 | |||
| 117 | #define IDX 4 |
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| 118 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 119 | RADEON_CP_VC_FRMT_Z| \ |
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| 120 | RADEON_CP_VC_FRMT_ST0| \ |
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| 121 | RADEON_CP_VC_FRMT_N0) |
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| 122 | #define TAG(x) x##_st_n |
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| 123 | #include "radeon_maos_vbtmp.h" |
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| 124 | |||
| 125 | #define IDX 5 |
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| 126 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 127 | RADEON_CP_VC_FRMT_Z| \ |
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| 128 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 129 | RADEON_CP_VC_FRMT_ST0| \ |
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| 130 | RADEON_CP_VC_FRMT_ST1) |
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| 131 | #define TAG(x) x##_rgba_st_st |
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| 132 | #include "radeon_maos_vbtmp.h" |
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| 133 | |||
| 134 | #define IDX 6 |
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| 135 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 136 | RADEON_CP_VC_FRMT_Z| \ |
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| 137 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 138 | RADEON_CP_VC_FRMT_ST0| \ |
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| 139 | RADEON_CP_VC_FRMT_N0) |
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| 140 | #define TAG(x) x##_rgba_st_n |
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| 141 | #include "radeon_maos_vbtmp.h" |
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| 142 | |||
| 143 | #define IDX 7 |
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| 144 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 145 | RADEON_CP_VC_FRMT_Z| \ |
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| 146 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 147 | RADEON_CP_VC_FRMT_PKSPEC| \ |
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| 148 | RADEON_CP_VC_FRMT_ST0| \ |
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| 149 | RADEON_CP_VC_FRMT_ST1) |
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| 150 | #define TAG(x) x##_rgba_spec_st_st |
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| 151 | #include "radeon_maos_vbtmp.h" |
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| 152 | |||
| 153 | #define IDX 8 |
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| 154 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 155 | RADEON_CP_VC_FRMT_Z| \ |
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| 156 | RADEON_CP_VC_FRMT_ST0| \ |
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| 157 | RADEON_CP_VC_FRMT_ST1| \ |
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| 158 | RADEON_CP_VC_FRMT_N0) |
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| 159 | #define TAG(x) x##_st_st_n |
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| 160 | #include "radeon_maos_vbtmp.h" |
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| 161 | |||
| 162 | #define IDX 9 |
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| 163 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 164 | RADEON_CP_VC_FRMT_Z| \ |
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| 165 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 166 | RADEON_CP_VC_FRMT_PKSPEC| \ |
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| 167 | RADEON_CP_VC_FRMT_ST0| \ |
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| 168 | RADEON_CP_VC_FRMT_ST1| \ |
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| 169 | RADEON_CP_VC_FRMT_N0) |
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| 170 | #define TAG(x) x##_rgba_spec_st_st_n |
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| 171 | #include "radeon_maos_vbtmp.h" |
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| 172 | |||
| 173 | #define IDX 10 |
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| 174 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 175 | RADEON_CP_VC_FRMT_Z| \ |
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| 176 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 177 | RADEON_CP_VC_FRMT_ST0| \ |
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| 178 | RADEON_CP_VC_FRMT_Q0) |
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| 179 | #define TAG(x) x##_rgba_stq |
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| 180 | #include "radeon_maos_vbtmp.h" |
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| 181 | |||
| 182 | #define IDX 11 |
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| 183 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 184 | RADEON_CP_VC_FRMT_Z| \ |
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| 185 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 186 | RADEON_CP_VC_FRMT_ST1| \ |
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| 187 | RADEON_CP_VC_FRMT_Q1| \ |
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| 188 | RADEON_CP_VC_FRMT_ST0| \ |
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| 189 | RADEON_CP_VC_FRMT_Q0) |
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| 190 | #define TAG(x) x##_rgba_stq_stq |
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| 191 | #include "radeon_maos_vbtmp.h" |
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| 192 | |||
| 193 | #define IDX 12 |
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| 194 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 195 | RADEON_CP_VC_FRMT_Z| \ |
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| 196 | RADEON_CP_VC_FRMT_W0| \ |
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| 197 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 198 | RADEON_CP_VC_FRMT_PKSPEC| \ |
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| 199 | RADEON_CP_VC_FRMT_ST0| \ |
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| 200 | RADEON_CP_VC_FRMT_Q0| \ |
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| 201 | RADEON_CP_VC_FRMT_ST1| \ |
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| 202 | RADEON_CP_VC_FRMT_Q1| \ |
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| 203 | RADEON_CP_VC_FRMT_N0) |
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| 204 | #define TAG(x) x##_w_rgba_spec_stq_stq_n |
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| 205 | #include "radeon_maos_vbtmp.h" |
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| 206 | |||
| 207 | #define IDX 13 |
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| 208 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 209 | RADEON_CP_VC_FRMT_Z| \ |
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| 210 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 211 | RADEON_CP_VC_FRMT_ST0| \ |
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| 212 | RADEON_CP_VC_FRMT_ST1| \ |
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| 213 | RADEON_CP_VC_FRMT_ST2) |
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| 214 | #define TAG(x) x##_rgba_st_st_st |
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| 215 | #include "radeon_maos_vbtmp.h" |
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| 216 | |||
| 217 | #define IDX 14 |
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| 218 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 219 | RADEON_CP_VC_FRMT_Z| \ |
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| 220 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 221 | RADEON_CP_VC_FRMT_PKSPEC| \ |
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| 222 | RADEON_CP_VC_FRMT_ST0| \ |
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| 223 | RADEON_CP_VC_FRMT_ST1| \ |
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| 224 | RADEON_CP_VC_FRMT_ST2) |
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| 225 | #define TAG(x) x##_rgba_spec_st_st_st |
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| 226 | #include "radeon_maos_vbtmp.h" |
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| 227 | |||
| 228 | #define IDX 15 |
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| 229 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 230 | RADEON_CP_VC_FRMT_Z| \ |
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| 231 | RADEON_CP_VC_FRMT_ST0| \ |
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| 232 | RADEON_CP_VC_FRMT_ST1| \ |
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| 233 | RADEON_CP_VC_FRMT_ST2| \ |
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| 234 | RADEON_CP_VC_FRMT_N0) |
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| 235 | #define TAG(x) x##_st_st_st_n |
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| 236 | #include "radeon_maos_vbtmp.h" |
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| 237 | |||
| 238 | #define IDX 16 |
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| 239 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 240 | RADEON_CP_VC_FRMT_Z| \ |
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| 241 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 242 | RADEON_CP_VC_FRMT_PKSPEC| \ |
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| 243 | RADEON_CP_VC_FRMT_ST0| \ |
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| 244 | RADEON_CP_VC_FRMT_ST1| \ |
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| 245 | RADEON_CP_VC_FRMT_ST2| \ |
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| 246 | RADEON_CP_VC_FRMT_N0) |
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| 247 | #define TAG(x) x##_rgba_spec_st_st_st_n |
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| 248 | #include "radeon_maos_vbtmp.h" |
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| 249 | |||
| 250 | #define IDX 17 |
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| 251 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 252 | RADEON_CP_VC_FRMT_Z| \ |
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| 253 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 254 | RADEON_CP_VC_FRMT_ST0| \ |
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| 255 | RADEON_CP_VC_FRMT_Q0| \ |
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| 256 | RADEON_CP_VC_FRMT_ST1| \ |
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| 257 | RADEON_CP_VC_FRMT_Q1| \ |
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| 258 | RADEON_CP_VC_FRMT_ST2| \ |
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| 259 | RADEON_CP_VC_FRMT_Q2) |
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| 260 | #define TAG(x) x##_rgba_stq_stq_stq |
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| 261 | #include "radeon_maos_vbtmp.h" |
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| 262 | |||
| 263 | #define IDX 18 |
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| 264 | #define IND (RADEON_CP_VC_FRMT_XY| \ |
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| 265 | RADEON_CP_VC_FRMT_Z| \ |
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| 266 | RADEON_CP_VC_FRMT_W0| \ |
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| 267 | RADEON_CP_VC_FRMT_PKCOLOR| \ |
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| 268 | RADEON_CP_VC_FRMT_PKSPEC| \ |
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| 269 | RADEON_CP_VC_FRMT_ST0| \ |
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| 270 | RADEON_CP_VC_FRMT_Q0| \ |
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| 271 | RADEON_CP_VC_FRMT_ST1| \ |
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| 272 | RADEON_CP_VC_FRMT_Q1| \ |
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| 273 | RADEON_CP_VC_FRMT_ST2| \ |
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| 274 | RADEON_CP_VC_FRMT_Q2| \ |
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| 275 | RADEON_CP_VC_FRMT_N0) |
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| 276 | #define TAG(x) x##_w_rgba_spec_stq_stq_stq_n |
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| 277 | #include "radeon_maos_vbtmp.h" |
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| 278 | |||
| 279 | |||
| 280 | |||
| 281 | |||
| 282 | /*********************************************************************** |
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| 283 | * Initialization |
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| 284 | ***********************************************************************/ |
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| 285 | |||
| 286 | |||
| 287 | static void init_tcl_verts( void ) |
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| 288 | { |
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| 289 | init_rgba(); |
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| 290 | init_n(); |
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| 291 | init_rgba_n(); |
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| 292 | init_rgba_st(); |
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| 293 | init_st_n(); |
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| 294 | init_rgba_st_st(); |
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| 295 | init_rgba_st_n(); |
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| 296 | init_rgba_spec_st_st(); |
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| 297 | init_st_st_n(); |
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| 298 | init_rgba_spec_st_st_n(); |
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| 299 | init_rgba_stq(); |
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| 300 | init_rgba_stq_stq(); |
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| 301 | init_w_rgba_spec_stq_stq_n(); |
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| 302 | init_rgba_st_st_st(); |
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| 303 | init_rgba_spec_st_st_st(); |
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| 304 | init_st_st_st_n(); |
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| 305 | init_rgba_spec_st_st_st_n(); |
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| 306 | init_rgba_stq_stq_stq(); |
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| 307 | init_w_rgba_spec_stq_stq_stq_n(); |
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| 308 | } |
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| 309 | |||
| 310 | |||
| 311 | void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) |
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| 312 | { |
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| 313 | r100ContextPtr rmesa = R100_CONTEXT(ctx); |
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| 314 | struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; |
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| 315 | GLuint req = 0; |
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| 316 | GLuint unit; |
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| 317 | GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & |
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| 318 | ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2)); |
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| 319 | int i; |
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| 320 | static int firsttime = 1; |
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| 321 | |||
| 322 | if (firsttime) { |
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| 323 | init_tcl_verts(); |
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| 324 | firsttime = 0; |
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| 325 | } |
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| 326 | |||
| 327 | if (1) { |
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| 328 | req |= RADEON_CP_VC_FRMT_Z; |
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| 329 | if (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 4) { |
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| 330 | req |= RADEON_CP_VC_FRMT_W0; |
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| 331 | } |
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| 332 | } |
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| 333 | |||
| 334 | if (inputs & VERT_BIT_NORMAL) { |
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| 335 | req |= RADEON_CP_VC_FRMT_N0; |
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| 336 | } |
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| 337 | |||
| 338 | if (inputs & VERT_BIT_COLOR0) { |
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| 339 | req |= RADEON_CP_VC_FRMT_PKCOLOR; |
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| 340 | } |
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| 341 | |||
| 342 | if (inputs & (VERT_BIT_COLOR1|VERT_BIT_FOG)) { |
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| 343 | req |= RADEON_CP_VC_FRMT_PKSPEC; |
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| 344 | } |
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| 345 | |||
| 346 | for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) { |
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| 347 | if (inputs & VERT_BIT_TEX(unit)) { |
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| 348 | req |= RADEON_ST_BIT(unit); |
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| 349 | /* assume we need the 3rd coord if texgen is active for r/q OR at least |
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| 350 | 3 coords are submitted. This may not be 100% correct */ |
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| 351 | if (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) { |
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| 352 | req |= RADEON_Q_BIT(unit); |
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| 353 | vtx |= RADEON_Q_BIT(unit); |
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| 354 | } |
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| 355 | if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) |
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| 356 | vtx |= RADEON_Q_BIT(unit); |
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| 357 | else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) && |
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| 358 | (!ctx->Texture.Unit[unit]._Current || |
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| 359 | ctx->Texture.Unit[unit]._Current->Target != GL_TEXTURE_CUBE_MAP)) { |
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| 360 | GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3); |
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| 361 | if (((rmesa->NeedTexMatrix >> unit) & 1) && |
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| 362 | (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) |
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| 363 | radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; |
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| 364 | } |
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| 365 | } |
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| 366 | } |
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| 367 | |||
| 368 | if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { |
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| 369 | RADEON_STATECHANGE( rmesa, tcl ); |
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| 370 | rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; |
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| 371 | } |
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| 372 | |||
| 373 | for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++) |
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| 374 | if ((setup_tab[i].vertex_format & req) == req) |
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| 375 | break; |
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| 376 | |||
| 377 | if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && |
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| 378 | rmesa->radeon.tcl.aos[0].bo) |
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| 379 | return; |
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| 380 | |||
| 381 | if (rmesa->radeon.tcl.aos[0].bo) |
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| 382 | radeonReleaseArrays( ctx, ~0 ); |
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| 383 | |||
| 384 | radeonAllocDmaRegion( &rmesa->radeon, |
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| 385 | &rmesa->radeon.tcl.aos[0].bo, |
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| 386 | &rmesa->radeon.tcl.aos[0].offset, |
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| 387 | VB->Count * setup_tab[i].vertex_size * 4, |
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| 388 | 4); |
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| 389 | |||
| 390 | /* The vertex code expects Obj to be clean to element 3. To fix |
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| 391 | * this, add more vertex code (for obj-2, obj-3) or preferably move |
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| 392 | * to maos. |
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| 393 | */ |
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| 394 | if (VB->AttribPtr[_TNL_ATTRIB_POS]->size < 3 || |
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| 395 | (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 3 && |
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| 396 | (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) { |
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| 397 | |||
| 398 | _math_trans_4f( rmesa->tcl.ObjClean.data, |
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| 399 | VB->AttribPtr[_TNL_ATTRIB_POS]->data, |
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| 400 | VB->AttribPtr[_TNL_ATTRIB_POS]->stride, |
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| 401 | GL_FLOAT, |
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| 402 | VB->AttribPtr[_TNL_ATTRIB_POS]->size, |
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| 403 | 0, |
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| 404 | VB->Count ); |
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| 405 | |||
| 406 | switch (VB->AttribPtr[_TNL_ATTRIB_POS]->size) { |
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| 407 | case 1: |
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| 408 | _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1); |
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| 409 | case 2: |
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| 410 | _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2); |
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| 411 | case 3: |
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| 412 | if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) { |
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| 413 | _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3); |
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| 414 | } |
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| 415 | case 4: |
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| 416 | default: |
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| 417 | break; |
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| 418 | } |
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| 419 | |||
| 420 | VB->AttribPtr[_TNL_ATTRIB_POS] = &rmesa->tcl.ObjClean; |
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| 421 | } |
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| 422 | |||
| 423 | |||
| 424 | radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1); |
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| 425 | setup_tab[i].emit( ctx, 0, VB->Count, |
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| 426 | rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset); |
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| 427 | radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo); |
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| 428 | // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size; |
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| 429 | rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size; |
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| 430 | rmesa->tcl.vertex_format = setup_tab[i].vertex_format; |
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| 431 | rmesa->radeon.tcl.aos_count = 1; |
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| 432 | } |
||
| 433 |