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/*

 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and

 *                VA Linux Systems Inc., Fremont, California.

 *

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining

 * a copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation on the rights to use, copy, modify, merge,

 * publish, distribute, sublicense, and/or sell copies of the Software,

 * and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial

 * portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR

 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */

/*

 * Authors:

 *   Kevin E. Martin 

 *   Rickard E. Faith 

 *   Alan Hourihane 

 *

 * References:

 *

 * !!!! FIXME !!!!

 *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical

 *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April

 *   1999.

 *

 * !!!! FIXME !!!!

 *   RAGE 128 Software Development Manual (Technical Reference Manual P/N

 *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.

 *

 */

/* !!!! FIXME !!!!  NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h

 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT

 * ON THE RADEON.  A FULL AUDIT OF THIS CODE IS NEEDED!  */

#ifndef _RADEON_REG_H_

#define _RADEON_REG_H_

				/* Registers for 2D/Video/Overlay */

#define RADEON_ADAPTER_ID                   0x0f2c /* PCI */

#define RADEON_AGP_BASE                     0x0170

#define RADEON_AGP_CNTL                     0x0174

#       define RADEON_AGP_APER_SIZE_256MB   (0x00 << 0)

#       define RADEON_AGP_APER_SIZE_128MB   (0x20 << 0)

#       define RADEON_AGP_APER_SIZE_64MB    (0x30 << 0)

#       define RADEON_AGP_APER_SIZE_32MB    (0x38 << 0)

#       define RADEON_AGP_APER_SIZE_16MB    (0x3c << 0)

#       define RADEON_AGP_APER_SIZE_8MB     (0x3e << 0)

#       define RADEON_AGP_APER_SIZE_4MB     (0x3f << 0)

#       define RADEON_AGP_APER_SIZE_MASK    (0x3f << 0)

#define RADEON_AGP_COMMAND                  0x0f60 /* PCI */

#define RADEON_AGP_COMMAND_PCI_CONFIG       0x0060 /* offset in PCI config*/

#       define RADEON_AGP_ENABLE            (1<<8)

#define RADEON_AGP_PLL_CNTL                 0x000b /* PLL */

#define RADEON_AGP_STATUS                   0x0f5c /* PCI */

#       define RADEON_AGP_1X_MODE           0x01

#       define RADEON_AGP_2X_MODE           0x02

#       define RADEON_AGP_4X_MODE           0x04

#       define RADEON_AGP_FW_MODE           0x10

#       define RADEON_AGP_MODE_MASK         0x17

#define RADEON_ATTRDR                       0x03c1 /* VGA */

#define RADEON_ATTRDW                       0x03c0 /* VGA */

#define RADEON_ATTRX                        0x03c0 /* VGA */

#define RADEON_AUX_SC_CNTL                  0x1660

#       define RADEON_AUX1_SC_EN            (1 << 0)

#       define RADEON_AUX1_SC_MODE_OR       (0 << 1)

#       define RADEON_AUX1_SC_MODE_NAND     (1 << 1)

#       define RADEON_AUX2_SC_EN            (1 << 2)

#       define RADEON_AUX2_SC_MODE_OR       (0 << 3)

#       define RADEON_AUX2_SC_MODE_NAND     (1 << 3)

#       define RADEON_AUX3_SC_EN            (1 << 4)

#       define RADEON_AUX3_SC_MODE_OR       (0 << 5)

#       define RADEON_AUX3_SC_MODE_NAND     (1 << 5)

#define RADEON_AUX1_SC_BOTTOM               0x1670

#define RADEON_AUX1_SC_LEFT                 0x1664

#define RADEON_AUX1_SC_RIGHT                0x1668

#define RADEON_AUX1_SC_TOP                  0x166c

#define RADEON_AUX2_SC_BOTTOM               0x1680

#define RADEON_AUX2_SC_LEFT                 0x1674

#define RADEON_AUX2_SC_RIGHT                0x1678

#define RADEON_AUX2_SC_TOP                  0x167c

#define RADEON_AUX3_SC_BOTTOM               0x1690

#define RADEON_AUX3_SC_LEFT                 0x1684

#define RADEON_AUX3_SC_RIGHT                0x1688

#define RADEON_AUX3_SC_TOP                  0x168c

#define RADEON_AUX_WINDOW_HORZ_CNTL         0x02d8

#define RADEON_AUX_WINDOW_VERT_CNTL         0x02dc

#define RADEON_BASE_CODE                    0x0f0b

#define RADEON_BIOS_0_SCRATCH               0x0010

#define RADEON_BIOS_1_SCRATCH               0x0014

#define RADEON_BIOS_2_SCRATCH               0x0018

#define RADEON_BIOS_3_SCRATCH               0x001c

#define RADEON_BIOS_4_SCRATCH               0x0020

#define RADEON_BIOS_5_SCRATCH               0x0024

#define RADEON_BIOS_6_SCRATCH               0x0028

#define RADEON_BIOS_7_SCRATCH               0x002c

#define RADEON_BIOS_ROM                     0x0f30 /* PCI */

#define RADEON_BIST                         0x0f0f /* PCI */

#define RADEON_BRUSH_DATA0                  0x1480

#define RADEON_BRUSH_DATA1                  0x1484

#define RADEON_BRUSH_DATA10                 0x14a8

#define RADEON_BRUSH_DATA11                 0x14ac

#define RADEON_BRUSH_DATA12                 0x14b0

#define RADEON_BRUSH_DATA13                 0x14b4

#define RADEON_BRUSH_DATA14                 0x14b8

#define RADEON_BRUSH_DATA15                 0x14bc

#define RADEON_BRUSH_DATA16                 0x14c0

#define RADEON_BRUSH_DATA17                 0x14c4

#define RADEON_BRUSH_DATA18                 0x14c8

#define RADEON_BRUSH_DATA19                 0x14cc

#define RADEON_BRUSH_DATA2                  0x1488

#define RADEON_BRUSH_DATA20                 0x14d0

#define RADEON_BRUSH_DATA21                 0x14d4

#define RADEON_BRUSH_DATA22                 0x14d8

#define RADEON_BRUSH_DATA23                 0x14dc

#define RADEON_BRUSH_DATA24                 0x14e0

#define RADEON_BRUSH_DATA25                 0x14e4

#define RADEON_BRUSH_DATA26                 0x14e8

#define RADEON_BRUSH_DATA27                 0x14ec

#define RADEON_BRUSH_DATA28                 0x14f0

#define RADEON_BRUSH_DATA29                 0x14f4

#define RADEON_BRUSH_DATA3                  0x148c

#define RADEON_BRUSH_DATA30                 0x14f8

#define RADEON_BRUSH_DATA31                 0x14fc

#define RADEON_BRUSH_DATA32                 0x1500

#define RADEON_BRUSH_DATA33                 0x1504

#define RADEON_BRUSH_DATA34                 0x1508

#define RADEON_BRUSH_DATA35                 0x150c

#define RADEON_BRUSH_DATA36                 0x1510

#define RADEON_BRUSH_DATA37                 0x1514

#define RADEON_BRUSH_DATA38                 0x1518

#define RADEON_BRUSH_DATA39                 0x151c

#define RADEON_BRUSH_DATA4                  0x1490

#define RADEON_BRUSH_DATA40                 0x1520

#define RADEON_BRUSH_DATA41                 0x1524

#define RADEON_BRUSH_DATA42                 0x1528

#define RADEON_BRUSH_DATA43                 0x152c

#define RADEON_BRUSH_DATA44                 0x1530

#define RADEON_BRUSH_DATA45                 0x1534

#define RADEON_BRUSH_DATA46                 0x1538

#define RADEON_BRUSH_DATA47                 0x153c

#define RADEON_BRUSH_DATA48                 0x1540

#define RADEON_BRUSH_DATA49                 0x1544

#define RADEON_BRUSH_DATA5                  0x1494

#define RADEON_BRUSH_DATA50                 0x1548

#define RADEON_BRUSH_DATA51                 0x154c

#define RADEON_BRUSH_DATA52                 0x1550

#define RADEON_BRUSH_DATA53                 0x1554

#define RADEON_BRUSH_DATA54                 0x1558

#define RADEON_BRUSH_DATA55                 0x155c

#define RADEON_BRUSH_DATA56                 0x1560

#define RADEON_BRUSH_DATA57                 0x1564

#define RADEON_BRUSH_DATA58                 0x1568

#define RADEON_BRUSH_DATA59                 0x156c

#define RADEON_BRUSH_DATA6                  0x1498

#define RADEON_BRUSH_DATA60                 0x1570

#define RADEON_BRUSH_DATA61                 0x1574

#define RADEON_BRUSH_DATA62                 0x1578

#define RADEON_BRUSH_DATA63                 0x157c

#define RADEON_BRUSH_DATA7                  0x149c

#define RADEON_BRUSH_DATA8                  0x14a0

#define RADEON_BRUSH_DATA9                  0x14a4

#define RADEON_BRUSH_SCALE                  0x1470

#define RADEON_BRUSH_Y_X                    0x1474

#define RADEON_BUS_CNTL                     0x0030

#       define RADEON_BUS_MASTER_DIS         (1 << 6)

#       define RADEON_BUS_RD_DISCARD_EN      (1 << 24)

#       define RADEON_BUS_RD_ABORT_EN        (1 << 25)

#       define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)

#       define RADEON_BUS_WRT_BURST          (1 << 29)

#       define RADEON_BUS_READ_BURST         (1 << 30)

#define RADEON_BUS_CNTL1                    0x0034

#       define RADEON_BUS_WAIT_ON_LOCK_EN    (1 << 4)

#define RADEON_CACHE_CNTL                   0x1724

#define RADEON_CACHE_LINE                   0x0f0c /* PCI */

#define RADEON_CAP0_TRIG_CNTL               0x0950 /* ? */

#define RADEON_CAP1_TRIG_CNTL               0x09c0 /* ? */

#define RADEON_CAPABILITIES_ID              0x0f50 /* PCI */

#define RADEON_CAPABILITIES_PTR             0x0f34 /* PCI */

#define RADEON_CLK_PIN_CNTL                 0x0001 /* PLL */

#define RADEON_CLOCK_CNTL_DATA              0x000c

#define RADEON_CLOCK_CNTL_INDEX             0x0008

#       define RADEON_PLL_WR_EN             (1 << 7)

#       define RADEON_PLL_DIV_SEL           (3 << 8)

#       define RADEON_PLL2_DIV_SEL_MASK     ~(3 << 8)

#define RADEON_CLR_CMP_CLR_3D               0x1a24

#define RADEON_CLR_CMP_CLR_DST              0x15c8

#define RADEON_CLR_CMP_CLR_SRC              0x15c4

#define RADEON_CLR_CMP_CNTL                 0x15c0

#       define RADEON_SRC_CMP_EQ_COLOR      (4 <<  0)

#       define RADEON_SRC_CMP_NEQ_COLOR     (5 <<  0)

#       define RADEON_CLR_CMP_SRC_SOURCE    (1 << 24)

#define RADEON_CLR_CMP_MASK                 0x15cc

#       define RADEON_CLR_CMP_MSK           0xffffffff

#define RADEON_CLR_CMP_MASK_3D              0x1A28

#define RADEON_COMMAND                      0x0f04 /* PCI */

#define RADEON_COMPOSITE_SHADOW_ID          0x1a0c

#define RADEON_CONFIG_APER_0_BASE           0x0100

#define RADEON_CONFIG_APER_1_BASE           0x0104

#define RADEON_CONFIG_APER_SIZE             0x0108

#define RADEON_CONFIG_BONDS                 0x00e8

#define RADEON_CONFIG_CNTL                  0x00e0

#       define RADEON_CFG_ATI_REV_A11       (0   << 16)

#       define RADEON_CFG_ATI_REV_A12       (1   << 16)

#       define RADEON_CFG_ATI_REV_A13       (2   << 16)

#       define RADEON_CFG_ATI_REV_ID_MASK   (0xf << 16)

#define RADEON_CONFIG_MEMSIZE               0x00f8

#define RADEON_CONFIG_MEMSIZE_EMBEDDED      0x0114

#define RADEON_CONFIG_REG_1_BASE            0x010c

#define RADEON_CONFIG_REG_APER_SIZE         0x0110

#define RADEON_CONFIG_XSTRAP                0x00e4

#define RADEON_CONSTANT_COLOR_C             0x1d34

#       define RADEON_CONSTANT_COLOR_MASK   0x00ffffff

#       define RADEON_CONSTANT_COLOR_ONE    0x00ffffff

#       define RADEON_CONSTANT_COLOR_ZERO   0x00000000

#define RADEON_CRC_CMDFIFO_ADDR             0x0740

#define RADEON_CRC_CMDFIFO_DOUT             0x0744

#define RADEON_GRPH_BUFFER_CNTL             0x02f0

#       define RADEON_GRPH_START_REQ_MASK          (0x7f)

#       define RADEON_GRPH_START_REQ_SHIFT         0

#       define RADEON_GRPH_STOP_REQ_MASK           (0x7f<<8)

#       define RADEON_GRPH_STOP_REQ_SHIFT          8

#       define RADEON_GRPH_CRITICAL_POINT_MASK     (0x7f<<16)

#       define RADEON_GRPH_CRITICAL_POINT_SHIFT    16

#       define RADEON_GRPH_CRITICAL_CNTL           (1<<28)

#       define RADEON_GRPH_BUFFER_SIZE             (1<<29)

#       define RADEON_GRPH_CRITICAL_AT_SOF         (1<<30)

#       define RADEON_GRPH_STOP_CNTL               (1<<31)

#define RADEON_GRPH2_BUFFER_CNTL            0x03f0

#       define RADEON_GRPH2_START_REQ_MASK         (0x7f)

#       define RADEON_GRPH2_START_REQ_SHIFT         0

#       define RADEON_GRPH2_STOP_REQ_MASK          (0x7f<<8)

#       define RADEON_GRPH2_STOP_REQ_SHIFT         8

#       define RADEON_GRPH2_CRITICAL_POINT_MASK    (0x7f<<16)

#       define RADEON_GRPH2_CRITICAL_POINT_SHIFT   16

#       define RADEON_GRPH2_CRITICAL_CNTL          (1<<28)

#       define RADEON_GRPH2_BUFFER_SIZE            (1<<29)

#       define RADEON_GRPH2_CRITICAL_AT_SOF        (1<<30)

#       define RADEON_GRPH2_STOP_CNTL              (1<<31)

#define RADEON_CRTC_CRNT_FRAME              0x0214

#define RADEON_CRTC_EXT_CNTL                0x0054

#       define RADEON_CRTC_VGA_XOVERSCAN    (1 <<  0)

#       define RADEON_VGA_ATI_LINEAR        (1 <<  3)

#       define RADEON_XCRT_CNT_EN           (1 <<  6)

#       define RADEON_CRTC_HSYNC_DIS        (1 <<  8)

#       define RADEON_CRTC_VSYNC_DIS        (1 <<  9)

#       define RADEON_CRTC_DISPLAY_DIS      (1 << 10)

#       define RADEON_CRTC_SYNC_TRISTAT     (1 << 11)

#       define RADEON_CRTC_CRT_ON           (1 << 15)

#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE      0x0055

#       define RADEON_CRTC_HSYNC_DIS_BYTE   (1 <<  0)

#       define RADEON_CRTC_VSYNC_DIS_BYTE   (1 <<  1)

#       define RADEON_CRTC_DISPLAY_DIS_BYTE (1 <<  2)

#define RADEON_CRTC_GEN_CNTL                0x0050

#       define RADEON_CRTC_DBL_SCAN_EN      (1 <<  0)

#       define RADEON_CRTC_INTERLACE_EN     (1 <<  1)

#       define RADEON_CRTC_CSYNC_EN         (1 <<  4)

#       define RADEON_CRTC_CUR_EN           (1 << 16)

#       define RADEON_CRTC_CUR_MODE_MASK    (7 << 17)

#       define RADEON_CRTC_ICON_EN          (1 << 20)

#       define RADEON_CRTC_EXT_DISP_EN      (1 << 24)

#       define RADEON_CRTC_EN               (1 << 25)

#       define RADEON_CRTC_DISP_REQ_EN_B    (1 << 26)

#define RADEON_CRTC2_GEN_CNTL               0x03f8

#       define RADEON_CRTC2_DBL_SCAN_EN     (1 <<  0)

#       define RADEON_CRTC2_INTERLACE_EN    (1 <<  1)

#       define RADEON_CRTC2_SYNC_TRISTAT    (1 <<  4)

#       define RADEON_CRTC2_HSYNC_TRISTAT   (1 <<  5)

#       define RADEON_CRTC2_VSYNC_TRISTAT   (1 <<  6)

#       define RADEON_CRTC2_CRT2_ON         (1 <<  7)

#       define RADEON_CRTC2_ICON_EN         (1 << 15)

#       define RADEON_CRTC2_CUR_EN          (1 << 16)

#       define RADEON_CRTC2_CUR_MODE_MASK   (7 << 20)

#       define RADEON_CRTC2_DISP_DIS        (1 << 23)

#       define RADEON_CRTC2_EN              (1 << 25)

#       define RADEON_CRTC2_DISP_REQ_EN_B   (1 << 26)

#       define RADEON_CRTC2_CSYNC_EN        (1 << 27)

#       define RADEON_CRTC2_HSYNC_DIS       (1 << 28)

#       define RADEON_CRTC2_VSYNC_DIS       (1 << 29)

#define RADEON_CRTC_MORE_CNTL               0x27c

#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)

#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)

#define RADEON_CRTC_GUI_TRIG_VLINE          0x0218

#define RADEON_CRTC_H_SYNC_STRT_WID         0x0204

#       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)

#       define RADEON_CRTC_H_SYNC_STRT_CHAR       (0x3ff <<  3)

#       define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3

#       define RADEON_CRTC_H_SYNC_WID             (0x3f  << 16)

#       define RADEON_CRTC_H_SYNC_WID_SHIFT       16

#       define RADEON_CRTC_H_SYNC_POL             (1     << 23)

#define RADEON_CRTC2_H_SYNC_STRT_WID        0x0304

#       define RADEON_CRTC2_H_SYNC_STRT_PIX        (0x07  <<  0)

#       define RADEON_CRTC2_H_SYNC_STRT_CHAR       (0x3ff <<  3)

#       define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3

#       define RADEON_CRTC2_H_SYNC_WID             (0x3f  << 16)

#       define RADEON_CRTC2_H_SYNC_WID_SHIFT       16

#       define RADEON_CRTC2_H_SYNC_POL             (1     << 23)

#define RADEON_CRTC_H_TOTAL_DISP            0x0200

#       define RADEON_CRTC_H_TOTAL          (0x03ff << 0)

#       define RADEON_CRTC_H_TOTAL_SHIFT    0

#       define RADEON_CRTC_H_DISP           (0x01ff << 16)

#       define RADEON_CRTC_H_DISP_SHIFT     16

#define RADEON_CRTC2_H_TOTAL_DISP           0x0300

#       define RADEON_CRTC2_H_TOTAL         (0x03ff << 0)

#       define RADEON_CRTC2_H_TOTAL_SHIFT   0

#       define RADEON_CRTC2_H_DISP          (0x01ff << 16)

#       define RADEON_CRTC2_H_DISP_SHIFT    16

#define RADEON_CRTC_OFFSET                  0x0224

#define RADEON_CRTC2_OFFSET                 0x0324

#define RADEON_CRTC_OFFSET_CNTL             0x0228

#       define RADEON_CRTC_TILE_EN          (1 << 15)

#define RADEON_CRTC2_OFFSET_CNTL            0x0328

#       define RADEON_CRTC2_TILE_EN         (1 << 15)

#define RADEON_CRTC_PITCH                   0x022c

#define RADEON_CRTC2_PITCH                  0x032c

#define RADEON_CRTC_STATUS                  0x005c

#       define RADEON_CRTC_VBLANK_SAVE      (1 <<  1)

#       define RADEON_CRTC_VBLANK_SAVE_CLEAR  (1 <<  1)

#define RADEON_CRTC2_STATUS                  0x03fc

#       define RADEON_CRTC2_VBLANK_SAVE      (1 <<  1)

#       define RADEON_CRTC2_VBLANK_SAVE_CLEAR  (1 <<  1)

#define RADEON_CRTC_V_SYNC_STRT_WID         0x020c

#       define RADEON_CRTC_V_SYNC_STRT        (0x7ff <<  0)

#       define RADEON_CRTC_V_SYNC_STRT_SHIFT  0

#       define RADEON_CRTC_V_SYNC_WID         (0x1f  << 16)

#       define RADEON_CRTC_V_SYNC_WID_SHIFT   16

#       define RADEON_CRTC_V_SYNC_POL         (1     << 23)

#define RADEON_CRTC2_V_SYNC_STRT_WID        0x030c

#       define RADEON_CRTC2_V_SYNC_STRT       (0x7ff <<  0)

#       define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0

#       define RADEON_CRTC2_V_SYNC_WID        (0x1f  << 16)

#       define RADEON_CRTC2_V_SYNC_WID_SHIFT  16

#       define RADEON_CRTC2_V_SYNC_POL        (1     << 23)

#define RADEON_CRTC_V_TOTAL_DISP            0x0208

#       define RADEON_CRTC_V_TOTAL          (0x07ff << 0)

#       define RADEON_CRTC_V_TOTAL_SHIFT    0

#       define RADEON_CRTC_V_DISP           (0x07ff << 16)

#       define RADEON_CRTC_V_DISP_SHIFT     16

#define RADEON_CRTC2_V_TOTAL_DISP           0x0308

#       define RADEON_CRTC2_V_TOTAL         (0x07ff << 0)

#       define RADEON_CRTC2_V_TOTAL_SHIFT   0

#       define RADEON_CRTC2_V_DISP          (0x07ff << 16)

#       define RADEON_CRTC2_V_DISP_SHIFT    16

#define RADEON_CRTC_VLINE_CRNT_VLINE        0x0210

#       define RADEON_CRTC_CRNT_VLINE_MASK  (0x7ff << 16)

#define RADEON_CRTC2_CRNT_FRAME             0x0314

#define RADEON_CRTC2_GUI_TRIG_VLINE         0x0318

#define RADEON_CRTC2_STATUS                 0x03fc

#define RADEON_CRTC2_VLINE_CRNT_VLINE       0x0310

#define RADEON_CRTC8_DATA                   0x03d5 /* VGA, 0x3b5 */

#define RADEON_CRTC8_IDX                    0x03d4 /* VGA, 0x3b4 */

#define RADEON_CUR_CLR0                     0x026c

#define RADEON_CUR_CLR1                     0x0270

#define RADEON_CUR_HORZ_VERT_OFF            0x0268

#define RADEON_CUR_HORZ_VERT_POSN           0x0264

#define RADEON_CUR_OFFSET                   0x0260

#       define RADEON_CUR_LOCK              (1 << 31)

#define RADEON_CUR2_CLR0                    0x036c

#define RADEON_CUR2_CLR1                    0x0370

#define RADEON_CUR2_HORZ_VERT_OFF           0x0368

#define RADEON_CUR2_HORZ_VERT_POSN          0x0364

#define RADEON_CUR2_OFFSET                  0x0360

#       define RADEON_CUR2_LOCK             (1 << 31)

#define RADEON_DAC_CNTL                     0x0058

#       define RADEON_DAC_RANGE_CNTL        (3 <<  0)

#       define RADEON_DAC_RANGE_CNTL_MASK   0x03

#       define RADEON_DAC_BLANKING          (1 <<  2)

#       define RADEON_DAC_CMP_EN            (1 <<  3)

#       define RADEON_DAC_CMP_OUTPUT        (1 <<  7)

#       define RADEON_DAC_8BIT_EN           (1 <<  8)

#       define RADEON_DAC_VGA_ADR_EN        (1 << 13)

#       define RADEON_DAC_PDWN              (1 << 15)

#       define RADEON_DAC_MASK_ALL          (0xff << 24)

#define RADEON_DAC_CNTL2                    0x007c

#       define RADEON_DAC2_DAC_CLK_SEL      (1 <<  0)

#       define RADEON_DAC2_DAC2_CLK_SEL     (1 <<  1)

#       define RADEON_DAC2_PALETTE_ACC_CTL  (1 <<  5)

#define RADEON_DAC_EXT_CNTL                 0x0280

#       define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)

#       define RADEON_DAC_FORCE_DATA_EN      (1 << 5)

#       define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)

#       define RADEON_DAC_FORCE_DATA_MASK   0x0003ff00

#       define RADEON_DAC_FORCE_DATA_SHIFT  8

#define RADEON_TV_DAC_CNTL                  0x088c

#       define RADEON_TV_DAC_STD_MASK       0x0300

#       define RADEON_TV_DAC_RDACPD         (1 <<  24)

#       define RADEON_TV_DAC_GDACPD         (1 <<  25)

#       define RADEON_TV_DAC_BDACPD         (1 <<  26)

#define RADEON_DISP_HW_DEBUG                0x0d14

#       define RADEON_CRT2_DISP1_SEL        (1 <<  5)

#define RADEON_DISP_OUTPUT_CNTL             0x0d64

#       define RADEON_DISP_DAC_SOURCE_MASK  0x03

#       define RADEON_DISP_DAC2_SOURCE_MASK  0x0c

#       define RADEON_DISP_DAC_SOURCE_CRTC2 0x01

#       define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04

#define RADEON_DAC_CRC_SIG                  0x02cc

#define RADEON_DAC_DATA                     0x03c9 /* VGA */

#define RADEON_DAC_MASK                     0x03c6 /* VGA */

#define RADEON_DAC_R_INDEX                  0x03c7 /* VGA */

#define RADEON_DAC_W_INDEX                  0x03c8 /* VGA */

#define RADEON_DDA_CONFIG                   0x02e0

#define RADEON_DDA_ON_OFF                   0x02e4

#define RADEON_DEFAULT_OFFSET               0x16e0

#define RADEON_DEFAULT_PITCH                0x16e4

#define RADEON_DEFAULT_SC_BOTTOM_RIGHT      0x16e8

#       define RADEON_DEFAULT_SC_RIGHT_MAX  (0x1fff <<  0)

#       define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)

#define RADEON_DESTINATION_3D_CLR_CMP_VAL   0x1820

#define RADEON_DESTINATION_3D_CLR_CMP_MSK   0x1824

#define RADEON_DEVICE_ID                    0x0f02 /* PCI */

#define RADEON_DISP_MISC_CNTL               0x0d00

#       define RADEON_SOFT_RESET_GRPH_PP    (1 << 0)

#define RADEON_DISP_MERGE_CNTL	          0x0d60

#       define RADEON_DISP_ALPHA_MODE_MASK  0x03

#       define RADEON_DISP_ALPHA_MODE_KEY   0

#       define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1

#       define RADEON_DISP_ALPHA_MODE_GLOBAL 2

#       define RADEON_DISP_RGB_OFFSET_EN    (1<<8)

#       define RADEON_DISP_GRPH_ALPHA_MASK  (0xff << 16)

#       define RADEON_DISP_OV0_ALPHA_MASK   (0xff << 24)

#	define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)

#define RADEON_DISP2_MERGE_CNTL	            0x0d68

#       define RADEON_DISP2_RGB_OFFSET_EN   (1<<8)

#define RADEON_DISP_LIN_TRANS_GRPH_A        0x0d80

#define RADEON_DISP_LIN_TRANS_GRPH_B        0x0d84

#define RADEON_DISP_LIN_TRANS_GRPH_C        0x0d88

#define RADEON_DISP_LIN_TRANS_GRPH_D        0x0d8c

#define RADEON_DISP_LIN_TRANS_GRPH_E        0x0d90

#define RADEON_DISP_LIN_TRANS_GRPH_F        0x0d98

#define RADEON_DP_BRUSH_BKGD_CLR            0x1478

#define RADEON_DP_BRUSH_FRGD_CLR            0x147c

#define RADEON_DP_CNTL                      0x16c0

#       define RADEON_DST_X_LEFT_TO_RIGHT   (1 <<  0)

#       define RADEON_DST_Y_TOP_TO_BOTTOM   (1 <<  1)

#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR     0x16d0

#       define RADEON_DST_Y_MAJOR             (1 <<  2)

#       define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)

#       define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)

#define RADEON_DP_DATATYPE                  0x16c4

#       define RADEON_HOST_BIG_ENDIAN_EN    (1 << 29)

#define RADEON_DP_GUI_MASTER_CNTL           0x146c

#       define RADEON_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)

#       define RADEON_GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)

#       define RADEON_GMC_SRC_CLIPPING            (1    <<  2)

#       define RADEON_GMC_DST_CLIPPING            (1    <<  3)

#       define RADEON_GMC_BRUSH_DATATYPE_MASK     (0x0f <<  4)

#       define RADEON_GMC_BRUSH_8X8_MONO_FG_BG    (0    <<  4)

#       define RADEON_GMC_BRUSH_8X8_MONO_FG_LA    (1    <<  4)

#       define RADEON_GMC_BRUSH_1X8_MONO_FG_BG    (4    <<  4)

#       define RADEON_GMC_BRUSH_1X8_MONO_FG_LA    (5    <<  4)

#       define RADEON_GMC_BRUSH_32x1_MONO_FG_BG   (6    <<  4)

#       define RADEON_GMC_BRUSH_32x1_MONO_FG_LA   (7    <<  4)

#       define RADEON_GMC_BRUSH_32x32_MONO_FG_BG  (8    <<  4)

#       define RADEON_GMC_BRUSH_32x32_MONO_FG_LA  (9    <<  4)

#       define RADEON_GMC_BRUSH_8x8_COLOR         (10   <<  4)

#       define RADEON_GMC_BRUSH_1X8_COLOR         (12   <<  4)

#       define RADEON_GMC_BRUSH_SOLID_COLOR       (13   <<  4)

#       define RADEON_GMC_BRUSH_NONE              (15   <<  4)

#       define RADEON_GMC_DST_8BPP_CI             (2    <<  8)

#       define RADEON_GMC_DST_15BPP               (3    <<  8)

#       define RADEON_GMC_DST_16BPP               (4    <<  8)

#       define RADEON_GMC_DST_24BPP               (5    <<  8)

#       define RADEON_GMC_DST_32BPP               (6    <<  8)

#       define RADEON_GMC_DST_8BPP_RGB            (7    <<  8)

#       define RADEON_GMC_DST_Y8                  (8    <<  8)

#       define RADEON_GMC_DST_RGB8                (9    <<  8)

#       define RADEON_GMC_DST_VYUY                (11   <<  8)

#       define RADEON_GMC_DST_YVYU                (12   <<  8)

#       define RADEON_GMC_DST_AYUV444             (14   <<  8)

#       define RADEON_GMC_DST_ARGB4444            (15   <<  8)

#       define RADEON_GMC_DST_DATATYPE_MASK       (0x0f <<  8)

#       define RADEON_GMC_DST_DATATYPE_SHIFT      8

#       define RADEON_GMC_SRC_DATATYPE_MASK       (3    << 12)

#       define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0    << 12)

#       define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1    << 12)

#       define RADEON_GMC_SRC_DATATYPE_COLOR      (3    << 12)

#       define RADEON_GMC_BYTE_PIX_ORDER          (1    << 14)

#       define RADEON_GMC_BYTE_MSB_TO_LSB         (0    << 14)

#       define RADEON_GMC_BYTE_LSB_TO_MSB         (1    << 14)

#       define RADEON_GMC_CONVERSION_TEMP         (1    << 15)

#       define RADEON_GMC_CONVERSION_TEMP_6500    (0    << 15)

#       define RADEON_GMC_CONVERSION_TEMP_9300    (1    << 15)

#       define RADEON_GMC_ROP3_MASK               (0xff << 16)

#       define RADEON_DP_SRC_SOURCE_MASK          (7    << 24)

#       define RADEON_DP_SRC_SOURCE_MEMORY        (2    << 24)

#       define RADEON_DP_SRC_SOURCE_HOST_DATA     (3    << 24)

#       define RADEON_GMC_3D_FCN_EN               (1    << 27)

#       define RADEON_GMC_CLR_CMP_CNTL_DIS        (1    << 28)

#       define RADEON_GMC_AUX_CLIP_DIS            (1    << 29)

#       define RADEON_GMC_WR_MSK_DIS              (1    << 30)

#       define RADEON_GMC_LD_BRUSH_Y_X            (1    << 31)

#       define RADEON_ROP3_ZERO             0x00000000

#       define RADEON_ROP3_DSa              0x00880000

#       define RADEON_ROP3_SDna             0x00440000

#       define RADEON_ROP3_S                0x00cc0000

#       define RADEON_ROP3_DSna             0x00220000

#       define RADEON_ROP3_D                0x00aa0000

#       define RADEON_ROP3_DSx              0x00660000

#       define RADEON_ROP3_DSo              0x00ee0000

#       define RADEON_ROP3_DSon             0x00110000

#       define RADEON_ROP3_DSxn             0x00990000

#       define RADEON_ROP3_Dn               0x00550000

#       define RADEON_ROP3_SDno             0x00dd0000

#       define RADEON_ROP3_Sn               0x00330000

#       define RADEON_ROP3_DSno             0x00bb0000

#       define RADEON_ROP3_DSan             0x00770000

#       define RADEON_ROP3_ONE              0x00ff0000

#       define RADEON_ROP3_DPa              0x00a00000

#       define RADEON_ROP3_PDna             0x00500000

#       define RADEON_ROP3_P                0x00f00000

#       define RADEON_ROP3_DPna             0x000a0000

#       define RADEON_ROP3_D                0x00aa0000

#       define RADEON_ROP3_DPx              0x005a0000

#       define RADEON_ROP3_DPo              0x00fa0000

#       define RADEON_ROP3_DPon             0x00050000

#       define RADEON_ROP3_PDxn             0x00a50000

#       define RADEON_ROP3_PDno             0x00f50000

#       define RADEON_ROP3_Pn               0x000f0000

#       define RADEON_ROP3_DPno             0x00af0000

#       define RADEON_ROP3_DPan             0x005f0000

#define RADEON_DP_GUI_MASTER_CNTL_C         0x1c84

#define RADEON_DP_MIX                       0x16c8

#define RADEON_DP_SRC_BKGD_CLR              0x15dc

#define RADEON_DP_SRC_FRGD_CLR              0x15d8

#define RADEON_DP_WRITE_MASK                0x16cc

#define RADEON_DST_BRES_DEC                 0x1630

#define RADEON_DST_BRES_ERR                 0x1628

#define RADEON_DST_BRES_INC                 0x162c

#define RADEON_DST_BRES_LNTH                0x1634

#define RADEON_DST_BRES_LNTH_SUB            0x1638

#define RADEON_DST_HEIGHT                   0x1410

#define RADEON_DST_HEIGHT_WIDTH             0x143c

#define RADEON_DST_HEIGHT_WIDTH_8           0x158c

#define RADEON_DST_HEIGHT_WIDTH_BW          0x15b4

#define RADEON_DST_HEIGHT_Y                 0x15a0

#define RADEON_DST_LINE_START               0x1600

#define RADEON_DST_LINE_END                 0x1604

#define RADEON_DST_LINE_PATCOUNT            0x1608

#       define RADEON_BRES_CNTL_SHIFT       8

#define RADEON_DST_OFFSET                   0x1404

#define RADEON_DST_PITCH                    0x1408

#define RADEON_DST_PITCH_OFFSET             0x142c

#define RADEON_DST_PITCH_OFFSET_C           0x1c80

#       define RADEON_PITCH_SHIFT           21

#       define RADEON_DST_TILE_LINEAR       (0 << 30)

#       define RADEON_DST_TILE_MACRO        (1 << 30)

#       define RADEON_DST_TILE_MICRO        (2 << 30)

#       define RADEON_DST_TILE_BOTH         (3 << 30)

#define RADEON_DST_WIDTH                    0x140c

#define RADEON_DST_WIDTH_HEIGHT             0x1598

#define RADEON_DST_WIDTH_X                  0x1588

#define RADEON_DST_WIDTH_X_INCY             0x159c

#define RADEON_DST_X                        0x141c

#define RADEON_DST_X_SUB                    0x15a4

#define RADEON_DST_X_Y                      0x1594

#define RADEON_DST_Y                        0x1420

#define RADEON_DST_Y_SUB                    0x15a8

#define RADEON_DST_Y_X                      0x1438

#define RADEON_FCP_CNTL                     0x0910

#      define RADEON_FCP0_SRC_PCICLK             0

#      define RADEON_FCP0_SRC_PCLK               1

#      define RADEON_FCP0_SRC_PCLKb              2

#      define RADEON_FCP0_SRC_HREF               3

#      define RADEON_FCP0_SRC_GND                4

#      define RADEON_FCP0_SRC_HREFb              5

#define RADEON_FLUSH_1                      0x1704

#define RADEON_FLUSH_2                      0x1708

#define RADEON_FLUSH_3                      0x170c

#define RADEON_FLUSH_4                      0x1710

#define RADEON_FLUSH_5                      0x1714

#define RADEON_FLUSH_6                      0x1718

#define RADEON_FLUSH_7                      0x171c

#define RADEON_FOG_3D_TABLE_START           0x1810

#define RADEON_FOG_3D_TABLE_END             0x1814

#define RADEON_FOG_3D_TABLE_DENSITY         0x181c

#define RADEON_FOG_TABLE_INDEX              0x1a14

#define RADEON_FOG_TABLE_DATA               0x1a18

#define RADEON_FP_CRTC_H_TOTAL_DISP         0x0250

#define RADEON_FP_CRTC_V_TOTAL_DISP         0x0254

#define RADEON_FP_CRTC2_H_TOTAL_DISP        0x0350

#define RADEON_FP_CRTC2_V_TOTAL_DISP        0x0354

#       define RADEON_FP_CRTC_H_TOTAL_MASK      0x000003ff

#       define RADEON_FP_CRTC_H_DISP_MASK       0x01ff0000

#       define RADEON_FP_CRTC_V_TOTAL_MASK      0x00000fff

#       define RADEON_FP_CRTC_V_DISP_MASK       0x0fff0000

#       define RADEON_FP_H_SYNC_STRT_CHAR_MASK  0x00001ff8

#       define RADEON_FP_H_SYNC_WID_MASK        0x003f0000

#       define RADEON_FP_V_SYNC_STRT_MASK       0x00000fff

#       define RADEON_FP_V_SYNC_WID_MASK        0x001f0000

#       define RADEON_FP_CRTC_H_TOTAL_SHIFT     0x00000000

#       define RADEON_FP_CRTC_H_DISP_SHIFT      0x00000010

#       define RADEON_FP_CRTC_V_TOTAL_SHIFT     0x00000000

#       define RADEON_FP_CRTC_V_DISP_SHIFT      0x00000010

#       define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003

#       define RADEON_FP_H_SYNC_WID_SHIFT       0x00000010

#       define RADEON_FP_V_SYNC_STRT_SHIFT      0x00000000

#       define RADEON_FP_V_SYNC_WID_SHIFT       0x00000010

#define RADEON_FP_GEN_CNTL                  0x0284

#       define RADEON_FP_FPON                  (1 <<  0)

#       define RADEON_FP_TMDS_EN               (1 <<  2)

#       define RADEON_FP_PANEL_FORMAT          (1 <<  3)

#       define RADEON_FP_EN_TMDS               (1 <<  7)

#       define RADEON_FP_DETECT_SENSE          (1 <<  8)

#       define RADEON_FP_SEL_CRTC2             (1 << 13)

#       define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)

#       define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)

#       define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)

#       define RADEON_FP_CRTC_USE_SHADOW_VEND  (1 << 18)

#       define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)

#       define RADEON_FP_DFP_SYNC_SEL          (1 << 21)

#       define RADEON_FP_CRTC_LOCK_8DOT        (1 << 22)

#       define RADEON_FP_CRT_SYNC_SEL          (1 << 23)

#       define RADEON_FP_USE_SHADOW_EN         (1 << 24)

#       define RADEON_FP_CRT_SYNC_ALT          (1 << 26)

#define RADEON_FP2_GEN_CNTL                 0x0288

#       define RADEON_FP2_BLANK_EN             (1 <<  1)

#       define RADEON_FP2_ON                   (1 <<  2)

#       define RADEON_FP2_PANEL_FORMAT         (1 <<  3)

#       define RADEON_FP2_SOURCE_SEL_MASK      (3 << 10)

#       define RADEON_FP2_SOURCE_SEL_CRTC2     (1 << 10)

#       define RADEON_FP2_SRC_SEL_MASK         (3 << 13)

#       define RADEON_FP2_SRC_SEL_CRTC2        (1 << 13)

#       define RADEON_FP2_FP_POL               (1 << 16)

#       define RADEON_FP2_LP_POL               (1 << 17)

#       define RADEON_FP2_SCK_POL              (1 << 18)

#       define RADEON_FP2_LCD_CNTL_MASK        (7 << 19)

#       define RADEON_FP2_PAD_FLOP_EN          (1 << 22)

#       define RADEON_FP2_CRC_EN               (1 << 23)

#       define RADEON_FP2_CRC_READ_EN          (1 << 24)

#       define RADEON_FP2_DV0_EN               (1 << 25)

#       define RADEON_FP2_DV0_RATE_SEL_SDR     (1 << 26)

#define RADEON_FP_H_SYNC_STRT_WID           0x02c4

#define RADEON_FP_H2_SYNC_STRT_WID          0x03c4

#define RADEON_FP_HORZ_STRETCH              0x028c

#define RADEON_FP_HORZ2_STRETCH             0x038c

#       define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff

#       define RADEON_HORZ_STRETCH_RATIO_MAX  4096

#       define RADEON_HORZ_PANEL_SIZE         (0x1ff   << 16)

#       define RADEON_HORZ_PANEL_SHIFT        16

#       define RADEON_HORZ_STRETCH_PIXREP     (0      << 25)

#       define RADEON_HORZ_STRETCH_BLEND      (1      << 26)

#       define RADEON_HORZ_STRETCH_ENABLE     (1      << 25)

#       define RADEON_HORZ_AUTO_RATIO         (1      << 27)

#       define RADEON_HORZ_FP_LOOP_STRETCH    (0x7    << 28)

#       define RADEON_HORZ_AUTO_RATIO_INC     (1      << 31)

#define RADEON_FP_V_SYNC_STRT_WID           0x02c8

#define RADEON_FP_VERT_STRETCH              0x0290

#define RADEON_FP_V2_SYNC_STRT_WID          0x03c8

#define RADEON_FP_VERT2_STRETCH             0x0390

#       define RADEON_VERT_PANEL_SIZE          (0xfff << 12)

#       define RADEON_VERT_PANEL_SHIFT         12

#       define RADEON_VERT_STRETCH_RATIO_MASK  0xfff

#       define RADEON_VERT_STRETCH_RATIO_SHIFT 0

#       define RADEON_VERT_STRETCH_RATIO_MAX   4096

#       define RADEON_VERT_STRETCH_ENABLE      (1     << 25)

#       define RADEON_VERT_STRETCH_LINEREP     (0     << 26)

#       define RADEON_VERT_STRETCH_BLEND       (1     << 26)

#       define RADEON_VERT_AUTO_RATIO_EN       (1     << 27)

#       define RADEON_VERT_STRETCH_RESERVED    0xf1000000

#define RADEON_GEN_INT_CNTL                 0x0040

#define RADEON_GEN_INT_STATUS               0x0044

#       define RADEON_VSYNC_INT_AK          (1 <<  2)

#       define RADEON_VSYNC_INT             (1 <<  2)

#       define RADEON_VSYNC2_INT_AK         (1 <<  6)

#       define RADEON_VSYNC2_INT            (1 <<  6)

#define RADEON_GENENB                       0x03c3 /* VGA */

#define RADEON_GENFC_RD                     0x03ca /* VGA */

#define RADEON_GENFC_WT                     0x03da /* VGA, 0x03ba */

#define RADEON_GENMO_RD                     0x03cc /* VGA */

#define RADEON_GENMO_WT                     0x03c2 /* VGA */

#define RADEON_GENS0                        0x03c2 /* VGA */

#define RADEON_GENS1                        0x03da /* VGA, 0x03ba */

#define RADEON_GPIO_MONID                   0x0068 /* DDC interface via I2C */

#define RADEON_GPIO_MONIDB                  0x006c

#define RADEON_GPIO_CRT2_DDC                0x006c

#define RADEON_GPIO_DVI_DDC                 0x0064

#define RADEON_GPIO_VGA_DDC                 0x0060

#       define RADEON_GPIO_A_0              (1 <<  0)

#       define RADEON_GPIO_A_1              (1 <<  1)

#       define RADEON_GPIO_Y_0              (1 <<  8)

#       define RADEON_GPIO_Y_1              (1 <<  9)

#       define RADEON_GPIO_Y_SHIFT_0        8

#       define RADEON_GPIO_Y_SHIFT_1        9

#       define RADEON_GPIO_EN_0             (1 << 16)

#       define RADEON_GPIO_EN_1             (1 << 17)

#       define RADEON_GPIO_MASK_0           (1 << 24) /*??*/

#       define RADEON_GPIO_MASK_1           (1 << 25) /*??*/

#define RADEON_GRPH8_DATA                   0x03cf /* VGA */

#define RADEON_GRPH8_IDX                    0x03ce /* VGA */

#define RADEON_GUI_SCRATCH_REG0             0x15e0

#define RADEON_GUI_SCRATCH_REG1             0x15e4

#define RADEON_GUI_SCRATCH_REG2             0x15e8

#define RADEON_GUI_SCRATCH_REG3             0x15ec

#define RADEON_GUI_SCRATCH_REG4             0x15f0

#define RADEON_GUI_SCRATCH_REG5             0x15f4

#define RADEON_HEADER                       0x0f0e /* PCI */

#define RADEON_HOST_DATA0                   0x17c0

#define RADEON_HOST_DATA1                   0x17c4

#define RADEON_HOST_DATA2                   0x17c8

#define RADEON_HOST_DATA3                   0x17cc

#define RADEON_HOST_DATA4                   0x17d0

#define RADEON_HOST_DATA5                   0x17d4

#define RADEON_HOST_DATA6                   0x17d8

#define RADEON_HOST_DATA7                   0x17dc

#define RADEON_HOST_DATA_LAST               0x17e0

#define RADEON_HOST_PATH_CNTL               0x0130

#       define RADEON_HDP_SOFT_RESET        (1 << 26)

#define RADEON_HTOTAL_CNTL                  0x0009 /* PLL */

#define RADEON_HTOTAL2_CNTL                 0x002e /* PLL */

#define RADEON_I2C_CNTL_1                   0x0094 /* ? */

#define RADEON_DVI_I2C_CNTL_1               0x02e4 /* ? */

#define RADEON_INTERRUPT_LINE               0x0f3c /* PCI */

#define RADEON_INTERRUPT_PIN                0x0f3d /* PCI */

#define RADEON_IO_BASE                      0x0f14 /* PCI */

#define RADEON_LATENCY                      0x0f0d /* PCI */

#define RADEON_LEAD_BRES_DEC                0x1608

#define RADEON_LEAD_BRES_LNTH               0x161c

#define RADEON_LEAD_BRES_LNTH_SUB           0x1624

#define RADEON_LVDS_GEN_CNTL                0x02d0

#       define RADEON_LVDS_ON               (1   <<  0)

#       define RADEON_LVDS_DISPLAY_DIS      (1   <<  1)

#       define RADEON_LVDS_PANEL_TYPE       (1   <<  2)

#       define RADEON_LVDS_PANEL_FORMAT     (1   <<  3)

#       define RADEON_LVDS_EN               (1   <<  7)

#       define RADEON_LVDS_DIGON            (1   << 18)

#       define RADEON_LVDS_BLON             (1   << 19)

#       define RADEON_LVDS_SEL_CRTC2        (1   << 23)

#define RADEON_LVDS_PLL_CNTL                0x02d4

#       define RADEON_HSYNC_DELAY_SHIFT     28

#       define RADEON_HSYNC_DELAY_MASK      (0xf << 28)

#define RADEON_MAX_LATENCY                  0x0f3f /* PCI */

#define RADEON_MC_AGP_LOCATION              0x014c

#define RADEON_MC_FB_LOCATION               0x0148

#define RADEON_DISPLAY_BASE_ADDR            0x23c

#define RADEON_DISPLAY2_BASE_ADDR           0x33c

#define RADEON_OV0_BASE_ADDR                0x43c

#define RADEON_NB_TOM                       0x15c

#define RADEON_MCLK_CNTL                    0x0012 /* PLL */

#       define RADEON_FORCEON_MCLKA         (1 << 16)

#       define RADEON_FORCEON_MCLKB         (1 << 17)

#       define RADEON_FORCEON_YCLKA         (1 << 18)

#       define RADEON_FORCEON_YCLKB         (1 << 19)

#       define RADEON_FORCEON_MC            (1 << 20)

#       define RADEON_FORCEON_AIC           (1 << 21)

#define RADEON_MDGPIO_A_REG                 0x01ac

#define RADEON_MDGPIO_EN_REG                0x01b0

#define RADEON_MDGPIO_MASK                  0x0198

#define RADEON_MDGPIO_Y_REG                 0x01b4

#define RADEON_MEM_ADDR_CONFIG              0x0148

#define RADEON_MEM_BASE                     0x0f10 /* PCI */

#define RADEON_MEM_CNTL                     0x0140

#       define RADEON_MEM_NUM_CHANNELS_MASK 0x01

#       define RADEON_MEM_USE_B_CH_ONLY     (1<<1)

#       define RV100_HALF_MODE              (1<<3)

#define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */

#define RADEON_MEM_INIT_LAT_TIMER           0x0154

#define RADEON_MEM_INTF_CNTL                0x014c

#define RADEON_MEM_SDRAM_MODE_REG           0x0158

#define RADEON_MEM_STR_CNTL                 0x0150

#define RADEON_MEM_VGA_RP_SEL               0x003c

#define RADEON_MEM_VGA_WP_SEL               0x0038

#define RADEON_MIN_GRANT                    0x0f3e /* PCI */

#define RADEON_MM_DATA                      0x0004

#define RADEON_MM_INDEX                     0x0000

#define RADEON_MPLL_CNTL                    0x000e /* PLL */

#define RADEON_MPP_TB_CONFIG                0x01c0 /* ? */

#define RADEON_MPP_GP_CONFIG                0x01c8 /* ? */

#define RADEON_N_VIF_COUNT                  0x0248

#define RADEON_OV0_AUTO_FLIP_CNTL           0x0470

#define RADEON_OV0_COLOUR_CNTL              0x04E0

#define RADEON_OV0_DEINTERLACE_PATTERN      0x0474

#define RADEON_OV0_EXCLUSIVE_HORZ           0x0408

#       define  RADEON_EXCL_HORZ_START_MASK        0x000000ff

#       define  RADEON_EXCL_HORZ_END_MASK          0x0000ff00

#       define  RADEON_EXCL_HORZ_BACK_PORCH_MASK   0x00ff0000

#       define  RADEON_EXCL_HORZ_EXCLUSIVE_EN      0x80000000

#define RADEON_OV0_EXCLUSIVE_VERT           0x040C

#       define  RADEON_EXCL_VERT_START_MASK        0x000003ff

#       define  RADEON_EXCL_VERT_END_MASK          0x03ff0000

#define RADEON_OV0_FILTER_CNTL              0x04A0

#define RADEON_OV0_FOUR_TAP_COEF_0          0x04B0

#define RADEON_OV0_FOUR_TAP_COEF_1          0x04B4

#define RADEON_OV0_FOUR_TAP_COEF_2          0x04B8

#define RADEON_OV0_FOUR_TAP_COEF_3          0x04BC

#define RADEON_OV0_FOUR_TAP_COEF_4          0x04C0

#define RADEON_OV0_GAMMA_000_00F            0x0d40

#define RADEON_OV0_GAMMA_010_01F            0x0d44

#define RADEON_OV0_GAMMA_020_03F            0x0d48

#define RADEON_OV0_GAMMA_040_07F            0x0d4c

#define RADEON_OV0_GAMMA_080_0BF            0x0e00

#define RADEON_OV0_GAMMA_0C0_0FF            0x0e04

#define RADEON_OV0_GAMMA_100_13F            0x0e08

#define RADEON_OV0_GAMMA_140_17F            0x0e0c

#define RADEON_OV0_GAMMA_180_1BF            0x0e10

#define RADEON_OV0_GAMMA_1C0_1FF            0x0e14

#define RADEON_OV0_GAMMA_200_23F            0x0e18

#define RADEON_OV0_GAMMA_240_27F            0x0e1c

#define RADEON_OV0_GAMMA_280_2BF            0x0e20

#define RADEON_OV0_GAMMA_2C0_2FF            0x0e24

#define RADEON_OV0_GAMMA_300_33F            0x0e28

#define RADEON_OV0_GAMMA_340_37F            0x0e2c

#define RADEON_OV0_GAMMA_380_3BF            0x0d50

#define RADEON_OV0_GAMMA_3C0_3FF            0x0d54

#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW     0x04EC

#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH    0x04F0

#define RADEON_OV0_H_INC                    0x0480

#define RADEON_OV0_KEY_CNTL                 0x04F4

#       define  RADEON_VIDEO_KEY_FN_MASK    0x00000003L

#       define  RADEON_VIDEO_KEY_FN_FALSE   0x00000000L

#       define  RADEON_VIDEO_KEY_FN_TRUE    0x00000001L

#       define  RADEON_VIDEO_KEY_FN_EQ      0x00000002L

#       define  RADEON_VIDEO_KEY_FN_NE      0x00000003L

#       define  RADEON_GRAPHIC_KEY_FN_MASK  0x00000030L

#       define  RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L

#       define  RADEON_GRAPHIC_KEY_FN_TRUE  0x00000010L

#       define  RADEON_GRAPHIC_KEY_FN_EQ    0x00000020L

#       define  RADEON_GRAPHIC_KEY_FN_NE    0x00000030L

#       define  RADEON_CMP_MIX_MASK         0x00000100L

#       define  RADEON_CMP_MIX_OR           0x00000000L

#       define  RADEON_CMP_MIX_AND          0x00000100L

#define RADEON_OV0_LIN_TRANS_A              0x0d20

#define RADEON_OV0_LIN_TRANS_B              0x0d24

#define RADEON_OV0_LIN_TRANS_C              0x0d28

#define RADEON_OV0_LIN_TRANS_D              0x0d2c

#define RADEON_OV0_LIN_TRANS_E              0x0d30

#define RADEON_OV0_LIN_TRANS_F              0x0d34

#define RADEON_OV0_P1_BLANK_LINES_AT_TOP    0x0430

#       define  RADEON_P1_BLNK_LN_AT_TOP_M1_MASK   0x00000fffL

#       define  RADEON_P1_ACTIVE_LINES_M1          0x0fff0000L

#define RADEON_OV0_P1_H_ACCUM_INIT          0x0488

#define RADEON_OV0_P1_V_ACCUM_INIT          0x0428

#       define  RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L

#       define  RADEON_OV0_P1_V_ACCUM_INIT_MASK    0x01ff8000L

#define RADEON_OV0_P1_X_START_END           0x0494

#define RADEON_OV0_P2_X_START_END           0x0498

#define RADEON_OV0_P23_BLANK_LINES_AT_TOP   0x0434

#       define  RADEON_P23_BLNK_LN_AT_TOP_M1_MASK  0x000007ffL

#       define  RADEON_P23_ACTIVE_LINES_M1         0x07ff0000L

#define RADEON_OV0_P23_H_ACCUM_INIT         0x048C

#define RADEON_OV0_P23_V_ACCUM_INIT         0x042C

#define RADEON_OV0_P3_X_START_END           0x049C

#define RADEON_OV0_REG_LOAD_CNTL            0x0410

#       define  RADEON_REG_LD_CTL_LOCK                 0x00000001L

#       define  RADEON_REG_LD_CTL_VBLANK_DURING_LOCK   0x00000002L

#       define  RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L

#       define  RADEON_REG_LD_CTL_LOCK_READBACK        0x00000008L

#define RADEON_OV0_SCALE_CNTL               0x0420

#       define  RADEON_SCALER_HORZ_PICK_NEAREST    0x00000004L

#       define  RADEON_SCALER_VERT_PICK_NEAREST    0x00000008L

#       define  RADEON_SCALER_SIGNED_UV            0x00000010L

#       define  RADEON_SCALER_GAMMA_SEL_MASK       0x00000060L

#       define  RADEON_SCALER_GAMMA_SEL_BRIGHT     0x00000000L

#       define  RADEON_SCALER_GAMMA_SEL_G22        0x00000020L

#       define  RADEON_SCALER_GAMMA_SEL_G18        0x00000040L

#       define  RADEON_SCALER_GAMMA_SEL_G14        0x00000060L

#       define  RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L

#       define  RADEON_SCALER_SURFAC_FORMAT        0x00000f00L

#       define  RADEON_SCALER_SOURCE_15BPP         0x00000300L

#       define  RADEON_SCALER_SOURCE_16BPP         0x00000400L

#       define  RADEON_SCALER_SOURCE_32BPP         0x00000600L

#       define  RADEON_SCALER_SOURCE_YUV9          0x00000900L

#       define  RADEON_SCALER_SOURCE_YUV12         0x00000A00L

#       define  RADEON_SCALER_SOURCE_VYUY422       0x00000B00L

#       define  RADEON_SCALER_SOURCE_YVYU422       0x00000C00L

#       define  RADEON_SCALER_ADAPTIVE_DEINT       0x00001000L

#       define  RADEON_SCALER_TEMPORAL_DEINT       0x00002000L

#       define  RADEON_SCALER_SMART_SWITCH         0x00008000L

#       define  RADEON_SCALER_BURST_PER_PLANE      0x007F0000L

#       define  RADEON_SCALER_DOUBLE_BUFFER        0x01000000L

#       define  RADEON_SCALER_DIS_LIMIT            0x08000000L

#       define  RADEON_SCALER_INT_EMU              0x20000000L

#       define  RADEON_SCALER_ENABLE               0x40000000L

#       define  RADEON_SCALER_SOFT_RESET           0x80000000L

#       define  RADEON_SCALER_ADAPTIVE_DEINT       0x00001000L

#define RADEON_OV0_STEP_BY                  0x0484

#define RADEON_OV0_TEST                     0x04F8

#define RADEON_OV0_V_INC                    0x0424

#define RADEON_OV0_VID_BUF_PITCH0_VALUE     0x0460

#define RADEON_OV0_VID_BUF_PITCH1_VALUE     0x0464

#define RADEON_OV0_VID_BUF0_BASE_ADRS       0x0440

#       define  RADEON_VIF_BUF0_PITCH_SEL          0x00000001L

#       define  RADEON_VIF_BUF0_TILE_ADRS          0x00000002L

#       define  RADEON_VIF_BUF0_BASE_ADRS_MASK     0x03fffff0L

#       define  RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L

#define RADEON_OV0_VID_BUF1_BASE_ADRS       0x0444

#       define  RADEON_VIF_BUF1_PITCH_SEL          0x00000001L

#       define  RADEON_VIF_BUF1_TILE_ADRS          0x00000002L

#       define  RADEON_VIF_BUF1_BASE_ADRS_MASK     0x03fffff0L

#       define  RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L

#define RADEON_OV0_VID_BUF2_BASE_ADRS       0x0448

#       define  RADEON_VIF_BUF2_PITCH_SEL          0x00000001L

#       define  RADEON_VIF_BUF2_TILE_ADRS          0x00000002L

#       define  RADEON_VIF_BUF2_BASE_ADRS_MASK     0x03fffff0L

#       define  RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L

#define RADEON_OV0_VID_BUF3_BASE_ADRS       0x044C

#define RADEON_OV0_VID_BUF4_BASE_ADRS       0x0450

#define RADEON_OV0_VID_BUF5_BASE_ADRS       0x0454

#define RADEON_OV0_VIDEO_KEY_CLR_HIGH       0x04E8

#define RADEON_OV0_VIDEO_KEY_CLR_LOW        0x04E4

#define RADEON_OV0_Y_X_START                0x0400

#define RADEON_OV0_Y_X_END                  0x0404

#define RADEON_OV1_Y_X_START                0x0600

#define RADEON_OV1_Y_X_END                  0x0604

#define RADEON_OVR_CLR                      0x0230

#define RADEON_OVR_WID_LEFT_RIGHT           0x0234

#define RADEON_OVR_WID_TOP_BOTTOM           0x0238

#define RADEON_P2PLL_CNTL                   0x002a /* P2PLL */

#       define RADEON_P2PLL_RESET                (1 <<  0)

#       define RADEON_P2PLL_SLEEP                (1 <<  1)

#       define RADEON_P2PLL_ATOMIC_UPDATE_EN     (1 << 16)

#       define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

#       define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC  (1 << 18)

#define RADEON_P2PLL_DIV_0                  0x002c

#       define RADEON_P2PLL_FB0_DIV_MASK    0x07ff

#       define RADEON_P2PLL_POST0_DIV_MASK  0x00070000

#define RADEON_P2PLL_REF_DIV                0x002B /* PLL */

#       define RADEON_P2PLL_REF_DIV_MASK    0x03ff

#       define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

#       define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

#define RADEON_PALETTE_DATA                 0x00b4

#define RADEON_PALETTE_30_DATA              0x00b8

#define RADEON_PALETTE_INDEX                0x00b0

#define RADEON_PCI_GART_PAGE                0x017c

#define RADEON_PIXCLKS_CNTL                 0x002d

#       define RADEON_PIX2CLK_SRC_SEL_MASK     0x03

#       define RADEON_PIX2CLK_SRC_SEL_CPUCLK   0x00

#       define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01

#       define RADEON_PIX2CLK_SRC_SEL_BYTECLK  0x02

#       define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03

#       define RADEON_PIX2CLK_ALWAYS_ONb       (1<<6)

#       define RADEON_PIX2CLK_DAC_ALWAYS_ONb   (1<<7)

#       define RADEON_PIXCLK_TV_SRC_SEL        (1 << 8)

#       define RADEON_PIXCLK_LVDS_ALWAYS_ONb   (1 << 14)

#       define RADEON_PIXCLK_TMDS_ALWAYS_ONb   (1 << 15)

#define RADEON_PLANE_3D_MASK_C              0x1d44

#define RADEON_PLL_TEST_CNTL                0x0013 /* PLL */

#define RADEON_PMI_CAP_ID                   0x0f5c /* PCI */

#define RADEON_PMI_DATA                     0x0f63 /* PCI */

#define RADEON_PMI_NXT_CAP_PTR              0x0f5d /* PCI */

#define RADEON_PMI_PMC_REG                  0x0f5e /* PCI */

#define RADEON_PMI_PMCSR_REG                0x0f60 /* PCI */

#define RADEON_PMI_REGISTER                 0x0f5c /* PCI */

#define RADEON_PPLL_CNTL                    0x0002 /* PLL */

#       define RADEON_PPLL_RESET                (1 <<  0)

#       define RADEON_PPLL_SLEEP                (1 <<  1)

#       define RADEON_PPLL_ATOMIC_UPDATE_EN     (1 << 16)

#       define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

#       define RADEON_PPLL_ATOMIC_UPDATE_VSYNC  (1 << 18)

#define RADEON_PPLL_DIV_0                   0x0004 /* PLL */

#define RADEON_PPLL_DIV_1                   0x0005 /* PLL */

#define RADEON_PPLL_DIV_2                   0x0006 /* PLL */

#define RADEON_PPLL_DIV_3                   0x0007 /* PLL */

#       define RADEON_PPLL_FB3_DIV_MASK     0x07ff

#       define RADEON_PPLL_POST3_DIV_MASK   0x00070000

#define RADEON_PPLL_REF_DIV                 0x0003 /* PLL */

#       define RADEON_PPLL_REF_DIV_MASK     0x03ff

#       define RADEON_PPLL_ATOMIC_UPDATE_R  (1 << 15) /* same as _W */

#       define RADEON_PPLL_ATOMIC_UPDATE_W  (1 << 15) /* same as _R */

#define RADEON_PWR_MNGMT_CNTL_STATUS        0x0f60 /* PCI */

#define RADEON_RBBM_GUICNTL                 0x172c

#       define RADEON_HOST_DATA_SWAP_NONE   (0 << 0)

#       define RADEON_HOST_DATA_SWAP_16BIT  (1 << 0)

#       define RADEON_HOST_DATA_SWAP_32BIT  (2 << 0)

#       define RADEON_HOST_DATA_SWAP_HDW    (3 << 0)

#define RADEON_RBBM_SOFT_RESET              0x00f0

#       define RADEON_SOFT_RESET_CP         (1 <<  0)

#       define RADEON_SOFT_RESET_HI         (1 <<  1)

#       define RADEON_SOFT_RESET_SE         (1 <<  2)

#       define RADEON_SOFT_RESET_RE         (1 <<  3)

#       define RADEON_SOFT_RESET_PP         (1 <<  4)

#       define RADEON_SOFT_RESET_E2         (1 <<  5)

#       define RADEON_SOFT_RESET_RB         (1 <<  6)

#       define RADEON_SOFT_RESET_HDP        (1 <<  7)

#define RADEON_RBBM_STATUS                  0x0e40

#       define RADEON_RBBM_FIFOCNT_MASK     0x007f

#       define RADEON_RBBM_ACTIVE           (1 << 31)

#define RADEON_RB2D_DSTCACHE_CTLSTAT        0x342c

#       define RADEON_RB2D_DC_FLUSH         (3 << 0)

#       define RADEON_RB2D_DC_FREE          (3 << 2)

#       define RADEON_RB2D_DC_FLUSH_ALL     0xf

#       define RADEON_RB2D_DC_BUSY          (1 << 31)

#define RADEON_RB2D_DSTCACHE_MODE           0x3428

#define RADEON_REG_BASE                     0x0f18 /* PCI */

#define RADEON_REGPROG_INF                  0x0f09 /* PCI */

#define RADEON_REVISION_ID                  0x0f08 /* PCI */

#define RADEON_SC_BOTTOM                    0x164c

#define RADEON_SC_BOTTOM_RIGHT              0x16f0

#define RADEON_SC_BOTTOM_RIGHT_C            0x1c8c

#define RADEON_SC_LEFT                      0x1640

#define RADEON_SC_RIGHT                     0x1644

#define RADEON_SC_TOP                       0x1648

#define RADEON_SC_TOP_LEFT                  0x16ec

#define RADEON_SC_TOP_LEFT_C                0x1c88

#       define RADEON_SC_SIGN_MASK_LO       0x8000

#       define RADEON_SC_SIGN_MASK_HI       0x80000000

#define RADEON_SCLK_CNTL                    0x000d /* PLL */

#       define RADEON_DYN_STOP_LAT_MASK     0x00007ff8

#       define RADEON_CP_MAX_DYN_STOP_LAT   0x0008

#       define RADEON_SCLK_FORCEON_MASK     0xffff8000

#define RADEON_SCLK_MORE_CNTL               0x0035 /* PLL */

#       define RADEON_SCLK_MORE_FORCEON     0x0700

#define RADEON_SDRAM_MODE_REG               0x0158

#define RADEON_SEQ8_DATA                    0x03c5 /* VGA */

#define RADEON_SEQ8_IDX                     0x03c4 /* VGA */

#define RADEON_SNAPSHOT_F_COUNT             0x0244

#define RADEON_SNAPSHOT_VH_COUNTS           0x0240

#define RADEON_SNAPSHOT_VIF_COUNT           0x024c

#define RADEON_SRC_OFFSET                   0x15ac

#define RADEON_SRC_PITCH                    0x15b0

#define RADEON_SRC_PITCH_OFFSET             0x1428

#define RADEON_SRC_SC_BOTTOM                0x165c

#define RADEON_SRC_SC_BOTTOM_RIGHT          0x16f4

#define RADEON_SRC_SC_RIGHT                 0x1654

#define RADEON_SRC_X                        0x1414

#define RADEON_SRC_X_Y                      0x1590

#define RADEON_SRC_Y                        0x1418

#define RADEON_SRC_Y_X                      0x1434

#define RADEON_STATUS                       0x0f06 /* PCI */

#define RADEON_SUBPIC_CNTL                  0x0540 /* ? */

#define RADEON_SUB_CLASS                    0x0f0a /* PCI */

#define RADEON_SURFACE_CNTL                 0x0b00

#       define RADEON_SURF_TRANSLATION_DIS  (1 << 8)

#       define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)

#       define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)

#define RADEON_SURFACE0_INFO                0x0b0c

#       define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)

#       define RADEON_SURF_TILE_COLOR_BOTH  (1 << 16)

#       define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)

#       define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)

#       define R200_SURF_TILE_NONE          (0 << 16)

#       define R200_SURF_TILE_COLOR_MACRO   (1 << 16)

#       define R200_SURF_TILE_COLOR_MICRO   (2 << 16)

#       define R200_SURF_TILE_COLOR_BOTH    (3 << 16)

#       define R200_SURF_TILE_DEPTH_32BPP   (4 << 16)

#       define R200_SURF_TILE_DEPTH_16BPP   (5 << 16)

#       define RADEON_SURF_AP0_SWP_16BPP    (1 << 20)

#       define RADEON_SURF_AP0_SWP_32BPP    (1 << 21)

#       define RADEON_SURF_AP1_SWP_16BPP    (1 << 22)

#       define RADEON_SURF_AP1_SWP_32BPP    (1 << 23)

#define RADEON_SURFACE0_LOWER_BOUND         0x0b04

#define RADEON_SURFACE0_UPPER_BOUND         0x0b08

#define RADEON_SURFACE1_INFO                0x0b1c

#define RADEON_SURFACE1_LOWER_BOUND         0x0b14

#define RADEON_SURFACE1_UPPER_BOUND         0x0b18

#define RADEON_SURFACE2_INFO                0x0b2c

#define RADEON_SURFACE2_LOWER_BOUND         0x0b24

#define RADEON_SURFACE2_UPPER_BOUND         0x0b28

#define RADEON_SURFACE3_INFO                0x0b3c

#define RADEON_SURFACE3_LOWER_BOUND         0x0b34

#define RADEON_SURFACE3_UPPER_BOUND         0x0b38

#define RADEON_SURFACE4_INFO                0x0b4c

#define RADEON_SURFACE4_LOWER_BOUND         0x0b44

#define RADEON_SURFACE4_UPPER_BOUND         0x0b48

#define RADEON_SURFACE5_INFO                0x0b5c

#define RADEON_SURFACE5_LOWER_BOUND         0x0b54

#define RADEON_SURFACE5_UPPER_BOUND         0x0b58

#define RADEON_SURFACE6_INFO                0x0b6c

#define RADEON_SURFACE6_LOWER_BOUND         0x0b64

#define RADEON_SURFACE6_UPPER_BOUND         0x0b68

#define RADEON_SURFACE7_INFO                0x0b7c

#define RADEON_SURFACE7_LOWER_BOUND         0x0b74

#define RADEON_SURFACE7_UPPER_BOUND         0x0b78

#define RADEON_SW_SEMAPHORE                 0x013c

#define RADEON_TEST_DEBUG_CNTL              0x0120

#define RADEON_TEST_DEBUG_MUX               0x0124

#define RADEON_TEST_DEBUG_OUT               0x012c

#define RADEON_TMDS_PLL_CNTL                0x02a8

#define RADEON_TMDS_TRANSMITTER_CNTL        0x02a4

#       define RADEON_TMDS_TRANSMITTER_PLLEN  1

#       define RADEON_TMDS_TRANSMITTER_PLLRST 2

#define RADEON_TRAIL_BRES_DEC               0x1614

#define RADEON_TRAIL_BRES_ERR               0x160c

#define RADEON_TRAIL_BRES_INC               0x1610

#define RADEON_TRAIL_X                      0x1618

#define RADEON_TRAIL_X_SUB                  0x1620

#define RADEON_VCLK_ECP_CNTL                0x0008 /* PLL */

#       define RADEON_VCLK_SRC_SEL_MASK     0x03

#       define RADEON_VCLK_SRC_SEL_CPUCLK   0x00

#       define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01

#       define RADEON_VCLK_SRC_SEL_BYTECLK  0x02

#       define RADEON_VCLK_SRC_SEL_PPLLCLK  0x03

#       define RADEON_PIXCLK_ALWAYS_ONb     (1<<6)

#       define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)

#define RADEON_VENDOR_ID                    0x0f00 /* PCI */

#define RADEON_VGA_DDA_CONFIG               0x02e8

#define RADEON_VGA_DDA_ON_OFF               0x02ec

#define RADEON_VID_BUFFER_CONTROL           0x0900

#define RADEON_VIDEOMUX_CNTL                0x0190

#define RADEON_VIPH_CONTROL                 0x0c40 /* ? */

#define RADEON_WAIT_UNTIL                   0x1720

#       define RADEON_WAIT_CRTC_PFLIP       (1 << 0)

#       define RADEON_WAIT_2D_IDLECLEAN     (1 << 16)

#       define RADEON_WAIT_3D_IDLECLEAN     (1 << 17)

#       define RADEON_WAIT_HOST_IDLECLEAN   (1 << 18)