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5564 | serge | 1 | /* |
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. |
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3 | Intel funded Tungsten Graphics to |
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4 | develop this 3D driver. |
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5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining |
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7 | a copy of this software and associated documentation files (the |
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8 | "Software"), to deal in the Software without restriction, including |
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9 | without limitation the rights to use, copy, modify, merge, publish, |
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10 | distribute, sublicense, and/or sell copies of the Software, and to |
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11 | permit persons to whom the Software is furnished to do so, subject to |
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12 | the following conditions: |
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13 | |||
14 | The above copyright notice and this permission notice (including the |
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15 | next paragraph) shall be included in all copies or substantial |
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16 | portions of the Software. |
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17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | |||
26 | **********************************************************************/ |
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27 | /* |
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28 | * Authors: |
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29 | * Keith Whitwell |
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30 | */ |
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31 | |||
32 | |||
33 | #ifndef BRW_STRUCTS_H |
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34 | #define BRW_STRUCTS_H |
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35 | |||
36 | struct brw_urb_fence |
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37 | { |
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38 | struct |
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39 | { |
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40 | unsigned length:8; |
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41 | unsigned vs_realloc:1; |
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42 | unsigned gs_realloc:1; |
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43 | unsigned clp_realloc:1; |
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44 | unsigned sf_realloc:1; |
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45 | unsigned vfe_realloc:1; |
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46 | unsigned cs_realloc:1; |
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47 | unsigned pad:2; |
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48 | unsigned opcode:16; |
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49 | } header; |
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50 | |||
51 | struct |
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52 | { |
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53 | unsigned vs_fence:10; |
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54 | unsigned gs_fence:10; |
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55 | unsigned clp_fence:10; |
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56 | unsigned pad:2; |
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57 | } bits0; |
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58 | |||
59 | struct |
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60 | { |
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61 | unsigned sf_fence:10; |
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62 | unsigned vf_fence:10; |
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63 | unsigned cs_fence:11; |
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64 | unsigned pad:1; |
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65 | } bits1; |
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66 | }; |
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67 | |||
68 | /* State structs for the various fixed function units: |
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69 | */ |
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70 | |||
71 | |||
72 | struct thread0 |
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73 | { |
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74 | unsigned pad0:1; |
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75 | unsigned grf_reg_count:3; |
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76 | unsigned pad1:2; |
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77 | unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */ |
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78 | }; |
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79 | |||
80 | struct thread1 |
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81 | { |
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82 | unsigned ext_halt_exception_enable:1; |
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83 | unsigned sw_exception_enable:1; |
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84 | unsigned mask_stack_exception_enable:1; |
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85 | unsigned timeout_exception_enable:1; |
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86 | unsigned illegal_op_exception_enable:1; |
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87 | unsigned pad0:3; |
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88 | unsigned depth_coef_urb_read_offset:6; /* WM only */ |
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89 | unsigned pad1:2; |
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90 | unsigned floating_point_mode:1; |
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91 | unsigned thread_priority:1; |
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92 | unsigned binding_table_entry_count:8; |
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93 | unsigned pad3:5; |
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94 | unsigned single_program_flow:1; |
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95 | }; |
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96 | |||
97 | struct thread2 |
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98 | { |
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99 | unsigned per_thread_scratch_space:4; |
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100 | unsigned pad0:6; |
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101 | unsigned scratch_space_base_pointer:22; |
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102 | }; |
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103 | |||
104 | |||
105 | struct thread3 |
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106 | { |
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107 | unsigned dispatch_grf_start_reg:4; |
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108 | unsigned urb_entry_read_offset:6; |
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109 | unsigned pad0:1; |
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110 | unsigned urb_entry_read_length:6; |
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111 | unsigned pad1:1; |
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112 | unsigned const_urb_entry_read_offset:6; |
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113 | unsigned pad2:1; |
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114 | unsigned const_urb_entry_read_length:6; |
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115 | unsigned pad3:1; |
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116 | }; |
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117 | |||
118 | |||
119 | |||
120 | struct brw_clip_unit_state |
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121 | { |
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122 | struct thread0 thread0; |
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123 | struct |
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124 | { |
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125 | unsigned pad0:7; |
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126 | unsigned sw_exception_enable:1; |
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127 | unsigned pad1:3; |
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128 | unsigned mask_stack_exception_enable:1; |
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129 | unsigned pad2:1; |
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130 | unsigned illegal_op_exception_enable:1; |
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131 | unsigned pad3:2; |
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132 | unsigned floating_point_mode:1; |
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133 | unsigned thread_priority:1; |
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134 | unsigned binding_table_entry_count:8; |
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135 | unsigned pad4:5; |
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136 | unsigned single_program_flow:1; |
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137 | } thread1; |
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138 | |||
139 | struct thread2 thread2; |
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140 | struct thread3 thread3; |
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141 | |||
142 | struct |
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143 | { |
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144 | unsigned pad0:9; |
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145 | unsigned gs_output_stats:1; /* not always */ |
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146 | unsigned stats_enable:1; |
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147 | unsigned nr_urb_entries:7; |
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148 | unsigned pad1:1; |
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149 | unsigned urb_entry_allocation_size:5; |
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150 | unsigned pad2:1; |
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151 | unsigned max_threads:5; /* may be less */ |
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152 | unsigned pad3:2; |
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153 | } thread4; |
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154 | |||
155 | struct |
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156 | { |
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157 | unsigned pad0:13; |
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158 | unsigned clip_mode:3; |
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159 | unsigned userclip_enable_flags:8; |
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160 | unsigned userclip_must_clip:1; |
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161 | unsigned negative_w_clip_test:1; |
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162 | unsigned guard_band_enable:1; |
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163 | unsigned viewport_z_clip_enable:1; |
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164 | unsigned viewport_xy_clip_enable:1; |
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165 | unsigned vertex_position_space:1; |
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166 | unsigned api_mode:1; |
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167 | unsigned pad2:1; |
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168 | } clip5; |
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169 | |||
170 | struct |
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171 | { |
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172 | unsigned pad0:5; |
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173 | unsigned clipper_viewport_state_ptr:27; |
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174 | } clip6; |
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175 | |||
176 | |||
177 | float viewport_xmin; |
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178 | float viewport_xmax; |
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179 | float viewport_ymin; |
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180 | float viewport_ymax; |
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181 | }; |
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182 | |||
183 | struct gen6_blend_state |
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184 | { |
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185 | struct { |
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186 | unsigned dest_blend_factor:5; |
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187 | unsigned source_blend_factor:5; |
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188 | unsigned pad3:1; |
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189 | unsigned blend_func:3; |
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190 | unsigned pad2:1; |
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191 | unsigned ia_dest_blend_factor:5; |
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192 | unsigned ia_source_blend_factor:5; |
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193 | unsigned pad1:1; |
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194 | unsigned ia_blend_func:3; |
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195 | unsigned pad0:1; |
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196 | unsigned ia_blend_enable:1; |
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197 | unsigned blend_enable:1; |
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198 | } blend0; |
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199 | |||
200 | struct { |
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201 | unsigned post_blend_clamp_enable:1; |
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202 | unsigned pre_blend_clamp_enable:1; |
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203 | unsigned clamp_range:2; |
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204 | unsigned pad0:4; |
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205 | unsigned x_dither_offset:2; |
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206 | unsigned y_dither_offset:2; |
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207 | unsigned dither_enable:1; |
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208 | unsigned alpha_test_func:3; |
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209 | unsigned alpha_test_enable:1; |
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210 | unsigned pad1:1; |
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211 | unsigned logic_op_func:4; |
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212 | unsigned logic_op_enable:1; |
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213 | unsigned pad2:1; |
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214 | unsigned write_disable_b:1; |
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215 | unsigned write_disable_g:1; |
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216 | unsigned write_disable_r:1; |
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217 | unsigned write_disable_a:1; |
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218 | unsigned pad3:1; |
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219 | unsigned alpha_to_coverage_dither:1; |
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220 | unsigned alpha_to_one:1; |
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221 | unsigned alpha_to_coverage:1; |
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222 | } blend1; |
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223 | }; |
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224 | |||
225 | struct gen6_color_calc_state |
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226 | { |
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227 | struct { |
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228 | unsigned alpha_test_format:1; |
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229 | unsigned pad0:14; |
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230 | unsigned round_disable:1; |
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231 | unsigned bf_stencil_ref:8; |
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232 | unsigned stencil_ref:8; |
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233 | } cc0; |
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234 | |||
235 | union { |
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236 | float alpha_ref_f; |
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237 | struct { |
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238 | unsigned ui:8; |
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239 | unsigned pad0:24; |
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240 | } alpha_ref_fi; |
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241 | } cc1; |
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242 | |||
243 | float constant_r; |
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244 | float constant_g; |
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245 | float constant_b; |
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246 | float constant_a; |
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247 | }; |
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248 | |||
249 | struct gen6_depth_stencil_state |
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250 | { |
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251 | struct { |
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252 | unsigned pad0:3; |
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253 | unsigned bf_stencil_pass_depth_pass_op:3; |
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254 | unsigned bf_stencil_pass_depth_fail_op:3; |
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255 | unsigned bf_stencil_fail_op:3; |
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256 | unsigned bf_stencil_func:3; |
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257 | unsigned bf_stencil_enable:1; |
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258 | unsigned pad1:2; |
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259 | unsigned stencil_write_enable:1; |
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260 | unsigned stencil_pass_depth_pass_op:3; |
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261 | unsigned stencil_pass_depth_fail_op:3; |
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262 | unsigned stencil_fail_op:3; |
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263 | unsigned stencil_func:3; |
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264 | unsigned stencil_enable:1; |
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265 | } ds0; |
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266 | |||
267 | struct { |
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268 | unsigned bf_stencil_write_mask:8; |
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269 | unsigned bf_stencil_test_mask:8; |
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270 | unsigned stencil_write_mask:8; |
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271 | unsigned stencil_test_mask:8; |
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272 | } ds1; |
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273 | |||
274 | struct { |
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275 | unsigned pad0:26; |
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276 | unsigned depth_write_enable:1; |
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277 | unsigned depth_test_func:3; |
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278 | unsigned pad1:1; |
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279 | unsigned depth_test_enable:1; |
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280 | } ds2; |
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281 | }; |
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282 | |||
283 | struct brw_cc_unit_state |
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284 | { |
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285 | struct |
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286 | { |
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287 | unsigned pad0:3; |
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288 | unsigned bf_stencil_pass_depth_pass_op:3; |
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289 | unsigned bf_stencil_pass_depth_fail_op:3; |
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290 | unsigned bf_stencil_fail_op:3; |
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291 | unsigned bf_stencil_func:3; |
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292 | unsigned bf_stencil_enable:1; |
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293 | unsigned pad1:2; |
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294 | unsigned stencil_write_enable:1; |
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295 | unsigned stencil_pass_depth_pass_op:3; |
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296 | unsigned stencil_pass_depth_fail_op:3; |
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297 | unsigned stencil_fail_op:3; |
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298 | unsigned stencil_func:3; |
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299 | unsigned stencil_enable:1; |
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300 | } cc0; |
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301 | |||
302 | |||
303 | struct |
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304 | { |
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305 | unsigned bf_stencil_ref:8; |
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306 | unsigned stencil_write_mask:8; |
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307 | unsigned stencil_test_mask:8; |
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308 | unsigned stencil_ref:8; |
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309 | } cc1; |
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310 | |||
311 | |||
312 | struct |
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313 | { |
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314 | unsigned logicop_enable:1; |
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315 | unsigned pad0:10; |
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316 | unsigned depth_write_enable:1; |
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317 | unsigned depth_test_function:3; |
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318 | unsigned depth_test:1; |
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319 | unsigned bf_stencil_write_mask:8; |
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320 | unsigned bf_stencil_test_mask:8; |
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321 | } cc2; |
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322 | |||
323 | |||
324 | struct |
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325 | { |
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326 | unsigned pad0:8; |
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327 | unsigned alpha_test_func:3; |
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328 | unsigned alpha_test:1; |
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329 | unsigned blend_enable:1; |
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330 | unsigned ia_blend_enable:1; |
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331 | unsigned pad1:1; |
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332 | unsigned alpha_test_format:1; |
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333 | unsigned pad2:16; |
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334 | } cc3; |
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335 | |||
336 | struct |
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337 | { |
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338 | unsigned pad0:5; |
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339 | unsigned cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ |
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340 | } cc4; |
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341 | |||
342 | struct |
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343 | { |
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344 | unsigned pad0:2; |
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345 | unsigned ia_dest_blend_factor:5; |
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346 | unsigned ia_src_blend_factor:5; |
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347 | unsigned ia_blend_function:3; |
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348 | unsigned statistics_enable:1; |
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349 | unsigned logicop_func:4; |
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350 | unsigned pad1:11; |
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351 | unsigned dither_enable:1; |
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352 | } cc5; |
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353 | |||
354 | struct |
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355 | { |
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356 | unsigned clamp_post_alpha_blend:1; |
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357 | unsigned clamp_pre_alpha_blend:1; |
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358 | unsigned clamp_range:2; |
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359 | unsigned pad0:11; |
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360 | unsigned y_dither_offset:2; |
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361 | unsigned x_dither_offset:2; |
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362 | unsigned dest_blend_factor:5; |
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363 | unsigned src_blend_factor:5; |
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364 | unsigned blend_function:3; |
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365 | } cc6; |
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366 | |||
367 | struct { |
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368 | union { |
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369 | float f; |
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370 | uint8_t ub[4]; |
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371 | } alpha_ref; |
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372 | } cc7; |
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373 | }; |
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374 | |||
375 | struct brw_sf_unit_state |
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376 | { |
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377 | struct thread0 thread0; |
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378 | struct thread1 thread1; |
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379 | struct thread2 thread2; |
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380 | struct thread3 thread3; |
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381 | |||
382 | struct |
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383 | { |
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384 | unsigned pad0:10; |
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385 | unsigned stats_enable:1; |
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386 | unsigned nr_urb_entries:7; |
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387 | unsigned pad1:1; |
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388 | unsigned urb_entry_allocation_size:5; |
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389 | unsigned pad2:1; |
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390 | unsigned max_threads:6; |
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391 | unsigned pad3:1; |
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392 | } thread4; |
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393 | |||
394 | struct |
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395 | { |
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396 | unsigned front_winding:1; |
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397 | unsigned viewport_transform:1; |
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398 | unsigned pad0:3; |
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399 | unsigned sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ |
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400 | } sf5; |
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401 | |||
402 | struct |
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403 | { |
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404 | unsigned pad0:9; |
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405 | unsigned dest_org_vbias:4; |
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406 | unsigned dest_org_hbias:4; |
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407 | unsigned scissor:1; |
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408 | unsigned disable_2x2_trifilter:1; |
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409 | unsigned disable_zero_pix_trifilter:1; |
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410 | unsigned point_rast_rule:2; |
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411 | unsigned line_endcap_aa_region_width:2; |
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412 | unsigned line_width:4; |
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413 | unsigned fast_scissor_disable:1; |
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414 | unsigned cull_mode:2; |
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415 | unsigned aa_enable:1; |
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416 | } sf6; |
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417 | |||
418 | struct |
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419 | { |
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420 | unsigned point_size:11; |
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421 | unsigned use_point_size_state:1; |
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422 | unsigned subpixel_precision:1; |
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423 | unsigned sprite_point:1; |
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424 | unsigned pad0:10; |
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425 | unsigned aa_line_distance_mode:1; |
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426 | unsigned trifan_pv:2; |
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427 | unsigned linestrip_pv:2; |
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428 | unsigned tristrip_pv:2; |
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429 | unsigned line_last_pixel_enable:1; |
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430 | } sf7; |
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431 | |||
432 | }; |
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433 | |||
434 | struct gen6_scissor_rect |
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435 | { |
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436 | unsigned xmin:16; |
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437 | unsigned ymin:16; |
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438 | unsigned xmax:16; |
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439 | unsigned ymax:16; |
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440 | }; |
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441 | |||
442 | struct brw_gs_unit_state |
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443 | { |
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444 | struct thread0 thread0; |
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445 | struct thread1 thread1; |
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446 | struct thread2 thread2; |
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447 | struct thread3 thread3; |
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448 | |||
449 | struct |
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450 | { |
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451 | unsigned pad0:8; |
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452 | unsigned rendering_enable:1; /* for Ironlake */ |
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453 | unsigned pad4:1; |
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454 | unsigned stats_enable:1; |
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455 | unsigned nr_urb_entries:7; |
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456 | unsigned pad1:1; |
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457 | unsigned urb_entry_allocation_size:5; |
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458 | unsigned pad2:1; |
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459 | unsigned max_threads:5; |
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460 | unsigned pad3:2; |
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461 | } thread4; |
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462 | |||
463 | struct |
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464 | { |
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465 | unsigned sampler_count:3; |
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466 | unsigned pad0:2; |
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467 | unsigned sampler_state_pointer:27; |
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468 | } gs5; |
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469 | |||
470 | |||
471 | struct |
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472 | { |
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473 | unsigned max_vp_index:4; |
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474 | unsigned pad0:12; |
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475 | unsigned svbi_post_inc_value:10; |
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476 | unsigned pad1:1; |
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477 | unsigned svbi_post_inc_enable:1; |
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478 | unsigned svbi_payload:1; |
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479 | unsigned discard_adjaceny:1; |
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480 | unsigned reorder_enable:1; |
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481 | unsigned pad2:1; |
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482 | } gs6; |
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483 | }; |
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484 | |||
485 | |||
486 | struct brw_vs_unit_state |
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487 | { |
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488 | struct thread0 thread0; |
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489 | struct thread1 thread1; |
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490 | struct thread2 thread2; |
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491 | struct thread3 thread3; |
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492 | |||
493 | struct |
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494 | { |
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495 | unsigned pad0:10; |
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496 | unsigned stats_enable:1; |
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497 | unsigned nr_urb_entries:7; |
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498 | unsigned pad1:1; |
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499 | unsigned urb_entry_allocation_size:5; |
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500 | unsigned pad2:1; |
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501 | unsigned max_threads:6; |
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502 | unsigned pad3:1; |
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503 | } thread4; |
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504 | |||
505 | struct |
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506 | { |
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507 | unsigned sampler_count:3; |
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508 | unsigned pad0:2; |
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509 | unsigned sampler_state_pointer:27; |
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510 | } vs5; |
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511 | |||
512 | struct |
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513 | { |
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514 | unsigned vs_enable:1; |
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515 | unsigned vert_cache_disable:1; |
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516 | unsigned pad0:30; |
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517 | } vs6; |
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518 | }; |
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519 | |||
520 | |||
521 | struct brw_wm_unit_state |
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522 | { |
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523 | struct thread0 thread0; |
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524 | struct thread1 thread1; |
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525 | struct thread2 thread2; |
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526 | struct thread3 thread3; |
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527 | |||
528 | struct { |
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529 | unsigned stats_enable:1; |
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530 | unsigned depth_buffer_clear:1; |
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531 | unsigned sampler_count:3; |
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532 | unsigned sampler_state_pointer:27; |
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533 | } wm4; |
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534 | |||
535 | struct |
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536 | { |
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537 | unsigned enable_8_pix:1; |
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538 | unsigned enable_16_pix:1; |
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539 | unsigned enable_32_pix:1; |
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540 | unsigned enable_con_32_pix:1; |
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541 | unsigned enable_con_64_pix:1; |
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542 | unsigned pad0:1; |
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543 | |||
544 | /* These next four bits are for Ironlake+ */ |
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545 | unsigned fast_span_coverage_enable:1; |
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546 | unsigned depth_buffer_clear:1; |
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547 | unsigned depth_buffer_resolve_enable:1; |
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548 | unsigned hierarchical_depth_buffer_resolve_enable:1; |
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549 | |||
550 | unsigned legacy_global_depth_bias:1; |
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551 | unsigned line_stipple:1; |
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552 | unsigned depth_offset:1; |
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553 | unsigned polygon_stipple:1; |
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554 | unsigned line_aa_region_width:2; |
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555 | unsigned line_endcap_aa_region_width:2; |
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556 | unsigned early_depth_test:1; |
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557 | unsigned thread_dispatch_enable:1; |
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558 | unsigned program_uses_depth:1; |
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559 | unsigned program_computes_depth:1; |
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560 | unsigned program_uses_killpixel:1; |
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561 | unsigned legacy_line_rast: 1; |
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562 | unsigned transposed_urb_read_enable:1; |
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563 | unsigned max_threads:7; |
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564 | } wm5; |
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565 | |||
566 | float global_depth_offset_constant; |
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567 | float global_depth_offset_scale; |
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568 | |||
569 | /* for Ironlake only */ |
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570 | struct { |
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571 | unsigned pad0:1; |
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572 | unsigned grf_reg_count_1:3; |
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573 | unsigned pad1:2; |
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574 | unsigned kernel_start_pointer_1:26; |
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575 | } wm8; |
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576 | |||
577 | struct { |
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578 | unsigned pad0:1; |
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579 | unsigned grf_reg_count_2:3; |
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580 | unsigned pad1:2; |
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581 | unsigned kernel_start_pointer_2:26; |
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582 | } wm9; |
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583 | |||
584 | struct { |
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585 | unsigned pad0:1; |
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586 | unsigned grf_reg_count_3:3; |
||
587 | unsigned pad1:2; |
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588 | unsigned kernel_start_pointer_3:26; |
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589 | } wm10; |
||
590 | }; |
||
591 | |||
592 | struct gen5_sampler_default_color { |
||
593 | uint8_t ub[4]; |
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594 | float f[4]; |
||
595 | uint16_t hf[4]; |
||
596 | uint16_t us[4]; |
||
597 | int16_t s[4]; |
||
598 | uint8_t b[4]; |
||
599 | }; |
||
600 | |||
601 | struct brw_clipper_viewport |
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602 | { |
||
603 | float xmin; |
||
604 | float xmax; |
||
605 | float ymin; |
||
606 | float ymax; |
||
607 | }; |
||
608 | |||
609 | struct brw_cc_viewport |
||
610 | { |
||
611 | float min_depth; |
||
612 | float max_depth; |
||
613 | }; |
||
614 | |||
615 | struct brw_sf_viewport |
||
616 | { |
||
617 | struct { |
||
618 | float m00; |
||
619 | float m11; |
||
620 | float m22; |
||
621 | float m30; |
||
622 | float m31; |
||
623 | float m32; |
||
624 | } viewport; |
||
625 | |||
626 | /* scissor coordinates are inclusive */ |
||
627 | struct { |
||
628 | int16_t xmin; |
||
629 | int16_t ymin; |
||
630 | int16_t xmax; |
||
631 | int16_t ymax; |
||
632 | } scissor; |
||
633 | }; |
||
634 | |||
635 | struct gen6_sf_viewport { |
||
636 | float m00; |
||
637 | float m11; |
||
638 | float m22; |
||
639 | float m30; |
||
640 | float m31; |
||
641 | float m32; |
||
642 | |||
643 | unsigned pad0[2]; |
||
644 | }; |
||
645 | |||
646 | struct gen7_sf_clip_viewport { |
||
647 | struct { |
||
648 | float m00; |
||
649 | float m11; |
||
650 | float m22; |
||
651 | float m30; |
||
652 | float m31; |
||
653 | float m32; |
||
654 | } viewport; |
||
655 | |||
656 | unsigned pad0[2]; |
||
657 | |||
658 | struct { |
||
659 | float xmin; |
||
660 | float xmax; |
||
661 | float ymin; |
||
662 | float ymax; |
||
663 | } guardband; |
||
664 | |||
665 | float pad1[4]; |
||
666 | }; |
||
667 | |||
668 | #endif |