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5564 | serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright 2006 VMware, Inc. |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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21 | * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR |
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22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | |||
28 | /* Provide additional functionality on top of bufmgr buffers: |
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29 | * - 2d semantics and blit operations |
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30 | * - refcounting of buffers for multiple images in a buffer. |
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31 | * - refcounting of buffer mappings. |
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32 | * - some logic for moving the buffers to the best memory pools for |
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33 | * given operations. |
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34 | * |
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35 | * Most of this is to make it easier to implement the fixed-layout |
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36 | * mipmap tree required by intel hardware in the face of GL's |
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37 | * programming interface where each image can be specifed in random |
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38 | * order and it isn't clear what layout the tree should have until the |
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39 | * last moment. |
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40 | */ |
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41 | |||
42 | #include |
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43 | #include |
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44 | |||
45 | #include "main/hash.h" |
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46 | #include "intel_context.h" |
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47 | #include "intel_regions.h" |
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48 | #include "intel_blit.h" |
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49 | #include "intel_buffer_objects.h" |
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50 | #include "intel_bufmgr.h" |
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51 | #include "intel_batchbuffer.h" |
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52 | |||
53 | #define FILE_DEBUG_FLAG DEBUG_REGION |
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54 | |||
55 | /* This should be set to the maximum backtrace size desired. |
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56 | * Set it to 0 to disable backtrace debugging. |
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57 | */ |
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58 | #define DEBUG_BACKTRACE_SIZE 0 |
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59 | |||
60 | #if DEBUG_BACKTRACE_SIZE == 0 |
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61 | /* Use the standard debug output */ |
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62 | #define _DBG(...) DBG(__VA_ARGS__) |
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63 | #else |
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64 | /* Use backtracing debug output */ |
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65 | #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);} |
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66 | |||
67 | /* Backtracing debug support */ |
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68 | #include |
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69 | |||
70 | static void |
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71 | debug_backtrace(void) |
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72 | { |
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73 | void *trace[DEBUG_BACKTRACE_SIZE]; |
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74 | char **strings = NULL; |
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75 | int traceSize; |
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76 | register int i; |
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77 | |||
78 | traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE); |
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79 | strings = backtrace_symbols(trace, traceSize); |
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80 | if (strings == NULL) { |
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81 | DBG("no backtrace:"); |
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82 | return; |
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83 | } |
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84 | |||
85 | /* Spit out all the strings with a colon separator. Ignore |
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86 | * the first, since we don't really care about the call |
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87 | * to debug_backtrace() itself. Skip until the final "/" in |
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88 | * the trace to avoid really long lines. |
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89 | */ |
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90 | for (i = 1; i < traceSize; i++) { |
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91 | char *p = strings[i], *slash = strings[i]; |
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92 | while (*p) { |
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93 | if (*p++ == '/') { |
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94 | slash = p; |
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95 | } |
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96 | } |
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97 | |||
98 | DBG("%s:", slash); |
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99 | } |
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100 | |||
101 | /* Free up the memory, and we're done */ |
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102 | free(strings); |
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103 | } |
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104 | |||
105 | #endif |
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106 | |||
107 | static struct intel_region * |
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108 | intel_region_alloc_internal(struct intel_screen *screen, |
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109 | GLuint cpp, |
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110 | GLuint width, GLuint height, GLuint pitch, |
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111 | uint32_t tiling, drm_intel_bo *buffer) |
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112 | { |
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113 | struct intel_region *region; |
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114 | |||
115 | region = calloc(sizeof(*region), 1); |
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116 | if (region == NULL) |
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117 | return region; |
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118 | |||
119 | region->cpp = cpp; |
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120 | region->width = width; |
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121 | region->height = height; |
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122 | region->pitch = pitch; |
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123 | region->refcount = 1; |
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124 | region->bo = buffer; |
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125 | region->tiling = tiling; |
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126 | |||
127 | _DBG("%s <-- %p\n", __func__, region); |
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128 | return region; |
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129 | } |
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130 | |||
131 | struct intel_region * |
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132 | intel_region_alloc(struct intel_screen *screen, |
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133 | uint32_t tiling, |
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134 | GLuint cpp, GLuint width, GLuint height, |
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135 | bool expect_accelerated_upload) |
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136 | { |
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137 | drm_intel_bo *buffer; |
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138 | unsigned long flags = 0; |
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139 | unsigned long aligned_pitch; |
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140 | struct intel_region *region; |
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141 | |||
142 | if (expect_accelerated_upload) |
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143 | flags |= BO_ALLOC_FOR_RENDER; |
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144 | |||
145 | buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region", |
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146 | width, height, cpp, |
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147 | &tiling, &aligned_pitch, flags); |
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148 | if (buffer == NULL) |
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149 | return NULL; |
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150 | |||
151 | region = intel_region_alloc_internal(screen, cpp, width, height, |
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152 | aligned_pitch, tiling, buffer); |
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153 | if (region == NULL) { |
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154 | drm_intel_bo_unreference(buffer); |
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155 | return NULL; |
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156 | } |
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157 | |||
158 | return region; |
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159 | } |
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160 | |||
161 | bool |
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162 | intel_region_flink(struct intel_region *region, uint32_t *name) |
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163 | { |
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164 | if (region->name == 0) { |
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165 | if (drm_intel_bo_flink(region->bo, ®ion->name)) |
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166 | return false; |
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167 | } |
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168 | |||
169 | *name = region->name; |
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170 | |||
171 | return true; |
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172 | } |
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173 | |||
174 | struct intel_region * |
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175 | intel_region_alloc_for_handle(struct intel_screen *screen, |
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176 | GLuint cpp, |
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177 | GLuint width, GLuint height, GLuint pitch, |
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178 | GLuint handle, const char *name) |
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179 | { |
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180 | struct intel_region *region; |
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181 | drm_intel_bo *buffer; |
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182 | int ret; |
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183 | uint32_t bit_6_swizzle, tiling; |
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184 | |||
185 | buffer = intel_bo_gem_create_from_name(screen->bufmgr, name, handle); |
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186 | if (buffer == NULL) |
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187 | return NULL; |
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188 | ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); |
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189 | if (ret != 0) { |
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190 | fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", |
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191 | handle, name, strerror(-ret)); |
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192 | drm_intel_bo_unreference(buffer); |
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193 | return NULL; |
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194 | } |
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195 | |||
196 | region = intel_region_alloc_internal(screen, cpp, |
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197 | width, height, pitch, tiling, buffer); |
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198 | if (region == NULL) { |
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199 | drm_intel_bo_unreference(buffer); |
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200 | return NULL; |
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201 | } |
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202 | |||
203 | region->name = handle; |
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204 | |||
205 | return region; |
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206 | } |
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207 | |||
208 | struct intel_region * |
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209 | intel_region_alloc_for_fd(struct intel_screen *screen, |
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210 | GLuint cpp, |
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211 | GLuint width, GLuint height, GLuint pitch, |
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212 | GLuint size, |
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213 | int fd, const char *name) |
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214 | { |
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215 | struct intel_region *region; |
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216 | drm_intel_bo *buffer; |
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217 | int ret; |
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218 | uint32_t bit_6_swizzle, tiling; |
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219 | |||
220 | buffer = drm_intel_bo_gem_create_from_prime(screen->bufmgr, fd, size); |
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221 | if (buffer == NULL) |
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222 | return NULL; |
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223 | ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); |
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224 | if (ret != 0) { |
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225 | fprintf(stderr, "Couldn't get tiling of buffer (%s): %s\n", |
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226 | name, strerror(-ret)); |
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227 | drm_intel_bo_unreference(buffer); |
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228 | return NULL; |
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229 | } |
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230 | |||
231 | region = intel_region_alloc_internal(screen, cpp, |
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232 | width, height, pitch, tiling, buffer); |
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233 | if (region == NULL) { |
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234 | drm_intel_bo_unreference(buffer); |
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235 | return NULL; |
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236 | } |
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237 | |||
238 | return region; |
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239 | } |
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240 | |||
241 | void |
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242 | intel_region_reference(struct intel_region **dst, struct intel_region *src) |
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243 | { |
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244 | _DBG("%s: %p(%d) -> %p(%d)\n", __func__, |
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245 | *dst, *dst ? (*dst)->refcount : 0, src, src ? src->refcount : 0); |
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246 | |||
247 | if (src != *dst) { |
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248 | if (*dst) |
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249 | intel_region_release(dst); |
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250 | |||
251 | if (src) |
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252 | src->refcount++; |
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253 | *dst = src; |
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254 | } |
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255 | } |
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256 | |||
257 | void |
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258 | intel_region_release(struct intel_region **region_handle) |
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259 | { |
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260 | struct intel_region *region = *region_handle; |
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261 | |||
262 | if (region == NULL) { |
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263 | _DBG("%s NULL\n", __func__); |
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264 | return; |
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265 | } |
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266 | |||
267 | _DBG("%s %p %d\n", __func__, region, region->refcount - 1); |
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268 | |||
269 | assert(region->refcount > 0); |
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270 | region->refcount--; |
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271 | |||
272 | if (region->refcount == 0) { |
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273 | drm_intel_bo_unreference(region->bo); |
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274 | |||
275 | free(region); |
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276 | } |
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277 | *region_handle = NULL; |
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278 | } |
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279 | |||
280 | /** |
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281 | * This function computes masks that may be used to select the bits of the X |
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282 | * and Y coordinates that indicate the offset within a tile. If the region is |
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283 | * untiled, the masks are set to 0. |
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284 | */ |
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285 | void |
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286 | intel_region_get_tile_masks(struct intel_region *region, |
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287 | uint32_t *mask_x, uint32_t *mask_y, |
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288 | bool map_stencil_as_y_tiled) |
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289 | { |
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290 | int cpp = region->cpp; |
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291 | uint32_t tiling = region->tiling; |
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292 | |||
293 | if (map_stencil_as_y_tiled) |
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294 | tiling = I915_TILING_Y; |
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295 | |||
296 | switch (tiling) { |
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297 | default: |
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298 | assert(false); |
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299 | case I915_TILING_NONE: |
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300 | *mask_x = *mask_y = 0; |
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301 | break; |
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302 | case I915_TILING_X: |
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303 | *mask_x = 512 / cpp - 1; |
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304 | *mask_y = 7; |
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305 | break; |
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306 | case I915_TILING_Y: |
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307 | *mask_x = 128 / cpp - 1; |
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308 | *mask_y = 31; |
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309 | break; |
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310 | } |
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311 | } |
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312 | |||
313 | /** |
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314 | * Compute the offset (in bytes) from the start of the region to the given x |
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315 | * and y coordinate. For tiled regions, caller must ensure that x and y are |
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316 | * multiples of the tile size. |
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317 | */ |
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318 | uint32_t |
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319 | intel_region_get_aligned_offset(struct intel_region *region, uint32_t x, |
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320 | uint32_t y, bool map_stencil_as_y_tiled) |
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321 | { |
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322 | int cpp = region->cpp; |
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323 | uint32_t pitch = region->pitch; |
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324 | uint32_t tiling = region->tiling; |
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325 | |||
326 | if (map_stencil_as_y_tiled) { |
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327 | tiling = I915_TILING_Y; |
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328 | |||
329 | /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile |
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330 | * gets transformed into a 32-high Y-tile. Accordingly, the pitch of |
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331 | * the resulting region is twice the pitch of the original region, since |
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332 | * each row in the Y-tiled view corresponds to two rows in the actual |
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333 | * W-tiled surface. So we need to correct the pitch before computing |
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334 | * the offsets. |
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335 | */ |
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336 | pitch *= 2; |
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337 | } |
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338 | |||
339 | switch (tiling) { |
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340 | default: |
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341 | assert(false); |
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342 | case I915_TILING_NONE: |
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343 | return y * pitch + x * cpp; |
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344 | case I915_TILING_X: |
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345 | assert((x % (512 / cpp)) == 0); |
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346 | assert((y % 8) == 0); |
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347 | return y * pitch + x / (512 / cpp) * 4096; |
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348 | case I915_TILING_Y: |
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349 | assert((x % (128 / cpp)) == 0); |
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350 | assert((y % 32) == 0); |
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351 | return y * pitch + x / (128 / cpp) * 4096; |
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352 | } |
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353 | }-->> |