Rev 4359 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
4315 | Serge | 1 | |
2 | #include |
||
3 | #include |
||
4 | |||
5 | |||
6 | //#include "xf86.h" |
||
7 | #include "uxa/intel.h" |
||
8 | #include "i830_reg.h" |
||
9 | #include "i965_reg.h" |
||
10 | |||
11 | |||
12 | #include "brw_defines.h" |
||
13 | #include "brw_structs.h" |
||
14 | |||
15 | |||
16 | #include |
||
17 | #include |
||
18 | |||
19 | |||
20 | #define PictOpSrc 1 |
||
21 | #define PictOpDst 2 |
||
22 | #define PictOpOver 3 |
||
23 | #define PictOpOverReverse 4 |
||
24 | #define PictOpIn 5 |
||
25 | #define PictOpInReverse 6 |
||
26 | #define PictOpOut 7 |
||
27 | #define PictOpOutReverse 8 |
||
28 | #define PictOpAtop 9 |
||
29 | #define PictOpAtopReverse 10 |
||
30 | #define PictOpXor 11 |
||
31 | #define PictOpAdd 12 |
||
32 | #define PictOpSaturate 13 |
||
33 | #define PictOpMaximum 13 |
||
34 | |||
35 | |||
36 | |||
37 | |||
38 | __LOCK_INIT_RECURSIVE(, __uxa_lock); |
||
39 | |||
40 | |||
41 | |||
42 | |||
43 | { |
||
44 | struct list entry; |
||
45 | uint32_t width; |
||
46 | uint32_t height; |
||
47 | void *data; |
||
48 | uint32_t pitch; |
||
49 | drm_intel_bo *bo; |
||
50 | uint32_t bo_size; |
||
51 | uint32_t flags; |
||
52 | }surface_t; |
||
53 | |||
54 | |||
55 | |||
56 | |||
57 | |||
58 | |||
59 | |||
60 | |||
61 | |||
62 | |||
63 | { |
||
64 | intel_screen_private *intel = intel_get_screen_private(); |
||
65 | |||
66 | |||
67 | intel->vertex_flush(intel); |
||
68 | |||
69 | |||
70 | } |
||
71 | |||
72 | |||
73 | { |
||
74 | struct intel_screen_private *intel = intel_get_screen_private(); |
||
75 | drm_intel_bo *bo; |
||
76 | surface_t *sf; |
||
77 | unsigned int size; |
||
78 | |||
79 | |||
80 | |||
81 | |||
82 | list_for_each_entry(sf, &sf_list, entry) |
||
83 | { |
||
84 | if (sf->bo->handle == handle) |
||
85 | { |
||
86 | bitmap->handle = (uint32_t)sf; |
||
87 | break; |
||
88 | } |
||
89 | } |
||
90 | __lock_release_recursive(__uxa_lock); |
||
91 | |||
92 | |||
93 | return 0; |
||
94 | |||
95 | |||
96 | if(sf == NULL) |
||
97 | goto err_1; |
||
98 | |||
99 | |||
100 | |||
101 | |||
102 | |||
103 | |||
104 | sf->height = bitmap->height; |
||
105 | sf->data = NULL; |
||
106 | sf->pitch = bitmap->pitch; |
||
107 | sf->bo = bo; |
||
108 | sf->bo_size = size; |
||
109 | sf->flags = bitmap->flags; |
||
110 | |||
111 | |||
112 | |||
113 | |||
114 | |||
115 | |||
116 | |||
117 | |||
118 | }; |
||
119 | |||
120 | |||
121 | { |
||
122 | sna_bitmap_from_handle(bitmap, handle); |
||
123 | }; |
||
124 | |||
125 | |||
126 | |||
127 | int w, int h, int src_x, int src_y) |
||
128 | { |
||
129 | // DBG("%s\n", __FUNCTION__); |
||
4348 | Serge | 130 | |
131 | |||
4315 | Serge | 132 | struct intel_pixmap privSrc; |
133 | struct _Picture pictSrc, pictDst; |
||
134 | struct intel_screen_private *intel = intel_get_screen_private(); |
||
135 | |||
136 | |||
137 | |||
138 | |||
139 | |||
140 | |||
141 | get_proc_info(proc_info); |
||
142 | winx = *(uint32_t*)(proc_info+34); |
||
143 | winy = *(uint32_t*)(proc_info+38); |
||
144 | |||
145 | |||
146 | memset(&pixMask, 0, sizeof(pixMask)); |
||
147 | memset(&privSrc, 0, sizeof(pixSrc)); |
||
148 | |||
149 | |||
150 | memset(&pictDst, 0, sizeof(pictDst)); |
||
151 | |||
152 | |||
153 | pixSrc.drawable.width = sf->width; |
||
154 | pixSrc.drawable.height = sf->height; |
||
155 | pixSrc.devKind = sf->pitch; |
||
156 | pixSrc.private = &privSrc; |
||
157 | |||
158 | |||
159 | privSrc.bo = sf->bo; |
||
160 | privSrc.stride = sf->pitch; |
||
161 | privSrc.tiling = I915_TILING_X; |
||
162 | |||
163 | |||
164 | pictSrc.filter = PictFilterNearest; |
||
165 | pictSrc.repeatType = RepeatNone; |
||
166 | |||
167 | |||
168 | pictDst.filter = PictFilterNearest; |
||
169 | pictDst.repeatType = RepeatNone; |
||
170 | |||
171 | |||
172 | |||
173 | |||
174 | &pixSrc, NULL, &fb_pixmap); |
||
175 | |||
176 | |||
177 | dst_x+winx, dst_y+winy, w, h); |
||
4348 | Serge | 178 | |
4315 | Serge | 179 | |
180 | |||
181 | |||
182 | |||
183 | |||
4348 | Serge | 184 | |
185 | |||
4315 | Serge | 186 | }; |
187 | |||
188 | |||
189 | |||
190 | { |
||
191 | struct drm_i915_fb_info fb; |
||
192 | static struct intel_pixmap ipix; |
||
193 | int ret; |
||
194 | |||
195 | |||
196 | |||
197 | |||
198 | if( ret != 0 ) |
||
199 | return ret; |
||
200 | |||
201 | |||
202 | if(intel->front_buffer == NULL) |
||
203 | return -1; |
||
204 | |||
205 | |||
206 | list_init(&ipix.batch); |
||
207 | ipix.stride = fb.pitch; |
||
208 | ipix.tiling = fb.tiling; |
||
209 | ipix.pinned = PIN_SCANOUT; |
||
210 | |||
211 | |||
212 | printf("size %d, offset %d handle %d\n",ipix.bo->size, ipix.bo->offset, ipix.bo->handle); |
||
213 | |||
214 | |||
215 | fb_pixmap.drawable.width = fb.width; |
||
216 | fb_pixmap.drawable.height = fb.height; |
||
217 | fb_pixmap.devKind = fb.pitch; |
||
218 | fb_pixmap.private = &ipix; |
||
219 | |||
220 | |||
221 | } |
||
222 | |||
223 | |||
224 | { |
||
225 | struct drm_i915_fb_info fb; |
||
226 | struct intel_pixmap *ipix; |
||
227 | size_t size; |
||
228 | int ret; |
||
229 | |||
230 | |||
4348 | Serge | 231 | |
232 | |||
4315 | Serge | 233 | if( ret != 0 ) |
234 | return ret; |
||
235 | |||
236 | |||
237 | |||
4348 | Serge | 238 | |
239 | ipix->stride = fb.pitch; |
||
4315 | Serge | 240 | ipix->tiling = fb.tiling; |
241 | |||
242 | |||
243 | fb_pixmap.drawable.height = fb.height; |
||
244 | fb_pixmap.devKind = fb.pitch; |
||
245 | |||
246 | |||
247 | }; |
||
248 | |||
249 | |||
250 | { |
||
251 | static struct pci_device device; |
||
252 | struct intel_screen_private *intel = intel_get_screen_private(); |
||
253 | |||
254 | |||
255 | int caps = 0; |
||
256 | |||
257 | |||
258 | |||
259 | |||
260 | |||
261 | |||
262 | goto done; |
||
263 | |||
264 | |||
265 | io.io_code = SRV_GET_PCI_INFO; |
||
266 | io.input = &device; |
||
267 | io.inp_size = sizeof(device); |
||
268 | io.output = NULL; |
||
269 | io.out_size = 0; |
||
270 | |||
271 | |||
272 | goto err1; |
||
273 | |||
274 | |||
275 | if (intel == NULL) |
||
276 | goto err1; |
||
277 | |||
278 | |||
279 | |||
280 | |||
281 | memset(intel, 0, sizeof(*intel)); |
||
282 | |||
283 | |||
284 | |||
285 | |||
286 | intel->info = intel_detect_chipset(intel->PciInfo); |
||
287 | intel->scrn = service; |
||
288 | |||
289 | |||
290 | if(intel->bufmgr == NULL) |
||
291 | { |
||
292 | printf("Memory manager initialization failed\n"); |
||
293 | goto err1; |
||
294 | }; |
||
295 | |||
296 | |||
4348 | Serge | 297 | |
298 | |||
299 | intel->wa_scratch_bo = |
||
300 | drm_intel_bo_alloc(intel->bufmgr, "wa scratch", |
||
301 | 4096, 4096); |
||
302 | } |
||
303 | |||
304 | |||
4315 | Serge | 305 | goto err1; |
306 | |||
307 | |||
308 | |||
309 | |||
310 | gen4_render_state_init(); |
||
311 | |||
312 | |||
313 | printf("Hardware acceleration initialization failed\n"); |
||
314 | goto err1; |
||
315 | } |
||
316 | |||
317 | |||
318 | |||
319 | |||
320 | |||
321 | |||
322 | // caps = sna_device->render.caps; |
||
323 | |||
324 | |||
325 | __lock_release_recursive(__uxa_lock); |
||
326 | |||
327 | |||
328 | return caps; |
||
329 | } |
||
330 | |||
331 | |||
332 | |||
333 | |||
334 | gen6_context_switch(intel_screen_private *intel, |
||
335 | int new_mode) |
||
336 | { |
||
337 | intel_batch_submit(intel->scrn); |
||
338 | } |
||
339 | |||
340 | |||
341 | gen5_context_switch(intel_screen_private *intel, |
||
342 | int new_mode) |
||
343 | { |
||
344 | /* Ironlake has a limitation that a 3D or Media command can't |
||
345 | * be the first command after a BLT, unless it's |
||
346 | * non-pipelined. Instead of trying to track it and emit a |
||
347 | * command at the right time, we just emit a dummy |
||
348 | * non-pipelined 3D instruction after each blit. |
||
349 | */ |
||
350 | |||
351 | |||
352 | OUT_BATCH(MI_FLUSH | |
||
353 | MI_STATE_INSTRUCTION_CACHE_FLUSH | |
||
354 | MI_INHIBIT_RENDER_CACHE_FLUSH); |
||
355 | } else { |
||
356 | OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16); |
||
357 | OUT_BATCH(0); |
||
358 | } |
||
359 | } |
||
360 | |||
361 | |||
362 | gen4_context_switch(intel_screen_private *intel, |
||
363 | int new_mode) |
||
364 | { |
||
365 | if (new_mode == I915_EXEC_BLT) { |
||
366 | OUT_BATCH(MI_FLUSH | |
||
367 | MI_STATE_INSTRUCTION_CACHE_FLUSH | |
||
368 | MI_INHIBIT_RENDER_CACHE_FLUSH); |
||
369 | } |
||
370 | } |
||
371 | |||
372 | |||
373 | intel_limits_init(intel_screen_private *intel) |
||
374 | { |
||
375 | /* Limits are described in the BLT engine chapter under Graphics Data Size |
||
376 | * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO, |
||
377 | * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO. |
||
378 | * |
||
379 | * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768. |
||
380 | * |
||
381 | * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled. |
||
382 | * i965 limits 3D surface to 4kB-aligned offset if tiled. |
||
383 | * i965 limits 3D surfaces to w,h of ?,8192. |
||
384 | * i965 limits 3D surface to pitch of 1B - 128kB. |
||
385 | * i965 limits 3D surface pitch alignment to 1 or 2 times the element size. |
||
386 | * i965 limits 3D surface pitch alignment to 512B if tiled. |
||
387 | * i965 limits 3D destination drawing rect to w,h of 8192,8192. |
||
388 | * |
||
389 | * i915 limits 3D textures to 4B-aligned offset if un-tiled. |
||
390 | * i915 limits 3D textures to ~4kB-aligned offset if tiled. |
||
391 | * i915 limits 3D textures to width,height of 2048,2048. |
||
392 | * i915 limits 3D textures to pitch of 16B - 8kB, in dwords. |
||
393 | * i915 limits 3D destination to ~4kB-aligned offset if tiled. |
||
394 | * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled. |
||
395 | * i915 limits 3D destination to pitch 64B-aligned if used with depth. |
||
396 | * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled. |
||
397 | * i915 limits 3D destination to POT aligned pitch if tiled. |
||
398 | * i915 limits 3D destination drawing rect to w,h of 2048,2048. |
||
399 | * |
||
400 | * i845 limits 3D textures to 4B-aligned offset if un-tiled. |
||
401 | * i845 limits 3D textures to ~4kB-aligned offset if tiled. |
||
402 | * i845 limits 3D textures to width,height of 2048,2048. |
||
403 | * i845 limits 3D textures to pitch of 4B - 8kB, in dwords. |
||
404 | * i845 limits 3D destination to 4B-aligned offset if un-tiled. |
||
405 | * i845 limits 3D destination to ~4kB-aligned offset if tiled. |
||
406 | * i845 limits 3D destination to pitch of 8B - 8kB, in dwords. |
||
407 | * i845 limits 3D destination drawing rect to w,h of 2048,2048. |
||
408 | * |
||
409 | * For the tiled issues, the only tiled buffer we draw to should be |
||
410 | * the front, which will have an appropriate pitch/offset already set up, |
||
411 | * so UXA doesn't need to worry. |
||
412 | */ |
||
413 | if (INTEL_INFO(intel)->gen >= 040) { |
||
414 | intel->accel_pixmap_offset_alignment = 4 * 2; |
||
415 | intel->accel_max_x = 8192; |
||
416 | intel->accel_max_y = 8192; |
||
417 | } else { |
||
418 | intel->accel_pixmap_offset_alignment = 4; |
||
419 | intel->accel_max_x = 2048; |
||
420 | intel->accel_max_y = 2048; |
||
421 | } |
||
422 | } |
||
423 | |||
424 | |||
425 | |||
426 | { |
||
427 | intel_screen_private *intel = intel_get_screen_private(); |
||
428 | |||
429 | |||
430 | |||
431 | |||
432 | intel->vertex_count = 0; |
||
433 | intel->vertex_offset = 0; |
||
434 | intel->vertex_used = 0; |
||
435 | intel->floats_per_vertex = 0; |
||
436 | intel->last_floats_per_vertex = 0; |
||
437 | intel->vertex_bo = NULL; |
||
438 | intel->surface_used = 0; |
||
439 | intel->surface_reloc = 0; |
||
440 | |||
441 | |||
442 | intel->uxa_driver->check_composite = i965_check_composite; |
||
443 | intel->uxa_driver->check_composite_texture = i965_check_composite_texture; |
||
444 | intel->uxa_driver->prepare_composite = i965_prepare_composite; |
||
445 | intel->uxa_driver->composite = i965_composite; |
||
446 | intel->uxa_driver->done_composite = i830_done_composite; |
||
447 | */ |
||
448 | intel->vertex_flush = i965_vertex_flush; |
||
449 | intel->batch_flush = i965_batch_flush; |
||
450 | intel->batch_commit_notify = i965_batch_commit_notify; |
||
451 | |||
452 | |||
453 | intel->context_switch = gen4_context_switch; |
||
454 | } else if (IS_GEN5(intel)) { |
||
455 | intel->context_switch = gen5_context_switch; |
||
456 | } else { |
||
457 | intel->context_switch = gen6_context_switch; |
||
458 | } |
||
459 | |||
460 | |||
461 | } |
||
462 | |||
463 | |||
464 | |||
465 | .gen = -1, |
||
466 | }; |
||
467 | |||
468 | |||
469 | .gen = 030, |
||
470 | }; |
||
471 | static const struct intel_device_info intel_i945_info = { |
||
472 | .gen = 031, |
||
473 | }; |
||
474 | |||
475 | |||
476 | .gen = 033, |
||
477 | }; |
||
478 | |||
479 | |||
480 | .gen = 040, |
||
481 | }; |
||
482 | |||
483 | |||
484 | .gen = 045, |
||
485 | }; |
||
486 | |||
487 | |||
488 | .gen = 050, |
||
489 | }; |
||
490 | |||
491 | |||
492 | .gen = 060, |
||
493 | }; |
||
494 | |||
495 | |||
496 | .gen = 070, |
||
497 | }; |
||
498 | |||
499 | |||
500 | .gen = 071, |
||
501 | }; |
||
502 | |||
503 | |||
504 | .gen = 075, |
||
505 | }; |
||
506 | |||
507 | |||
508 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
||
509 | |||
510 | |||
511 | |||
512 | |||
513 | |||
514 | INTEL_I915GM_IDS(&intel_i915_info), |
||
515 | INTEL_I945G_IDS(&intel_i945_info), |
||
516 | INTEL_I945GM_IDS(&intel_i945_info), |
||
517 | |||
518 | |||
519 | INTEL_PINEVIEW_IDS(&intel_g33_info), |
||
520 | |||
521 | |||
522 | INTEL_I965GM_IDS(&intel_i965_info), |
||
523 | |||
524 | |||
525 | INTEL_GM45_IDS(&intel_g4x_info), |
||
526 | |||
527 | |||
528 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_info), |
||
529 | |||
530 | |||
531 | INTEL_SNB_M_IDS(&intel_sandybridge_info), |
||
532 | |||
533 | |||
534 | INTEL_IVB_M_IDS(&intel_ivybridge_info), |
||
535 | |||
536 | |||
537 | INTEL_HSW_M_IDS(&intel_haswell_info), |
||
538 | |||
539 | |||
540 | INTEL_VLV_M_IDS(&intel_valleyview_info), |
||
541 | |||
542 | |||
543 | |||
544 | |||
545 | }; |
||
546 | |||
547 | |||
548 | { |
||
549 | while(list->device_id) |
||
550 | { |
||
551 | if(dev==list->device_id) |
||
552 | return list; |
||
553 | list++; |
||
554 | } |
||
555 | return NULL; |
||
556 | } |
||
557 | |||
558 | |||
559 | |||
560 | intel_detect_chipset(struct pci_device *pci) |
||
561 | { |
||
562 | const struct pci_id_match *ent = NULL; |
||
563 | |||
564 | |||
565 | |||
566 | |||
567 | return (const struct intel_device_info*)ent->match_data; |
||
568 | else |
||
569 | return &intel_generic_info; |
||
570 | }><>><>><> |
||
571 |