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Rev | Author | Line No. | Line |
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4304 | Serge | 1 | /************************************************************************** |
2 | |||
3 | Copyright 2001 VA Linux Systems Inc., Fremont, California. |
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4 | Copyright © 2002 by David Dawes |
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5 | |||
6 | All Rights Reserved. |
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7 | |||
8 | Permission is hereby granted, free of charge, to any person obtaining a |
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9 | copy of this software and associated documentation files (the "Software"), |
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10 | to deal in the Software without restriction, including without limitation |
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11 | on the rights to use, copy, modify, merge, publish, distribute, sub |
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12 | license, and/or sell copies of the Software, and to permit persons to whom |
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13 | the Software is furnished to do so, subject to the following conditions: |
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14 | |||
15 | The above copyright notice and this permission notice (including the next |
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16 | paragraph) shall be included in all copies or substantial portions of the |
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17 | Software. |
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18 | |||
19 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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20 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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21 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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22 | THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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23 | DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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24 | OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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25 | USE OR OTHER DEALINGS IN THE SOFTWARE. |
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26 | |||
27 | **************************************************************************/ |
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28 | |||
29 | /* |
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30 | * Authors: Jeff Hartmann |
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31 | * Abraham van der Merwe |
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32 | * David Dawes |
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33 | * Alan Hourihane |
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34 | */ |
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35 | |||
36 | #ifdef HAVE_CONFIG_H |
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37 | #include "config.h" |
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38 | #endif |
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39 | |||
40 | #include |
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41 | #include |
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42 | #include "i915_pciids.h" |
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43 | |||
44 | #include "compiler.h" |
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45 | #include "sna.h" |
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46 | |||
4315 | Serge | 47 | #include |
48 | #include |
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49 | |||
4304 | Serge | 50 | #define to_surface(x) (surface_t*)((x)->handle) |
51 | |||
4368 | Serge | 52 | typedef struct { |
53 | int l; |
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54 | int t; |
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55 | int r; |
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56 | int b; |
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57 | } rect_t; |
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58 | |||
4304 | Serge | 59 | static struct sna_fb sna_fb; |
60 | static int tls_mask; |
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61 | |||
62 | int tls_alloc(void); |
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63 | |||
64 | static inline void *tls_get(int key) |
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65 | { |
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66 | void *val; |
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67 | __asm__ __volatile__( |
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68 | "movl %%fs:(%1), %0" |
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69 | :"=r"(val) |
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70 | :"r"(key)); |
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71 | |||
72 | return val; |
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73 | }; |
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74 | |||
75 | static inline int |
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76 | tls_set(int key, const void *ptr) |
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77 | { |
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78 | if(!(key & 3)) |
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79 | { |
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80 | __asm__ __volatile__( |
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81 | "movl %0, %%fs:(%1)" |
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82 | ::"r"(ptr),"r"(key)); |
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83 | return 0; |
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84 | } |
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85 | else return -1; |
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86 | } |
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87 | |||
88 | |||
89 | |||
90 | |||
91 | int kgem_init_fb(struct kgem *kgem, struct sna_fb *fb); |
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92 | int kgem_update_fb(struct kgem *kgem, struct sna_fb *fb); |
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93 | uint32_t kgem_surface_size(struct kgem *kgem,bool relaxed_fencing, |
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94 | unsigned flags, uint32_t width, uint32_t height, |
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95 | uint32_t bpp, uint32_t tiling, uint32_t *pitch); |
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96 | struct kgem_bo *kgem_bo_from_handle(struct kgem *kgem, int handle, |
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97 | int pitch, int height); |
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98 | |||
99 | void kgem_close_batches(struct kgem *kgem); |
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100 | void sna_bo_destroy(struct kgem *kgem, struct kgem_bo *bo); |
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101 | |||
102 | |||
103 | static bool sna_solid_cache_init(struct sna *sna); |
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104 | |||
105 | struct sna *sna_device; |
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106 | |||
107 | __LOCK_INIT_RECURSIVE(, __sna_lock); |
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108 | |||
109 | static void no_render_reset(struct sna *sna) |
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110 | { |
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111 | (void)sna; |
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112 | } |
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113 | |||
114 | static void no_render_flush(struct sna *sna) |
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115 | { |
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116 | (void)sna; |
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117 | } |
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118 | |||
119 | static void |
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120 | no_render_context_switch(struct kgem *kgem, |
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121 | int new_mode) |
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122 | { |
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123 | if (!kgem->nbatch) |
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124 | return; |
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125 | |||
126 | if (kgem_ring_is_idle(kgem, kgem->ring)) { |
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127 | DBG(("%s: GPU idle, flushing\n", __FUNCTION__)); |
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128 | _kgem_submit(kgem); |
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129 | } |
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130 | |||
131 | (void)new_mode; |
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132 | } |
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133 | |||
134 | static void |
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135 | no_render_retire(struct kgem *kgem) |
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136 | { |
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137 | (void)kgem; |
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138 | } |
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139 | |||
140 | static void |
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141 | no_render_expire(struct kgem *kgem) |
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142 | { |
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143 | (void)kgem; |
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144 | } |
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145 | |||
146 | static void |
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147 | no_render_fini(struct sna *sna) |
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148 | { |
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149 | (void)sna; |
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150 | } |
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151 | |||
152 | const char *no_render_init(struct sna *sna) |
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153 | { |
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154 | struct sna_render *render = &sna->render; |
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155 | |||
156 | memset (render,0, sizeof (*render)); |
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157 | |||
158 | render->prefer_gpu = PREFER_GPU_BLT; |
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159 | |||
160 | render->vertices = render->vertex_data; |
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161 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
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162 | |||
163 | render->reset = no_render_reset; |
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164 | render->flush = no_render_flush; |
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165 | render->fini = no_render_fini; |
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166 | |||
167 | sna->kgem.context_switch = no_render_context_switch; |
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168 | sna->kgem.retire = no_render_retire; |
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169 | sna->kgem.expire = no_render_expire; |
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170 | |||
171 | sna->kgem.mode = KGEM_RENDER; |
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172 | sna->kgem.ring = KGEM_RENDER; |
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173 | |||
174 | sna_vertex_init(sna); |
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175 | return "generic"; |
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176 | } |
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177 | |||
178 | void sna_vertex_init(struct sna *sna) |
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179 | { |
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180 | // pthread_mutex_init(&sna->render.lock, NULL); |
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181 | // pthread_cond_init(&sna->render.wait, NULL); |
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182 | sna->render.active = 0; |
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183 | } |
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184 | |||
185 | int sna_accel_init(struct sna *sna) |
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186 | { |
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187 | const char *backend; |
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188 | |||
189 | backend = no_render_init(sna); |
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190 | if (sna->info->gen >= 0100) |
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191 | (void)backend; |
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192 | else if (sna->info->gen >= 070) |
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193 | backend = gen7_render_init(sna, backend); |
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194 | else if (sna->info->gen >= 060) |
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195 | backend = gen6_render_init(sna, backend); |
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196 | else if (sna->info->gen >= 050) |
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197 | backend = gen5_render_init(sna, backend); |
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198 | else if (sna->info->gen >= 040) |
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199 | backend = gen4_render_init(sna, backend); |
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200 | else if (sna->info->gen >= 030) |
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201 | backend = gen3_render_init(sna, backend); |
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202 | |||
203 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
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204 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
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205 | |||
206 | kgem_reset(&sna->kgem); |
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207 | |||
208 | sna_device = sna; |
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209 | |||
210 | return kgem_init_fb(&sna->kgem, &sna_fb); |
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211 | } |
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212 | |||
213 | int sna_init(uint32_t service) |
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214 | { |
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215 | ioctl_t io; |
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216 | int caps = 0; |
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217 | |||
218 | static struct pci_device device; |
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219 | struct sna *sna; |
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220 | |||
221 | DBG(("%s\n", __FUNCTION__)); |
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222 | |||
223 | __lock_acquire_recursive(__sna_lock); |
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224 | |||
225 | if(sna_device) |
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226 | goto done; |
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227 | |||
228 | io.handle = service; |
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229 | io.io_code = SRV_GET_PCI_INFO; |
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230 | io.input = &device; |
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231 | io.inp_size = sizeof(device); |
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232 | io.output = NULL; |
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233 | io.out_size = 0; |
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234 | |||
235 | if (call_service(&io)!=0) |
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236 | goto err1; |
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237 | |||
238 | sna = malloc(sizeof(*sna)); |
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239 | if (sna == NULL) |
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240 | goto err1; |
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241 | |||
242 | memset(sna, 0, sizeof(*sna)); |
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243 | |||
244 | sna->cpu_features = sna_cpu_detect(); |
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245 | |||
246 | sna->PciInfo = &device; |
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247 | sna->info = intel_detect_chipset(sna->PciInfo); |
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248 | sna->scrn = service; |
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249 | |||
250 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
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251 | |||
252 | |||
253 | /* Disable tiling by default */ |
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254 | sna->tiling = 0; |
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255 | |||
256 | /* Default fail-safe value of 75 Hz */ |
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257 | // sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
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258 | |||
259 | sna->flags = 0; |
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260 | |||
261 | sna_accel_init(sna); |
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262 | |||
263 | tls_mask = tls_alloc(); |
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264 | |||
265 | // printf("tls mask %x\n", tls_mask); |
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266 | |||
267 | done: |
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268 | caps = sna_device->render.caps; |
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269 | |||
270 | err1: |
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271 | __lock_release_recursive(__sna_lock); |
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272 | |||
273 | return caps; |
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274 | } |
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275 | |||
276 | void sna_fini() |
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277 | { |
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4368 | Serge | 278 | ENTER(); |
279 | |||
4304 | Serge | 280 | if( sna_device ) |
281 | { |
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282 | struct kgem_bo *mask; |
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283 | |||
284 | __lock_acquire_recursive(__sna_lock); |
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285 | |||
286 | mask = tls_get(tls_mask); |
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287 | |||
288 | sna_device->render.fini(sna_device); |
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289 | if(mask) |
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290 | kgem_bo_destroy(&sna_device->kgem, mask); |
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4368 | Serge | 291 | // kgem_close_batches(&sna_device->kgem); |
4304 | Serge | 292 | kgem_cleanup_cache(&sna_device->kgem); |
293 | |||
294 | sna_device = NULL; |
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295 | __lock_release_recursive(__sna_lock); |
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296 | }; |
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4368 | Serge | 297 | LEAVE(); |
4304 | Serge | 298 | } |
299 | |||
300 | #if 0 |
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301 | |||
302 | static bool sna_solid_cache_init(struct sna *sna) |
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303 | { |
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304 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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305 | |||
306 | DBG(("%s\n", __FUNCTION__)); |
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307 | |||
308 | cache->cache_bo = |
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309 | kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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310 | if (!cache->cache_bo) |
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311 | return FALSE; |
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312 | |||
313 | /* |
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314 | * Initialise [0] with white since it is very common and filling the |
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315 | * zeroth slot simplifies some of the checks. |
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316 | */ |
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317 | cache->color[0] = 0xffffffff; |
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318 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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319 | cache->bo[0]->pitch = 4; |
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320 | cache->dirty = 1; |
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321 | cache->size = 1; |
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322 | cache->last = 0; |
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323 | |||
324 | return TRUE; |
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325 | } |
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326 | |||
327 | void |
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328 | sna_render_flush_solid(struct sna *sna) |
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329 | { |
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330 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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331 | |||
332 | DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
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333 | assert(cache->dirty); |
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334 | assert(cache->size); |
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335 | |||
336 | kgem_bo_write(&sna->kgem, cache->cache_bo, |
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337 | cache->color, cache->size*sizeof(uint32_t)); |
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338 | cache->dirty = 0; |
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339 | cache->last = 0; |
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340 | } |
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341 | |||
342 | static void |
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343 | sna_render_finish_solid(struct sna *sna, bool force) |
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344 | { |
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345 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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346 | int i; |
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347 | |||
348 | DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
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349 | force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
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350 | |||
351 | if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
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352 | return; |
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353 | |||
354 | if (cache->dirty) |
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355 | sna_render_flush_solid(sna); |
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356 | |||
357 | for (i = 0; i < cache->size; i++) { |
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358 | if (cache->bo[i] == NULL) |
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359 | continue; |
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360 | |||
361 | kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
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362 | cache->bo[i] = NULL; |
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363 | } |
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364 | kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
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365 | |||
366 | DBG(("sna_render_finish_solid reset\n")); |
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367 | |||
368 | cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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369 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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370 | cache->bo[0]->pitch = 4; |
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371 | if (force) |
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372 | cache->size = 1; |
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373 | } |
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374 | |||
375 | |||
376 | struct kgem_bo * |
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377 | sna_render_get_solid(struct sna *sna, uint32_t color) |
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378 | { |
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379 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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380 | int i; |
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381 | |||
382 | DBG(("%s: %08x\n", __FUNCTION__, color)); |
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383 | |||
384 | // if ((color & 0xffffff) == 0) /* alpha only */ |
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385 | // return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
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386 | |||
387 | if (color == 0xffffffff) { |
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388 | DBG(("%s(white)\n", __FUNCTION__)); |
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389 | return kgem_bo_reference(cache->bo[0]); |
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390 | } |
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391 | |||
392 | if (cache->color[cache->last] == color) { |
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393 | DBG(("sna_render_get_solid(%d) = %x (last)\n", |
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394 | cache->last, color)); |
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395 | return kgem_bo_reference(cache->bo[cache->last]); |
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396 | } |
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397 | |||
398 | for (i = 1; i < cache->size; i++) { |
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399 | if (cache->color[i] == color) { |
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400 | if (cache->bo[i] == NULL) { |
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401 | DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
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402 | i, color)); |
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403 | goto create; |
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404 | } else { |
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405 | DBG(("sna_render_get_solid(%d) = %x (old)\n", |
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406 | i, color)); |
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407 | goto done; |
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408 | } |
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409 | } |
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410 | } |
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411 | |||
412 | sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
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413 | |||
414 | i = cache->size++; |
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415 | cache->color[i] = color; |
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416 | cache->dirty = 1; |
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417 | DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
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418 | |||
419 | create: |
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420 | cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
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421 | i*sizeof(uint32_t), sizeof(uint32_t)); |
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422 | cache->bo[i]->pitch = 4; |
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423 | |||
424 | done: |
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425 | cache->last = i; |
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426 | return kgem_bo_reference(cache->bo[i]); |
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427 | } |
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428 | |||
429 | #endif |
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430 | |||
431 | |||
432 | int sna_blit_copy(bitmap_t *src_bitmap, int dst_x, int dst_y, |
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433 | int w, int h, int src_x, int src_y) |
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434 | |||
435 | { |
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436 | struct sna_copy_op copy; |
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437 | struct _Pixmap src, dst; |
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438 | struct kgem_bo *src_bo; |
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439 | |||
440 | char proc_info[1024]; |
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441 | int winx, winy; |
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442 | |||
443 | get_proc_info(proc_info); |
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444 | |||
445 | winx = *(uint32_t*)(proc_info+34); |
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446 | winy = *(uint32_t*)(proc_info+38); |
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447 | |||
448 | memset(&src, 0, sizeof(src)); |
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449 | memset(&dst, 0, sizeof(dst)); |
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450 | |||
451 | src.drawable.bitsPerPixel = 32; |
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452 | src.drawable.width = src_bitmap->width; |
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453 | src.drawable.height = src_bitmap->height; |
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454 | |||
455 | dst.drawable.bitsPerPixel = 32; |
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456 | dst.drawable.width = sna_fb.width; |
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457 | dst.drawable.height = sna_fb.height; |
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458 | |||
459 | memset(©, 0, sizeof(copy)); |
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460 | |||
461 | src_bo = (struct kgem_bo*)src_bitmap->handle; |
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462 | |||
463 | if( sna_device->render.copy(sna_device, GXcopy, |
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464 | &src, src_bo, |
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465 | &dst, sna_fb.fb_bo, ©) ) |
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466 | { |
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467 | copy.blt(sna_device, ©, src_x, src_y, w, h, winx+dst_x, winy+dst_y); |
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468 | copy.done(sna_device, ©); |
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469 | } |
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470 | |||
471 | kgem_submit(&sna_device->kgem); |
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472 | |||
473 | return 0; |
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474 | |||
475 | // __asm__ __volatile__("int3"); |
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476 | |||
477 | }; |
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478 | |||
479 | typedef struct |
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480 | { |
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481 | uint32_t width; |
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482 | uint32_t height; |
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483 | void *data; |
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484 | uint32_t pitch; |
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485 | struct kgem_bo *bo; |
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486 | uint32_t bo_size; |
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487 | uint32_t flags; |
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488 | }surface_t; |
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489 | |||
490 | |||
491 | |||
492 | int sna_create_bitmap(bitmap_t *bitmap) |
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493 | { |
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494 | surface_t *sf; |
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495 | struct kgem_bo *bo; |
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496 | |||
497 | sf = malloc(sizeof(*sf)); |
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498 | if(sf == NULL) |
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499 | goto err_1; |
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500 | |||
501 | __lock_acquire_recursive(__sna_lock); |
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502 | |||
503 | bo = kgem_create_2d(&sna_device->kgem, bitmap->width, bitmap->height, |
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504 | 32,I915_TILING_NONE, CREATE_CPU_MAP); |
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505 | |||
506 | if(bo == NULL) |
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507 | goto err_2; |
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508 | |||
509 | void *map = kgem_bo_map(&sna_device->kgem, bo); |
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510 | if(map == NULL) |
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511 | goto err_3; |
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512 | |||
513 | sf->width = bitmap->width; |
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514 | sf->height = bitmap->height; |
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515 | sf->data = map; |
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516 | sf->pitch = bo->pitch; |
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517 | sf->bo = bo; |
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518 | sf->bo_size = PAGE_SIZE * bo->size.pages.count; |
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519 | sf->flags = bitmap->flags; |
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520 | |||
521 | bitmap->handle = (uint32_t)sf; |
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522 | __lock_release_recursive(__sna_lock); |
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523 | |||
524 | return 0; |
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525 | |||
526 | err_3: |
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527 | kgem_bo_destroy(&sna_device->kgem, bo); |
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528 | err_2: |
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529 | __lock_release_recursive(__sna_lock); |
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530 | free(sf); |
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531 | err_1: |
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532 | return -1; |
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533 | }; |
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534 | |||
535 | int sna_bitmap_from_handle(bitmap_t *bitmap, uint32_t handle) |
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536 | { |
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537 | surface_t *sf; |
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538 | struct kgem_bo *bo; |
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539 | |||
540 | sf = malloc(sizeof(*sf)); |
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541 | if(sf == NULL) |
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542 | goto err_1; |
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543 | |||
544 | __lock_acquire_recursive(__sna_lock); |
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545 | |||
546 | bo = kgem_bo_from_handle(&sna_device->kgem, handle, bitmap->pitch, bitmap->height); |
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547 | |||
548 | __lock_release_recursive(__sna_lock); |
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549 | |||
550 | sf->width = bitmap->width; |
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551 | sf->height = bitmap->height; |
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552 | sf->data = NULL; |
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553 | sf->pitch = bo->pitch; |
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554 | sf->bo = bo; |
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555 | sf->bo_size = PAGE_SIZE * bo->size.pages.count; |
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556 | sf->flags = bitmap->flags; |
||
557 | |||
558 | bitmap->handle = (uint32_t)sf; |
||
559 | |||
560 | return 0; |
||
561 | |||
562 | err_2: |
||
563 | __lock_release_recursive(__sna_lock); |
||
564 | free(sf); |
||
565 | err_1: |
||
566 | return -1; |
||
567 | }; |
||
568 | |||
569 | void sna_set_bo_handle(bitmap_t *bitmap, int handle) |
||
570 | { |
||
571 | surface_t *sf = to_surface(bitmap); |
||
572 | struct kgem_bo *bo = sf->bo; |
||
573 | bo->handle = handle; |
||
574 | } |
||
575 | |||
576 | int sna_destroy_bitmap(bitmap_t *bitmap) |
||
577 | { |
||
578 | surface_t *sf = to_surface(bitmap); |
||
579 | |||
580 | __lock_acquire_recursive(__sna_lock); |
||
581 | |||
582 | kgem_bo_destroy(&sna_device->kgem, sf->bo); |
||
583 | |||
584 | __lock_release_recursive(__sna_lock); |
||
585 | |||
586 | free(sf); |
||
587 | |||
588 | bitmap->handle = -1; |
||
589 | bitmap->data = (void*)-1; |
||
590 | bitmap->pitch = -1; |
||
591 | |||
592 | return 0; |
||
593 | }; |
||
594 | |||
595 | int sna_lock_bitmap(bitmap_t *bitmap) |
||
596 | { |
||
597 | surface_t *sf = to_surface(bitmap); |
||
598 | |||
599 | // printf("%s\n", __FUNCTION__); |
||
600 | __lock_acquire_recursive(__sna_lock); |
||
601 | |||
602 | kgem_bo_sync__cpu(&sna_device->kgem, sf->bo); |
||
603 | |||
604 | __lock_release_recursive(__sna_lock); |
||
605 | |||
606 | bitmap->data = sf->data; |
||
607 | bitmap->pitch = sf->pitch; |
||
608 | |||
609 | return 0; |
||
610 | }; |
||
611 | |||
612 | int sna_resize_bitmap(bitmap_t *bitmap) |
||
613 | { |
||
614 | surface_t *sf = to_surface(bitmap); |
||
615 | struct kgem *kgem = &sna_device->kgem; |
||
616 | struct kgem_bo *bo = sf->bo; |
||
617 | |||
618 | uint32_t size; |
||
619 | uint32_t pitch; |
||
620 | |||
621 | bitmap->pitch = -1; |
||
622 | bitmap->data = (void *) -1; |
||
623 | |||
624 | size = kgem_surface_size(kgem,kgem->has_relaxed_fencing, CREATE_CPU_MAP, |
||
625 | bitmap->width, bitmap->height, 32, I915_TILING_NONE, &pitch); |
||
626 | assert(size && size <= kgem->max_object_size); |
||
627 | |||
628 | if(sf->bo_size >= size) |
||
629 | { |
||
630 | sf->width = bitmap->width; |
||
631 | sf->height = bitmap->height; |
||
632 | sf->pitch = pitch; |
||
633 | bo->pitch = pitch; |
||
634 | |||
635 | return 0; |
||
636 | } |
||
637 | else |
||
638 | { |
||
639 | __lock_acquire_recursive(__sna_lock); |
||
640 | |||
641 | sna_bo_destroy(kgem, bo); |
||
642 | |||
643 | sf->bo = NULL; |
||
644 | |||
645 | bo = kgem_create_2d(kgem, bitmap->width, bitmap->height, |
||
646 | 32, I915_TILING_NONE, CREATE_CPU_MAP); |
||
647 | |||
648 | if(bo == NULL) |
||
649 | { |
||
650 | __lock_release_recursive(__sna_lock); |
||
651 | return -1; |
||
652 | }; |
||
653 | |||
654 | void *map = kgem_bo_map(kgem, bo); |
||
655 | if(map == NULL) |
||
656 | { |
||
657 | sna_bo_destroy(kgem, bo); |
||
658 | __lock_release_recursive(__sna_lock); |
||
659 | return -1; |
||
660 | }; |
||
661 | |||
662 | __lock_release_recursive(__sna_lock); |
||
663 | |||
664 | sf->width = bitmap->width; |
||
665 | sf->height = bitmap->height; |
||
666 | sf->data = map; |
||
667 | sf->pitch = bo->pitch; |
||
668 | sf->bo = bo; |
||
669 | sf->bo_size = PAGE_SIZE * bo->size.pages.count; |
||
670 | } |
||
671 | |||
672 | return 0; |
||
673 | }; |
||
674 | |||
675 | |||
676 | |||
677 | int sna_create_mask() |
||
678 | { |
||
679 | struct kgem_bo *bo; |
||
680 | |||
681 | // printf("%s width %d height %d\n", __FUNCTION__, sna_fb.width, sna_fb.height); |
||
682 | |||
683 | __lock_acquire_recursive(__sna_lock); |
||
684 | |||
685 | bo = kgem_create_2d(&sna_device->kgem, sna_fb.width, sna_fb.height, |
||
686 | 8,I915_TILING_NONE, CREATE_CPU_MAP); |
||
687 | |||
688 | if(unlikely(bo == NULL)) |
||
689 | goto err_1; |
||
690 | |||
691 | int *map = kgem_bo_map(&sna_device->kgem, bo); |
||
692 | if(map == NULL) |
||
693 | goto err_2; |
||
694 | |||
695 | __lock_release_recursive(__sna_lock); |
||
696 | |||
697 | memset(map, 0, bo->pitch * sna_fb.height); |
||
698 | |||
699 | tls_set(tls_mask, bo); |
||
700 | |||
701 | return 0; |
||
702 | |||
703 | err_2: |
||
704 | kgem_bo_destroy(&sna_device->kgem, bo); |
||
705 | err_1: |
||
706 | __lock_release_recursive(__sna_lock); |
||
707 | return -1; |
||
708 | }; |
||
709 | |||
4368 | Serge | 710 | #define MI_LOAD_REGISTER_IMM (0x22<<23) |
711 | #define MI_WAIT_FOR_EVENT (0x03<<23) |
||
4304 | Serge | 712 | |
4368 | Serge | 713 | static bool sna_emit_wait_for_scanline_gen6(struct sna *sna, |
714 | rect_t *crtc, |
||
715 | int pipe, int y1, int y2, |
||
716 | bool full_height) |
||
717 | { |
||
718 | uint32_t *b; |
||
719 | uint32_t event; |
||
720 | |||
721 | // if (!sna->kgem.has_secure_batches) |
||
722 | // return false; |
||
723 | |||
724 | assert(y1 >= 0); |
||
725 | assert(y2 > y1); |
||
726 | assert(sna->kgem.mode == KGEM_RENDER); |
||
727 | |||
728 | /* Always program one less than the desired value */ |
||
729 | if (--y1 < 0) |
||
730 | y1 = crtc->b; |
||
731 | y2--; |
||
732 | |||
733 | /* The scanline granularity is 3 bits */ |
||
734 | y1 &= ~7; |
||
735 | y2 &= ~7; |
||
736 | if (y2 == y1) |
||
737 | return false; |
||
738 | |||
739 | event = 1 << (3*full_height + pipe*8); |
||
740 | |||
741 | b = kgem_get_batch(&sna->kgem); |
||
742 | sna->kgem.nbatch += 10; |
||
743 | |||
744 | b[0] = MI_LOAD_REGISTER_IMM | 1; |
||
745 | b[1] = 0x44050; /* DERRMR */ |
||
746 | b[2] = ~event; |
||
747 | b[3] = MI_LOAD_REGISTER_IMM | 1; |
||
748 | b[4] = 0x4f100; /* magic */ |
||
749 | b[5] = (1 << 31) | (1 << 30) | pipe << 29 | (y1 << 16) | y2; |
||
750 | b[6] = MI_WAIT_FOR_EVENT | event; |
||
751 | b[7] = MI_LOAD_REGISTER_IMM | 1; |
||
752 | b[8] = 0x44050; /* DERRMR */ |
||
753 | b[9] = ~0; |
||
754 | |||
755 | sna->kgem.batch_flags |= I915_EXEC_SECURE; |
||
756 | |||
757 | return true; |
||
758 | } |
||
759 | |||
4304 | Serge | 760 | bool |
4368 | Serge | 761 | sna_wait_for_scanline(struct sna *sna, |
762 | rect_t *crtc, |
||
763 | rect_t *clip) |
||
764 | { |
||
765 | bool full_height; |
||
766 | int y1, y2, pipe; |
||
767 | bool ret; |
||
768 | |||
769 | // if (sna->flags & SNA_NO_VSYNC) |
||
770 | // return false; |
||
771 | |||
772 | /* |
||
773 | * Make sure we don't wait for a scanline that will |
||
774 | * never occur |
||
775 | */ |
||
776 | y1 = clip->t - crtc->t; |
||
777 | if (y1 < 0) |
||
778 | y1 = 0; |
||
779 | y2 = clip->b - crtc->t; |
||
780 | if (y2 > crtc->b - crtc->t) |
||
781 | y2 = crtc->b - crtc->t; |
||
782 | // DBG(("%s: clipped range = %d, %d\n", __FUNCTION__, y1, y2)); |
||
783 | // printf("%s: clipped range = %d, %d\n", __FUNCTION__, y1, y2); |
||
784 | |||
785 | if (y2 <= y1 + 4) |
||
786 | return false; |
||
787 | |||
788 | full_height = y1 == 0 && y2 == crtc->b - crtc->t; |
||
789 | |||
790 | pipe = 0; |
||
791 | DBG(("%s: pipe=%d, y1=%d, y2=%d, full_height?=%d\n", |
||
792 | __FUNCTION__, pipe, y1, y2, full_height)); |
||
793 | |||
794 | if (sna->kgem.gen >= 0100) |
||
795 | ret = false; |
||
796 | // else if (sna->kgem.gen >= 075) |
||
797 | // ret = sna_emit_wait_for_scanline_hsw(sna, crtc, pipe, y1, y2, full_height); |
||
798 | // else if (sna->kgem.gen >= 070) |
||
799 | // ret = sna_emit_wait_for_scanline_ivb(sna, crtc, pipe, y1, y2, full_height); |
||
800 | else if (sna->kgem.gen >= 060) |
||
801 | ret =sna_emit_wait_for_scanline_gen6(sna, crtc, pipe, y1, y2, full_height); |
||
802 | // else if (sna->kgem.gen >= 040) |
||
803 | // ret = sna_emit_wait_for_scanline_gen4(sna, crtc, pipe, y1, y2, full_height); |
||
804 | |||
805 | return ret; |
||
806 | } |
||
807 | |||
808 | |||
809 | bool |
||
4304 | Serge | 810 | gen6_composite(struct sna *sna, |
811 | uint8_t op, |
||
812 | PixmapPtr src, struct kgem_bo *src_bo, |
||
813 | PixmapPtr mask,struct kgem_bo *mask_bo, |
||
814 | PixmapPtr dst, struct kgem_bo *dst_bo, |
||
815 | int32_t src_x, int32_t src_y, |
||
816 | int32_t msk_x, int32_t msk_y, |
||
817 | int32_t dst_x, int32_t dst_y, |
||
818 | int32_t width, int32_t height, |
||
819 | struct sna_composite_op *tmp); |
||
820 | |||
821 | |||
822 | #define MAP(ptr) ((void*)((uintptr_t)(ptr) & ~3)) |
||
823 | |||
824 | int sna_blit_tex(bitmap_t *bitmap, bool scale, int dst_x, int dst_y, |
||
825 | int w, int h, int src_x, int src_y) |
||
826 | |||
827 | { |
||
828 | surface_t *sf = to_surface(bitmap); |
||
829 | |||
830 | struct drm_i915_mask_update update; |
||
831 | |||
832 | struct sna_composite_op composite; |
||
833 | struct _Pixmap src, dst, mask; |
||
834 | struct kgem_bo *src_bo, *mask_bo; |
||
835 | int winx, winy; |
||
836 | |||
837 | char proc_info[1024]; |
||
838 | |||
839 | get_proc_info(proc_info); |
||
840 | |||
841 | winx = *(uint32_t*)(proc_info+34); |
||
842 | winy = *(uint32_t*)(proc_info+38); |
||
843 | // winw = *(uint32_t*)(proc_info+42)+1; |
||
844 | // winh = *(uint32_t*)(proc_info+46)+1; |
||
845 | |||
846 | mask_bo = tls_get(tls_mask); |
||
847 | |||
848 | if(unlikely(mask_bo == NULL)) |
||
849 | { |
||
850 | sna_create_mask(); |
||
851 | mask_bo = tls_get(tls_mask); |
||
852 | if( mask_bo == NULL) |
||
853 | return -1; |
||
854 | }; |
||
855 | |||
856 | if(kgem_update_fb(&sna_device->kgem, &sna_fb)) |
||
857 | { |
||
858 | __lock_acquire_recursive(__sna_lock); |
||
859 | kgem_bo_destroy(&sna_device->kgem, mask_bo); |
||
860 | __lock_release_recursive(__sna_lock); |
||
861 | |||
862 | sna_create_mask(); |
||
863 | mask_bo = tls_get(tls_mask); |
||
864 | if( mask_bo == NULL) |
||
865 | return -1; |
||
866 | } |
||
867 | |||
868 | VG_CLEAR(update); |
||
869 | update.handle = mask_bo->handle; |
||
870 | update.bo_map = (int)kgem_bo_map__cpu(&sna_device->kgem, mask_bo); |
||
871 | drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update); |
||
872 | mask_bo->pitch = update.bo_pitch; |
||
873 | |||
874 | memset(&src, 0, sizeof(src)); |
||
875 | memset(&dst, 0, sizeof(dst)); |
||
876 | memset(&mask, 0, sizeof(dst)); |
||
877 | |||
878 | src.drawable.bitsPerPixel = 32; |
||
879 | |||
880 | src.drawable.width = sf->width; |
||
881 | src.drawable.height = sf->height; |
||
882 | |||
883 | dst.drawable.bitsPerPixel = 32; |
||
884 | dst.drawable.width = sna_fb.width; |
||
885 | dst.drawable.height = sna_fb.height; |
||
886 | |||
887 | mask.drawable.bitsPerPixel = 8; |
||
888 | mask.drawable.width = update.width; |
||
889 | mask.drawable.height = update.height; |
||
890 | |||
891 | memset(&composite, 0, sizeof(composite)); |
||
892 | |||
893 | src_bo = sf->bo; |
||
894 | |||
895 | __lock_acquire_recursive(__sna_lock); |
||
896 | |||
4368 | Serge | 897 | { |
898 | rect_t crtc, clip; |
||
4304 | Serge | 899 | |
4368 | Serge | 900 | crtc.l = 0; |
901 | crtc.t = 0; |
||
902 | crtc.r = sna_fb.width-1; |
||
903 | crtc.b = sna_fb.height-1; |
||
904 | |||
905 | clip.l = winx+dst_x; |
||
906 | clip.t = winy+dst_y; |
||
907 | clip.r = clip.l+w-1; |
||
908 | clip.b = clip.t+h-1; |
||
909 | |||
910 | kgem_set_mode(&sna_device->kgem, KGEM_RENDER, sna_fb.fb_bo); |
||
911 | sna_wait_for_scanline(sna_device, &crtc, &clip); |
||
912 | } |
||
913 | |||
4304 | Serge | 914 | if( sna_device->render.blit_tex(sna_device, PictOpSrc,scale, |
915 | &src, src_bo, |
||
916 | &mask, mask_bo, |
||
917 | &dst, sna_fb.fb_bo, |
||
918 | src_x, src_y, |
||
919 | dst_x, dst_y, |
||
920 | winx+dst_x, winy+dst_y, |
||
921 | w, h, |
||
922 | &composite) ) |
||
923 | { |
||
924 | struct sna_composite_rectangles r; |
||
925 | |||
926 | r.src.x = src_x; |
||
927 | r.src.y = src_y; |
||
928 | r.mask.x = dst_x; |
||
929 | r.mask.y = dst_y; |
||
930 | r.dst.x = winx+dst_x; |
||
931 | r.dst.y = winy+dst_y; |
||
932 | r.width = w; |
||
933 | r.height = h; |
||
934 | |||
935 | composite.blt(sna_device, &composite, &r); |
||
936 | composite.done(sna_device, &composite); |
||
937 | |||
938 | }; |
||
939 | |||
940 | kgem_submit(&sna_device->kgem); |
||
941 | |||
942 | __lock_release_recursive(__sna_lock); |
||
943 | |||
944 | bitmap->data = (void*)-1; |
||
945 | bitmap->pitch = -1; |
||
946 | |||
947 | return 0; |
||
948 | } |
||
949 | |||
950 | |||
951 | |||
952 | |||
953 | |||
954 | |||
955 | |||
956 | static const struct intel_device_info intel_generic_info = { |
||
957 | .gen = -1, |
||
958 | }; |
||
959 | |||
960 | static const struct intel_device_info intel_i915_info = { |
||
961 | .gen = 030, |
||
962 | }; |
||
963 | static const struct intel_device_info intel_i945_info = { |
||
964 | .gen = 031, |
||
965 | }; |
||
966 | |||
967 | static const struct intel_device_info intel_g33_info = { |
||
968 | .gen = 033, |
||
969 | }; |
||
970 | |||
971 | static const struct intel_device_info intel_i965_info = { |
||
972 | .gen = 040, |
||
973 | }; |
||
974 | |||
975 | static const struct intel_device_info intel_g4x_info = { |
||
976 | .gen = 045, |
||
977 | }; |
||
978 | |||
979 | static const struct intel_device_info intel_ironlake_info = { |
||
980 | .gen = 050, |
||
981 | }; |
||
982 | |||
983 | static const struct intel_device_info intel_sandybridge_info = { |
||
984 | .gen = 060, |
||
985 | }; |
||
986 | |||
987 | static const struct intel_device_info intel_ivybridge_info = { |
||
988 | .gen = 070, |
||
989 | }; |
||
990 | |||
991 | static const struct intel_device_info intel_valleyview_info = { |
||
992 | .gen = 071, |
||
993 | }; |
||
994 | |||
995 | static const struct intel_device_info intel_haswell_info = { |
||
996 | .gen = 075, |
||
997 | }; |
||
998 | |||
999 | #define INTEL_DEVICE_MATCH(d,i) \ |
||
1000 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
||
1001 | |||
1002 | |||
1003 | static const struct pci_id_match intel_device_match[] = { |
||
1004 | |||
1005 | INTEL_I915G_IDS(&intel_i915_info), |
||
1006 | INTEL_I915GM_IDS(&intel_i915_info), |
||
1007 | INTEL_I945G_IDS(&intel_i945_info), |
||
1008 | INTEL_I945GM_IDS(&intel_i945_info), |
||
1009 | |||
1010 | INTEL_G33_IDS(&intel_g33_info), |
||
1011 | INTEL_PINEVIEW_IDS(&intel_g33_info), |
||
1012 | |||
1013 | INTEL_I965G_IDS(&intel_i965_info), |
||
1014 | INTEL_I965GM_IDS(&intel_i965_info), |
||
1015 | |||
1016 | INTEL_G45_IDS(&intel_g4x_info), |
||
1017 | INTEL_GM45_IDS(&intel_g4x_info), |
||
1018 | |||
1019 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_info), |
||
1020 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_info), |
||
1021 | |||
1022 | INTEL_SNB_D_IDS(&intel_sandybridge_info), |
||
1023 | INTEL_SNB_M_IDS(&intel_sandybridge_info), |
||
1024 | |||
1025 | INTEL_IVB_D_IDS(&intel_ivybridge_info), |
||
1026 | INTEL_IVB_M_IDS(&intel_ivybridge_info), |
||
1027 | |||
1028 | INTEL_HSW_D_IDS(&intel_haswell_info), |
||
1029 | INTEL_HSW_M_IDS(&intel_haswell_info), |
||
1030 | |||
1031 | INTEL_VLV_D_IDS(&intel_valleyview_info), |
||
1032 | INTEL_VLV_M_IDS(&intel_valleyview_info), |
||
1033 | |||
1034 | INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info), |
||
1035 | |||
1036 | { 0, 0, 0 }, |
||
1037 | }; |
||
1038 | |||
1039 | const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
||
1040 | { |
||
1041 | while(list->device_id) |
||
1042 | { |
||
1043 | if(dev==list->device_id) |
||
1044 | return list; |
||
1045 | list++; |
||
1046 | } |
||
1047 | return NULL; |
||
1048 | } |
||
1049 | |||
1050 | const struct intel_device_info * |
||
1051 | intel_detect_chipset(struct pci_device *pci) |
||
1052 | { |
||
1053 | const struct pci_id_match *ent = NULL; |
||
1054 | |||
1055 | ent = PciDevMatch(pci->device_id, intel_device_match); |
||
1056 | |||
1057 | if(ent != NULL) |
||
1058 | return (const struct intel_device_info*)ent->match_data; |
||
1059 | else |
||
1060 | return &intel_generic_info; |
||
1061 | } |
||
1062 | |||
1063 | int intel_get_device_id(int fd) |
||
1064 | { |
||
1065 | struct drm_i915_getparam gp; |
||
1066 | int devid = 0; |
||
1067 | |||
1068 | memset(&gp, 0, sizeof(gp)); |
||
1069 | gp.param = I915_PARAM_CHIPSET_ID; |
||
1070 | gp.value = &devid; |
||
1071 | |||
1072 | if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp)) |
||
1073 | return 0; |
||
1074 | |||
1075 | return devid; |
||
1076 | } |
||
1077 | |||
1078 | int drmIoctl(int fd, unsigned long request, void *arg) |
||
1079 | { |
||
1080 | ioctl_t io; |
||
1081 | |||
1082 | io.handle = fd; |
||
1083 | io.io_code = request; |
||
1084 | io.input = arg; |
||
1085 | io.inp_size = 64; |
||
1086 | io.output = NULL; |
||
1087 | io.out_size = 0; |
||
1088 | |||
1089 | return call_service(&io); |
||
1090 | }><>><>=>>><>><>><>><>><>>23) |
||
1091 | |||
1092 | |||
1093 |