WebSVN – Kolibri OS – Blame – /contrib/sdk/sources/Intel-2D/sna/gen6_render.c

Rev	Author	Line No.	Line
4304	Serge	1	/*
		2	* Copyright © 2006,2008,2011 Intel Corporation
		3	* Copyright © 2007 Red Hat, Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice (including the next
		13	* paragraph) shall be included in all copies or substantial portions of the
		14	* Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
		21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		22	* SOFTWARE.
		23	*
		24	* Authors:
		25	* Wang Zhenyu
		26	* Eric Anholt
		27	* Carl Worth
		28	* Keith Packard
		29	* Chris Wilson
		30	*
		31	*/
		32
		33
		34	#include "sna.h"
		35	#include "sna_reg.h"
		36	#include "sna_render.h"
		37	#include "sna_render_inline.h"
		38	//#include "sna_video.h"
		39
		40	#include "brw/brw.h"
		41	#include "gen6_render.h"
4501	Serge	42	#include "gen6_common.h"
		43	#include "gen4_common.h"
4304	Serge	44	#include "gen4_source.h"
		45	#include "gen4_vertex.h"
		46
		47	#define NO_COMPOSITE 0
		48	#define NO_COMPOSITE_SPANS 0
		49	#define NO_COPY 0
		50	#define NO_COPY_BOXES 0
		51	#define NO_FILL 0
		52	#define NO_FILL_BOXES 0
		53	#define NO_FILL_ONE 0
		54	#define NO_FILL_CLEAR 0
		55
		56	#define NO_RING_SWITCH 0
		57	#define PREFER_RENDER 0
		58
		59	#define USE_8_PIXEL_DISPATCH 1
		60	#define USE_16_PIXEL_DISPATCH 1
		61	#define USE_32_PIXEL_DISPATCH 0
		62
		63	#if !USE_8_PIXEL_DISPATCH && !USE_16_PIXEL_DISPATCH && !USE_32_PIXEL_DISPATCH
		64	#error "Must select at least 8, 16 or 32 pixel dispatch"
		65	#endif
		66
		67	#define GEN6_MAX_SIZE 8192
		68
		69	struct gt_info {
		70	const char *name;
		71	int max_vs_threads;
		72	int max_gs_threads;
		73	int max_wm_threads;
		74	struct {
		75	int size;
		76	int max_vs_entries;
		77	int max_gs_entries;
		78	} urb;
4501	Serge	79	int gt;
4304	Serge	80	};
		81
		82	static const struct gt_info gt1_info = {
		83	.name = "Sandybridge (gen6, gt1)",
		84	.max_vs_threads = 24,
		85	.max_gs_threads = 21,
		86	.max_wm_threads = 40,
		87	.urb = { 32, 256, 256 },
4501	Serge	88	.gt = 1,
4304	Serge	89	};
		90
		91	static const struct gt_info gt2_info = {
		92	.name = "Sandybridge (gen6, gt2)",
		93	.max_vs_threads = 60,
		94	.max_gs_threads = 60,
		95	.max_wm_threads = 80,
		96	.urb = { 64, 256, 256 },
4501	Serge	97	.gt = 2,
4304	Serge	98	};
		99
		100	static const uint32_t ps_kernel_packed[][4] = {
		101	#include "exa_wm_src_affine.g6b"
		102	#include "exa_wm_src_sample_argb.g6b"
		103	#include "exa_wm_yuv_rgb.g6b"
		104	#include "exa_wm_write.g6b"
		105	};
		106
		107	static const uint32_t ps_kernel_planar[][4] = {
		108	#include "exa_wm_src_affine.g6b"
		109	#include "exa_wm_src_sample_planar.g6b"
		110	#include "exa_wm_yuv_rgb.g6b"
		111	#include "exa_wm_write.g6b"
		112	};
		113
		114	#define NOKERNEL(kernel_enum, func, ns) \
		115	[GEN6_WM_KERNEL_##kernel_enum] = {#kernel_enum, func, 0, ns}
		116	#define KERNEL(kernel_enum, kernel, ns) \
		117	[GEN6_WM_KERNEL_##kernel_enum] = {#kernel_enum, kernel, sizeof(kernel), ns}
		118
		119	static const struct wm_kernel_info {
		120	const char *name;
		121	const void *data;
		122	unsigned int size;
		123	unsigned int num_surfaces;
		124	} wm_kernels[] = {
		125	NOKERNEL(NOMASK, brw_wm_kernel__affine, 2),
		126	NOKERNEL(NOMASK_P, brw_wm_kernel__projective, 2),
		127
		128	NOKERNEL(MASK, brw_wm_kernel__affine_mask, 3),
		129	NOKERNEL(MASK_P, brw_wm_kernel__projective_mask, 3),
		130
		131	NOKERNEL(MASKCA, brw_wm_kernel__affine_mask_ca, 3),
		132	NOKERNEL(MASKCA_P, brw_wm_kernel__projective_mask_ca, 3),
		133
		134	NOKERNEL(MASKSA, brw_wm_kernel__affine_mask_sa, 3),
		135	NOKERNEL(MASKSA_P, brw_wm_kernel__projective_mask_sa, 3),
		136
		137	NOKERNEL(OPACITY, brw_wm_kernel__affine_opacity, 2),
		138	NOKERNEL(OPACITY_P, brw_wm_kernel__projective_opacity, 2),
		139
		140	KERNEL(VIDEO_PLANAR, ps_kernel_planar, 7),
		141	KERNEL(VIDEO_PACKED, ps_kernel_packed, 2),
		142	};
		143	#undef KERNEL
		144
		145	static const struct blendinfo {
		146	bool src_alpha;
		147	uint32_t src_blend;
		148	uint32_t dst_blend;
		149	} gen6_blend_op[] = {
		150	/* Clear */ {0, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ZERO},
		151	/* Src */ {0, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ZERO},
		152	/* Dst */ {0, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ONE},
		153	/* Over */ {1, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		154	/* OverReverse */ {0, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_ONE},
		155	/* In */ {0, GEN6_BLENDFACTOR_DST_ALPHA, GEN6_BLENDFACTOR_ZERO},
		156	/* InReverse */ {1, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_SRC_ALPHA},
		157	/* Out */ {0, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_ZERO},
		158	/* OutReverse */ {1, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		159	/* Atop */ {1, GEN6_BLENDFACTOR_DST_ALPHA, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		160	/* AtopReverse */ {1, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_SRC_ALPHA},
		161	/* Xor */ {1, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		162	/* Add */ {0, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ONE},
		163	};
		164
		165	/**
		166	* Highest-valued BLENDFACTOR used in gen6_blend_op.
		167	*
		168	* This leaves out GEN6_BLENDFACTOR_INV_DST_COLOR,
		169	* GEN6_BLENDFACTOR_INV_CONST_{COLOR,ALPHA},
		170	* GEN6_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA}
		171	*/
		172	#define GEN6_BLENDFACTOR_COUNT (GEN6_BLENDFACTOR_INV_DST_ALPHA + 1)
		173
		174	#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64)
		175
		176	#define BLEND_OFFSET(s, d) \
		177	(((s) * GEN6_BLENDFACTOR_COUNT + (d)) * GEN6_BLEND_STATE_PADDED_SIZE)
		178
		179	#define NO_BLEND BLEND_OFFSET(GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ZERO)
		180	#define CLEAR BLEND_OFFSET(GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ZERO)
		181
		182	#define SAMPLER_OFFSET(sf, se, mf, me) \
		183	(((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me) + 2) * 2 * sizeof(struct gen6_sampler_state))
		184
		185	#define VERTEX_2s2s 0
		186
		187	#define COPY_SAMPLER 0
		188	#define COPY_VERTEX VERTEX_2s2s
		189	#define COPY_FLAGS(a) GEN6_SET_FLAGS(COPY_SAMPLER, (a) == GXcopy ? NO_BLEND : CLEAR, GEN6_WM_KERNEL_NOMASK, COPY_VERTEX)
		190
		191	#define FILL_SAMPLER (2 * sizeof(struct gen6_sampler_state))
		192	#define FILL_VERTEX VERTEX_2s2s
		193	#define FILL_FLAGS(op, format) GEN6_SET_FLAGS(FILL_SAMPLER, gen6_get_blend((op), false, (format)), GEN6_WM_KERNEL_NOMASK, FILL_VERTEX)
		194	#define FILL_FLAGS_NOBLEND GEN6_SET_FLAGS(FILL_SAMPLER, NO_BLEND, GEN6_WM_KERNEL_NOMASK, FILL_VERTEX)
		195
		196	#define GEN6_SAMPLER(f) (((f) >> 16) & 0xfff0)
		197	#define GEN6_BLEND(f) (((f) >> 0) & 0xfff0)
		198	#define GEN6_KERNEL(f) (((f) >> 16) & 0xf)
		199	#define GEN6_VERTEX(f) (((f) >> 0) & 0xf)
		200	#define GEN6_SET_FLAGS(S, B, K, V) (((S) \| (K)) << 16 \| ((B) \| (V)))
		201
		202	#define OUT_BATCH(v) batch_emit(sna, v)
		203	#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
		204	#define OUT_VERTEX_F(v) vertex_emit(sna, v)
		205
		206	static inline bool too_large(int width, int height)
		207	{
		208	return width > GEN6_MAX_SIZE \|\| height > GEN6_MAX_SIZE;
		209	}
		210
		211	static uint32_t gen6_get_blend(int op,
		212	bool has_component_alpha,
		213	uint32_t dst_format)
		214	{
		215	uint32_t src, dst;
		216
		217
		218	src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend;
		219	dst = GEN6_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend;
		220
		221	// dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend;
		222
		223	#if 0
		224	/* If there's no dst alpha channel, adjust the blend op so that
		225	* we'll treat it always as 1.
		226	*/
		227	if (PICT_FORMAT_A(dst_format) == 0) {
		228	if (src == GEN6_BLENDFACTOR_DST_ALPHA)
		229	src = GEN6_BLENDFACTOR_ONE;
		230	else if (src == GEN6_BLENDFACTOR_INV_DST_ALPHA)
		231	src = GEN6_BLENDFACTOR_ZERO;
		232	}
		233
		234	/* If the source alpha is being used, then we should only be in a
		235	* case where the source blend factor is 0, and the source blend
		236	* value is the mask channels multiplied by the source picture's alpha.
		237	*/
		238	if (has_component_alpha && gen6_blend_op[op].src_alpha) {
		239	if (dst == GEN6_BLENDFACTOR_SRC_ALPHA)
		240	dst = GEN6_BLENDFACTOR_SRC_COLOR;
		241	else if (dst == GEN6_BLENDFACTOR_INV_SRC_ALPHA)
		242	dst = GEN6_BLENDFACTOR_INV_SRC_COLOR;
		243	}
		244
		245	DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n",
		246	op, dst_format, PICT_FORMAT_A(dst_format),
		247	src, dst, (int)BLEND_OFFSET(src, dst)));
		248	#endif
		249
		250	return BLEND_OFFSET(src, dst);
		251	}
		252
		253	static uint32_t gen6_get_card_format(PictFormat format)
		254	{
		255	switch (format) {
		256	default:
		257	return -1;
		258	case PICT_a8r8g8b8:
		259	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
		260	case PICT_x8r8g8b8:
		261	return GEN6_SURFACEFORMAT_B8G8R8X8_UNORM;
		262	case PICT_a8b8g8r8:
		263	return GEN6_SURFACEFORMAT_R8G8B8A8_UNORM;
		264	case PICT_x8b8g8r8:
		265	return GEN6_SURFACEFORMAT_R8G8B8X8_UNORM;
		266	case PICT_a2r10g10b10:
		267	return GEN6_SURFACEFORMAT_B10G10R10A2_UNORM;
		268	case PICT_x2r10g10b10:
		269	return GEN6_SURFACEFORMAT_B10G10R10X2_UNORM;
		270	case PICT_r8g8b8:
		271	return GEN6_SURFACEFORMAT_R8G8B8_UNORM;
		272	case PICT_r5g6b5:
		273	return GEN6_SURFACEFORMAT_B5G6R5_UNORM;
		274	case PICT_a1r5g5b5:
		275	return GEN6_SURFACEFORMAT_B5G5R5A1_UNORM;
		276	case PICT_a8:
		277	return GEN6_SURFACEFORMAT_A8_UNORM;
		278	case PICT_a4r4g4b4:
		279	return GEN6_SURFACEFORMAT_B4G4R4A4_UNORM;
		280	}
		281	}
		282
		283	static uint32_t gen6_get_dest_format(PictFormat format)
		284	{
		285	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
		286
		287	#if 0
		288
		289	switch (format) {
		290	default:
		291	return -1;
		292	case PICT_a8r8g8b8:
		293	case PICT_x8r8g8b8:
		294	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
		295	case PICT_a8b8g8r8:
		296	case PICT_x8b8g8r8:
		297	return GEN6_SURFACEFORMAT_R8G8B8A8_UNORM;
		298	case PICT_a2r10g10b10:
		299	case PICT_x2r10g10b10:
		300	return GEN6_SURFACEFORMAT_B10G10R10A2_UNORM;
		301	case PICT_r5g6b5:
		302	return GEN6_SURFACEFORMAT_B5G6R5_UNORM;
		303	case PICT_x1r5g5b5:
		304	case PICT_a1r5g5b5:
		305	return GEN6_SURFACEFORMAT_B5G5R5A1_UNORM;
		306	case PICT_a8:
		307	return GEN6_SURFACEFORMAT_A8_UNORM;
		308	case PICT_a4r4g4b4:
		309	case PICT_x4r4g4b4:
		310	return GEN6_SURFACEFORMAT_B4G4R4A4_UNORM;
		311	}
		312	#endif
		313
		314	}
		315
		316	#if 0
		317
		318	static bool gen6_check_dst_format(PictFormat format)
		319	{
		320	if (gen6_get_dest_format(format) != -1)
		321	return true;
		322
		323	DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
		324	return false;
		325	}
		326
		327	static bool gen6_check_format(uint32_t format)
		328	{
		329	if (gen6_get_card_format(format) != -1)
		330	return true;
		331
		332	DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
		333	return false;
		334	}
		335
		336	static uint32_t gen6_filter(uint32_t filter)
		337	{
		338	switch (filter) {
		339	default:
		340	assert(0);
		341	case PictFilterNearest:
		342	return SAMPLER_FILTER_NEAREST;
		343	case PictFilterBilinear:
		344	return SAMPLER_FILTER_BILINEAR;
		345	}
		346	}
		347
		348	static uint32_t gen6_check_filter(PicturePtr picture)
		349	{
		350	switch (picture->filter) {
		351	case PictFilterNearest:
		352	case PictFilterBilinear:
		353	return true;
		354	default:
		355	return false;
		356	}
		357	}
		358
		359	static uint32_t gen6_repeat(uint32_t repeat)
		360	{
		361	switch (repeat) {
		362	default:
		363	assert(0);
		364	case RepeatNone:
		365	return SAMPLER_EXTEND_NONE;
		366	case RepeatNormal:
		367	return SAMPLER_EXTEND_REPEAT;
		368	case RepeatPad:
		369	return SAMPLER_EXTEND_PAD;
		370	case RepeatReflect:
		371	return SAMPLER_EXTEND_REFLECT;
		372	}
		373	}
		374
		375	static bool gen6_check_repeat(PicturePtr picture)
		376	{
		377	if (!picture->repeat)
		378	return true;
		379
		380	switch (picture->repeatType) {
		381	case RepeatNone:
		382	case RepeatNormal:
		383	case RepeatPad:
		384	case RepeatReflect:
		385	return true;
		386	default:
		387	return false;
		388	}
		389	}
		390	#endif
		391
		392	static int
		393	gen6_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine)
		394	{
		395	int base;
		396
		397	if (has_mask) {
		398	if (is_ca) {
		399	if (gen6_blend_op[op].src_alpha)
		400	base = GEN6_WM_KERNEL_MASKSA;
		401	else
		402	base = GEN6_WM_KERNEL_MASKCA;
		403	} else
		404	base = GEN6_WM_KERNEL_MASK;
		405	} else
		406	base = GEN6_WM_KERNEL_NOMASK;
		407
		408	return base + !is_affine;
		409	}
		410
		411	static void
		412	gen6_emit_urb(struct sna *sna)
		413	{
		414	OUT_BATCH(GEN6_3DSTATE_URB \| (3 - 2));
		415	OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) \|
		416	(sna->render_state.gen6.info->urb.max_vs_entries << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
		417	OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) \|
		418	(0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
		419	}
		420
		421	static void
		422	gen6_emit_state_base_address(struct sna *sna)
		423	{
		424	OUT_BATCH(GEN6_STATE_BASE_ADDRESS \| (10 - 2));
		425	OUT_BATCH(0); /* general */
		426	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */
		427	sna->kgem.nbatch,
		428	NULL,
		429	I915_GEM_DOMAIN_INSTRUCTION << 16,
		430	BASE_ADDRESS_MODIFY));
		431	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */
		432	sna->kgem.nbatch,
		433	sna->render_state.gen6.general_bo,
		434	I915_GEM_DOMAIN_INSTRUCTION << 16,
		435	BASE_ADDRESS_MODIFY));
		436	OUT_BATCH(0); /* indirect */
		437	OUT_BATCH(kgem_add_reloc(&sna->kgem,
		438	sna->kgem.nbatch,
		439	sna->render_state.gen6.general_bo,
		440	I915_GEM_DOMAIN_INSTRUCTION << 16,
		441	BASE_ADDRESS_MODIFY));
		442
		443	/* upper bounds, disable */
		444	OUT_BATCH(0);
		445	OUT_BATCH(BASE_ADDRESS_MODIFY);
		446	OUT_BATCH(0);
		447	OUT_BATCH(BASE_ADDRESS_MODIFY);
		448	}
		449
		450	static void
		451	gen6_emit_viewports(struct sna *sna)
		452	{
		453	OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS \|
		454	GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC \|
		455	(4 - 2));
		456	OUT_BATCH(0);
		457	OUT_BATCH(0);
		458	OUT_BATCH(0);
		459	}
		460
		461	static void
		462	gen6_emit_vs(struct sna *sna)
		463	{
		464	/* disable VS constant buffer */
		465	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS \| (5 - 2));
		466	OUT_BATCH(0);
		467	OUT_BATCH(0);
		468	OUT_BATCH(0);
		469	OUT_BATCH(0);
		470
		471	OUT_BATCH(GEN6_3DSTATE_VS \| (6 - 2));
		472	OUT_BATCH(0); /* no VS kernel */
		473	OUT_BATCH(0);
		474	OUT_BATCH(0);
		475	OUT_BATCH(0);
		476	OUT_BATCH(0); /* pass-through */
		477	}
		478
		479	static void
		480	gen6_emit_gs(struct sna *sna)
		481	{
		482	/* disable GS constant buffer */
		483	OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS \| (5 - 2));
		484	OUT_BATCH(0);
		485	OUT_BATCH(0);
		486	OUT_BATCH(0);
		487	OUT_BATCH(0);
		488
		489	OUT_BATCH(GEN6_3DSTATE_GS \| (7 - 2));
		490	OUT_BATCH(0); /* no GS kernel */
		491	OUT_BATCH(0);
		492	OUT_BATCH(0);
		493	OUT_BATCH(0);
		494	OUT_BATCH(0);
		495	OUT_BATCH(0); /* pass-through */
		496	}
		497
		498	static void
		499	gen6_emit_clip(struct sna *sna)
		500	{
		501	OUT_BATCH(GEN6_3DSTATE_CLIP \| (4 - 2));
		502	OUT_BATCH(0);
		503	OUT_BATCH(0); /* pass-through */
		504	OUT_BATCH(0);
		505	}
		506
		507	static void
		508	gen6_emit_wm_constants(struct sna *sna)
		509	{
		510	/* disable WM constant buffer */
		511	OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS \| (5 - 2));
		512	OUT_BATCH(0);
		513	OUT_BATCH(0);
		514	OUT_BATCH(0);
		515	OUT_BATCH(0);
		516	}
		517
		518	static void
		519	gen6_emit_null_depth_buffer(struct sna *sna)
		520	{
		521	OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER \| (7 - 2));
		522	OUT_BATCH(GEN6_SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT \|
		523	GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
		524	OUT_BATCH(0);
		525	OUT_BATCH(0);
		526	OUT_BATCH(0);
		527	OUT_BATCH(0);
		528	OUT_BATCH(0);
		529
		530	OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS \| (2 - 2));
		531	OUT_BATCH(0);
		532	}
		533
		534	static void
		535	gen6_emit_invariant(struct sna *sna)
		536	{
		537	OUT_BATCH(GEN6_PIPELINE_SELECT \| PIPELINE_SELECT_3D);
		538
		539	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE \| (3 - 2));
		540	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER \|
		541	GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
		542	OUT_BATCH(0);
		543
		544	OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK \| (2 - 2));
		545	OUT_BATCH(1);
		546
		547	gen6_emit_urb(sna);
		548
		549	gen6_emit_state_base_address(sna);
		550
		551	gen6_emit_viewports(sna);
		552	gen6_emit_vs(sna);
		553	gen6_emit_gs(sna);
		554	gen6_emit_clip(sna);
		555	gen6_emit_wm_constants(sna);
		556	gen6_emit_null_depth_buffer(sna);
		557
		558	sna->render_state.gen6.needs_invariant = false;
		559	}
		560
		561	static bool
		562	gen6_emit_cc(struct sna *sna, int blend)
		563	{
		564	struct gen6_render_state *render = &sna->render_state.gen6;
		565
		566	if (render->blend == blend)
		567	return blend != NO_BLEND;
		568
		569	DBG(("%s: blend = %x\n", __FUNCTION__, blend));
		570
		571	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS \| (4 - 2));
		572	OUT_BATCH((render->cc_blend + blend) \| 1);
		573	if (render->blend == (unsigned)-1) {
		574	OUT_BATCH(1);
		575	OUT_BATCH(1);
		576	} else {
		577	OUT_BATCH(0);
		578	OUT_BATCH(0);
		579	}
		580
		581	render->blend = blend;
		582	return blend != NO_BLEND;
		583	}
		584
		585	static void
		586	gen6_emit_sampler(struct sna *sna, uint32_t state)
		587	{
		588	if (sna->render_state.gen6.samplers == state)
		589	return;
		590
		591	sna->render_state.gen6.samplers = state;
		592
		593	DBG(("%s: sampler = %x\n", __FUNCTION__, state));
		594
		595	OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS \|
		596	GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS \|
		597	(4 - 2));
		598	OUT_BATCH(0); /* VS */
		599	OUT_BATCH(0); /* GS */
		600	OUT_BATCH(sna->render_state.gen6.wm_state + state);
		601	}
		602
		603	static void
		604	gen6_emit_sf(struct sna *sna, bool has_mask)
		605	{
		606	int num_sf_outputs = has_mask ? 2 : 1;
		607
		608	if (sna->render_state.gen6.num_sf_outputs == num_sf_outputs)
		609	return;
		610
		611	DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n",
		612	__FUNCTION__, num_sf_outputs, 1, 0));
		613
		614	sna->render_state.gen6.num_sf_outputs = num_sf_outputs;
		615
		616	OUT_BATCH(GEN6_3DSTATE_SF \| (20 - 2));
		617	OUT_BATCH(num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT \|
		618	1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT \|
		619	1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT);
		620	OUT_BATCH(0);
		621	OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
		622	OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
		623	OUT_BATCH(0);
		624	OUT_BATCH(0);
		625	OUT_BATCH(0);
		626	OUT_BATCH(0);
		627	OUT_BATCH(0); /* DW9 */
		628	OUT_BATCH(0);
		629	OUT_BATCH(0);
		630	OUT_BATCH(0);
		631	OUT_BATCH(0);
		632	OUT_BATCH(0); /* DW14 */
		633	OUT_BATCH(0);
		634	OUT_BATCH(0);
		635	OUT_BATCH(0);
		636	OUT_BATCH(0);
		637	OUT_BATCH(0); /* DW19 */
		638	}
		639
		640	static void
		641	gen6_emit_wm(struct sna *sna, unsigned int kernel, bool has_mask)
		642	{
		643	const uint32_t *kernels;
		644
		645	if (sna->render_state.gen6.kernel == kernel)
		646	return;
		647
		648	sna->render_state.gen6.kernel = kernel;
		649	kernels = sna->render_state.gen6.wm_kernel[kernel];
		650
		651	DBG(("%s: switching to %s, num_surfaces=%d (8-pixel? %d, 16-pixel? %d,32-pixel? %d)\n",
		652	__FUNCTION__,
		653	wm_kernels[kernel].name, wm_kernels[kernel].num_surfaces,
		654	kernels[0], kernels[1], kernels[2]));
		655
		656	OUT_BATCH(GEN6_3DSTATE_WM \| (9 - 2));
		657	OUT_BATCH(kernels[0] ?: kernels[1] ?: kernels[2]);
		658	OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT \|
		659	wm_kernels[kernel].num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
		660	OUT_BATCH(0); /* scratch space */
		661	OUT_BATCH((kernels[0] ? 4 : kernels[1] ? 6 : 8) << GEN6_3DSTATE_WM_DISPATCH_0_START_GRF_SHIFT \|
		662	8 << GEN6_3DSTATE_WM_DISPATCH_1_START_GRF_SHIFT \|
		663	6 << GEN6_3DSTATE_WM_DISPATCH_2_START_GRF_SHIFT);
		664	OUT_BATCH((sna->render_state.gen6.info->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT \|
		665	(kernels[0] ? GEN6_3DSTATE_WM_8_DISPATCH_ENABLE : 0) \|
		666	(kernels[1] ? GEN6_3DSTATE_WM_16_DISPATCH_ENABLE : 0) \|
		667	(kernels[2] ? GEN6_3DSTATE_WM_32_DISPATCH_ENABLE : 0) \|
		668	GEN6_3DSTATE_WM_DISPATCH_ENABLE);
		669	OUT_BATCH((1 + has_mask) << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT \|
		670	GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
		671	OUT_BATCH(kernels[2]);
		672	OUT_BATCH(kernels[1]);
		673	}
		674
		675	static bool
		676	gen6_emit_binding_table(struct sna *sna, uint16_t offset)
		677	{
		678	if (sna->render_state.gen6.surface_table == offset)
		679	return false;
		680
		681	/* Binding table pointers */
		682	OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS \|
		683	GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS \|
		684	(4 - 2));
		685	OUT_BATCH(0); /* vs */
		686	OUT_BATCH(0); /* gs */
		687	/* Only the PS uses the binding table */
		688	OUT_BATCH(offset*4);
		689
		690	sna->render_state.gen6.surface_table = offset;
		691	return true;
		692	}
		693
		694	static bool
		695	gen6_emit_drawing_rectangle(struct sna *sna,
		696	const struct sna_composite_op *op)
		697	{
		698	uint32_t limit = (op->dst.height - 1) << 16 \| (op->dst.width - 1);
		699	uint32_t offset = (uint16_t)op->dst.y << 16 \| (uint16_t)op->dst.x;
		700
		701	assert(!too_large(op->dst.x, op->dst.y));
		702	assert(!too_large(op->dst.width, op->dst.height));
		703
		704	if (sna->render_state.gen6.drawrect_limit == limit &&
		705	sna->render_state.gen6.drawrect_offset == offset)
		706	return false;
		707
		708	/* [DevSNB-C+{W/A}] Before any depth stall flush (including those
		709	* produced by non-pipelined state commands), software needs to first
		710	* send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
		711	* 0.
		712	*
		713	* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
		714	* BEFORE the pipe-control with a post-sync op and no write-cache
		715	* flushes.
		716	*/
		717	if (!sna->render_state.gen6.first_state_packet) {
		718	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		719	OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL \|
		720	GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD);
		721	OUT_BATCH(0);
		722	OUT_BATCH(0);
		723	}
		724
		725	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		726	OUT_BATCH(GEN6_PIPE_CONTROL_WRITE_TIME);
		727	OUT_BATCH(kgem_add_reloc(&sna->kgem, sna->kgem.nbatch,
		728	sna->render_state.gen6.general_bo,
		729	I915_GEM_DOMAIN_INSTRUCTION << 16 \|
		730	I915_GEM_DOMAIN_INSTRUCTION,
		731	64));
		732	OUT_BATCH(0);
		733
		734	OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE \| (4 - 2));
		735	OUT_BATCH(0);
		736	OUT_BATCH(limit);
		737	OUT_BATCH(offset);
		738
		739	sna->render_state.gen6.drawrect_offset = offset;
		740	sna->render_state.gen6.drawrect_limit = limit;
		741	return true;
		742	}
		743
		744	static void
		745	gen6_emit_vertex_elements(struct sna *sna,
		746	const struct sna_composite_op *op)
		747	{
		748	/*
		749	* vertex data in vertex buffer
		750	* position: (x, y)
		751	* texture coordinate 0: (u0, v0) if (is_affine is true) else (u0, v0, w0)
		752	* texture coordinate 1 if (has_mask is true): same as above
		753	*/
		754	struct gen6_render_state *render = &sna->render_state.gen6;
		755	uint32_t src_format, dw;
		756	int id = GEN6_VERTEX(op->u.gen6.flags);
		757	bool has_mask;
		758
		759	DBG(("%s: setup id=%d\n", __FUNCTION__, id));
		760
		761	if (render->ve_id == id)
		762	return;
		763	render->ve_id = id;
		764
		765	/* The VUE layout
		766	* dword 0-3: pad (0.0, 0.0, 0.0. 0.0)
		767	* dword 4-7: position (x, y, 1.0, 1.0),
		768	* dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0)
		769	* dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0)
		770	*
		771	* dword 4-15 are fetched from vertex buffer
		772	*/
		773	has_mask = (id >> 2) != 0;
		774	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS \|
		775	((2 * (3 + has_mask)) + 1 - 2));
		776
		777	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		778	GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT \|
		779
		780	OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT \|
		781	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT \|
		782	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT \|
		783	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
		784
		785	/* x,y */
		786	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		787	GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT \|
		788
		789	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT \|
		790	GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT \|
		791	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT \|
		792	GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
		793
		794	/* u0, v0, w0 */
		795	DBG(("%s: first channel %d floats, offset=4b\n", __FUNCTION__, id & 3));
		796	dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
		797	switch (id & 3) {
		798	default:
		799	assert(0);
		800	case 0:
		801	src_format = GEN6_SURFACEFORMAT_R16G16_SSCALED;
		802	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		803	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		804	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		805	break;
		806	case 1:
		807	src_format = GEN6_SURFACEFORMAT_R32_FLOAT;
		808	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		809	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT;
		810	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		811	break;
		812	case 2:
		813	src_format = GEN6_SURFACEFORMAT_R32G32_FLOAT;
		814	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		815	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		816	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		817	break;
		818	case 3:
		819	src_format = GEN6_SURFACEFORMAT_R32G32B32_FLOAT;
		820	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		821	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		822	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT;
		823	break;
		824	}
		825	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		826	src_format << VE0_FORMAT_SHIFT \|
		827	4 << VE0_OFFSET_SHIFT);
		828	OUT_BATCH(dw);
		829
		830	/* u1, v1, w1 */
		831	if (has_mask) {
		832	unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float);
		833	DBG(("%s: second channel %d floats, offset=%db\n", __FUNCTION__, id >> 2, offset));
		834	dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
		835	switch (id >> 2) {
		836	case 1:
		837	src_format = GEN6_SURFACEFORMAT_R32_FLOAT;
		838	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		839	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT;
		840	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		841	break;
		842	default:
		843	assert(0);
		844	case 2:
		845	src_format = GEN6_SURFACEFORMAT_R32G32_FLOAT;
		846	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		847	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		848	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		849	break;
		850	case 3:
		851	src_format = GEN6_SURFACEFORMAT_R32G32B32_FLOAT;
		852	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		853	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		854	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT;
		855	break;
		856	}
		857	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		858	src_format << VE0_FORMAT_SHIFT \|
		859	offset << VE0_OFFSET_SHIFT);
		860	OUT_BATCH(dw);
		861	}
		862	}
		863
		864	static void
		865	gen6_emit_flush(struct sna *sna)
		866	{
		867	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		868	OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH \|
		869	GEN6_PIPE_CONTROL_TC_FLUSH \|
		870	GEN6_PIPE_CONTROL_CS_STALL);
		871	OUT_BATCH(0);
		872	OUT_BATCH(0);
		873	}
		874
		875	static void
		876	gen6_emit_state(struct sna *sna,
		877	const struct sna_composite_op *op,
		878	uint16_t wm_binding_table)
		879	{
4501	Serge	880	bool need_flush, need_stall;
4304	Serge	881
		882	assert(op->dst.bo->exec);
		883
4501	Serge	884	need_flush =
		885	gen6_emit_cc(sna, GEN6_BLEND(op->u.gen6.flags)) &&
		886	wm_binding_table & 1;
4304	Serge	887	gen6_emit_sampler(sna, GEN6_SAMPLER(op->u.gen6.flags));
		888	gen6_emit_sf(sna, GEN6_VERTEX(op->u.gen6.flags) >> 2);
		889	gen6_emit_wm(sna, GEN6_KERNEL(op->u.gen6.flags), GEN6_VERTEX(op->u.gen6.flags) >> 2);
		890	gen6_emit_vertex_elements(sna, op);
		891
4501	Serge	892	need_stall = gen6_emit_binding_table(sna, wm_binding_table & ~1);
4304	Serge	893	if (gen6_emit_drawing_rectangle(sna, op))
		894	need_stall = false;
4501	Serge	895	if (need_flush \|\| kgem_bo_is_dirty(op->src.bo) \|\| kgem_bo_is_dirty(op->mask.bo)) {
4304	Serge	896	gen6_emit_flush(sna);
		897	kgem_clear_dirty(&sna->kgem);
		898	assert(op->dst.bo->exec);
		899	kgem_bo_mark_dirty(op->dst.bo);
		900	need_stall = false;
		901	}
		902	if (need_stall) {
		903	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		904	OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL \|
		905	GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD);
		906	OUT_BATCH(0);
		907	OUT_BATCH(0);
		908	}
		909	sna->render_state.gen6.first_state_packet = false;
		910	}
		911
		912	static bool gen6_magic_ca_pass(struct sna *sna,
		913	const struct sna_composite_op *op)
		914	{
		915	struct gen6_render_state *state = &sna->render_state.gen6;
		916
		917	if (!op->need_magic_ca_pass)
		918	return false;
		919
		920	DBG(("%s: CA fixup (%d -> %d)\n", __FUNCTION__,
		921	sna->render.vertex_start, sna->render.vertex_index));
		922
		923	gen6_emit_flush(sna);
		924
		925	gen6_emit_cc(sna, gen6_get_blend(PictOpAdd, true, op->dst.format));
		926	gen6_emit_wm(sna,
		927	gen6_choose_composite_kernel(PictOpAdd,
		928	true, true,
		929	op->is_affine),
		930	true);
		931
		932	OUT_BATCH(GEN6_3DPRIMITIVE \|
		933	GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL \|
		934	_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT \|
		935
		936	4);
		937	OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
		938	OUT_BATCH(sna->render.vertex_start);
		939	OUT_BATCH(1); /* single instance */
		940	OUT_BATCH(0); /* start instance location */
		941	OUT_BATCH(0); /* index buffer offset, ignored */
		942
		943	state->last_primitive = sna->kgem.nbatch;
		944	return true;
		945	}
		946
		947	typedef struct gen6_surface_state_padded {
		948	struct gen6_surface_state state;
		949	char pad[32 - sizeof(struct gen6_surface_state)];
		950	} gen6_surface_state_padded;
		951
		952	static void null_create(struct sna_static_stream *stream)
		953	{
		954	/* A bunch of zeros useful for legacy border color and depth-stencil */
		955	sna_static_stream_map(stream, 64, 64);
		956	}
		957
		958	static void scratch_create(struct sna_static_stream *stream)
		959	{
		960	/* 64 bytes of scratch space for random writes, such as
		961	* the pipe-control w/a.
		962	*/
		963	sna_static_stream_map(stream, 64, 64);
		964	}
		965
		966	static void
		967	sampler_state_init(struct gen6_sampler_state *sampler_state,
		968	sampler_filter_t filter,
		969	sampler_extend_t extend)
		970	{
		971	sampler_state->ss0.lod_preclamp = 1; /* GL mode */
		972
		973	/* We use the legacy mode to get the semantics specified by
		974	* the Render extension. */
		975	sampler_state->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
		976
		977	switch (filter) {
		978	default:
		979	case SAMPLER_FILTER_NEAREST:
		980	sampler_state->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
		981	sampler_state->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
		982	break;
		983	case SAMPLER_FILTER_BILINEAR:
		984	sampler_state->ss0.min_filter = GEN6_MAPFILTER_LINEAR;
		985	sampler_state->ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
		986	break;
		987	}
		988
		989	switch (extend) {
		990	default:
		991	case SAMPLER_EXTEND_NONE:
		992	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
		993	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
		994	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
		995	break;
		996	case SAMPLER_EXTEND_REPEAT:
		997	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
		998	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
		999	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
		1000	break;
		1001	case SAMPLER_EXTEND_PAD:
		1002	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
		1003	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
		1004	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
		1005	break;
		1006	case SAMPLER_EXTEND_REFLECT:
		1007	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
		1008	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
		1009	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
		1010	break;
		1011	}
		1012	}
		1013
		1014	static void
		1015	sampler_copy_init(struct gen6_sampler_state *ss)
		1016	{
		1017	sampler_state_init(ss, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
		1018	ss->ss3.non_normalized_coord = 1;
		1019
		1020	sampler_state_init(ss+1, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
		1021	}
		1022
		1023	static void
		1024	sampler_fill_init(struct gen6_sampler_state *ss)
		1025	{
		1026	sampler_state_init(ss, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_REPEAT);
		1027	ss->ss3.non_normalized_coord = 1;
		1028
		1029	sampler_state_init(ss+1, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
		1030	}
		1031
		1032	static uint32_t
		1033	gen6_tiling_bits(uint32_t tiling)
		1034	{
		1035	switch (tiling) {
		1036	default: assert(0);
		1037	case I915_TILING_NONE: return 0;
		1038	case I915_TILING_X: return GEN6_SURFACE_TILED;
		1039	case I915_TILING_Y: return GEN6_SURFACE_TILED \| GEN6_SURFACE_TILED_Y;
		1040	}
		1041	}
		1042
		1043	/**
		1044	* Sets up the common fields for a surface state buffer for the given
		1045	* picture in the given surface state buffer.
		1046	*/
		1047	static int
		1048	gen6_bind_bo(struct sna *sna,
		1049	struct kgem_bo *bo,
		1050	uint32_t width,
		1051	uint32_t height,
		1052	uint32_t format,
		1053	bool is_dst)
		1054	{
		1055	uint32_t *ss;
		1056	uint32_t domains;
		1057	uint16_t offset;
		1058	uint32_t is_scanout = is_dst && bo->scanout;
		1059
		1060	/* After the first bind, we manage the cache domains within the batch */
		1061	offset = kgem_bo_get_binding(bo, format \| is_dst << 30 \| is_scanout << 31);
		1062	if (offset) {
		1063	DBG(("[%x] bo(handle=%d), format=%d, reuse %s binding\n",
		1064	offset, bo->handle, format,
		1065	is_dst ? "render" : "sampler"));
		1066	if (is_dst)
		1067	kgem_bo_mark_dirty(bo);
		1068	return offset * sizeof(uint32_t);
		1069	}
		1070
		1071	offset = sna->kgem.surface -=
		1072	sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1073	ss = sna->kgem.batch + offset;
		1074	ss[0] = (GEN6_SURFACE_2D << GEN6_SURFACE_TYPE_SHIFT \|
		1075	GEN6_SURFACE_BLEND_ENABLED \|
		1076	format << GEN6_SURFACE_FORMAT_SHIFT);
		1077	if (is_dst) {
		1078	ss[0] \|= GEN6_SURFACE_RC_READ_WRITE;
		1079	domains = I915_GEM_DOMAIN_RENDER << 16 \|I915_GEM_DOMAIN_RENDER;
		1080	} else
		1081	domains = I915_GEM_DOMAIN_SAMPLER << 16;
		1082	ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
		1083	ss[2] = ((width - 1) << GEN6_SURFACE_WIDTH_SHIFT \|
		1084	(height - 1) << GEN6_SURFACE_HEIGHT_SHIFT);
		1085	assert(bo->pitch <= (1 << 18));
		1086	ss[3] = (gen6_tiling_bits(bo->tiling) \|
		1087	(bo->pitch - 1) << GEN6_SURFACE_PITCH_SHIFT);
		1088	ss[4] = 0;
		1089	ss[5] = (is_scanout \|\| bo->io) ? 0 : 3 << 16;
		1090
		1091	kgem_bo_set_binding(bo, format \| is_dst << 30 \| is_scanout << 31, offset);
		1092
		1093	DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
		1094	offset, bo->handle, ss[1],
		1095	format, width, height, bo->pitch, bo->tiling,
		1096	domains & 0xffff ? "render" : "sampler"));
		1097
		1098	return offset * sizeof(uint32_t);
		1099	}
		1100
		1101	static void gen6_emit_vertex_buffer(struct sna *sna,
		1102	const struct sna_composite_op *op)
		1103	{
		1104	int id = GEN6_VERTEX(op->u.gen6.flags);
		1105
		1106	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS \| 3);
		1107	OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT \| VB0_VERTEXDATA \|
		1108	4*op->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT);
		1109	sna->render.vertex_reloc[sna->render.nvertex_reloc++] = sna->kgem.nbatch;
		1110	OUT_BATCH(0);
		1111	OUT_BATCH(~0); /* max address: disabled */
		1112	OUT_BATCH(0);
		1113
		1114	sna->render.vb_id \|= 1 << id;
		1115	}
		1116
		1117	static void gen6_emit_primitive(struct sna *sna)
		1118	{
		1119	if (sna->kgem.nbatch == sna->render_state.gen6.last_primitive) {
		1120	DBG(("%s: continuing previous primitive, start=%d, index=%d\n",
		1121	__FUNCTION__,
		1122	sna->render.vertex_start,
		1123	sna->render.vertex_index));
		1124	sna->render.vertex_offset = sna->kgem.nbatch - 5;
		1125	return;
		1126	}
		1127
		1128	OUT_BATCH(GEN6_3DPRIMITIVE \|
		1129	GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL \|
		1130	_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT \|
		1131
		1132	4);
		1133	sna->render.vertex_offset = sna->kgem.nbatch;
		1134	OUT_BATCH(0); /* vertex count, to be filled in later */
		1135	OUT_BATCH(sna->render.vertex_index);
		1136	OUT_BATCH(1); /* single instance */
		1137	OUT_BATCH(0); /* start instance location */
		1138	OUT_BATCH(0); /* index buffer offset, ignored */
		1139	sna->render.vertex_start = sna->render.vertex_index;
		1140	DBG(("%s: started new primitive: index=%d\n",
		1141	__FUNCTION__, sna->render.vertex_start));
		1142
		1143	sna->render_state.gen6.last_primitive = sna->kgem.nbatch;
		1144	}
		1145
		1146	static bool gen6_rectangle_begin(struct sna *sna,
		1147	const struct sna_composite_op *op)
		1148	{
		1149	int id = 1 << GEN6_VERTEX(op->u.gen6.flags);
		1150	int ndwords;
		1151
		1152	if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset)
		1153	return true;
		1154
		1155	ndwords = op->need_magic_ca_pass ? 60 : 6;
		1156	if ((sna->render.vb_id & id) == 0)
		1157	ndwords += 5;
		1158	if (!kgem_check_batch(&sna->kgem, ndwords))
		1159	return false;
		1160
		1161	if ((sna->render.vb_id & id) == 0)
		1162	gen6_emit_vertex_buffer(sna, op);
		1163
		1164	gen6_emit_primitive(sna);
		1165	return true;
		1166	}
		1167
		1168	static int gen6_get_rectangles__flush(struct sna *sna,
		1169	const struct sna_composite_op *op)
		1170	{
		1171	/* Preventing discarding new vbo after lock contention */
		1172	if (sna_vertex_wait__locked(&sna->render)) {
		1173	int rem = vertex_space(sna);
		1174	if (rem > op->floats_per_rect)
		1175	return rem;
		1176	}
		1177
		1178	if (!kgem_check_batch(&sna->kgem, op->need_magic_ca_pass ? 65 : 5))
		1179	return 0;
		1180	if (!kgem_check_reloc_and_exec(&sna->kgem, 2))
		1181	return 0;
		1182
		1183	if (sna->render.vertex_offset) {
		1184	gen4_vertex_flush(sna);
		1185	if (gen6_magic_ca_pass(sna, op)) {
		1186	gen6_emit_flush(sna);
		1187	gen6_emit_cc(sna, GEN6_BLEND(op->u.gen6.flags));
		1188	gen6_emit_wm(sna,
		1189	GEN6_KERNEL(op->u.gen6.flags),
		1190	GEN6_VERTEX(op->u.gen6.flags) >> 2);
		1191	}
		1192	}
		1193
		1194	return gen4_vertex_finish(sna);
		1195	}
		1196
		1197	inline static int gen6_get_rectangles(struct sna *sna,
		1198	const struct sna_composite_op *op,
		1199	int want,
		1200	void (emit_state)(struct sna , const struct sna_composite_op *op))
		1201	{
		1202	int rem;
		1203
		1204	assert(want);
		1205
		1206	start:
		1207	rem = vertex_space(sna);
		1208	if (unlikely(rem < op->floats_per_rect)) {
		1209	DBG(("flushing vbo for %s: %d < %d\n",
		1210	__FUNCTION__, rem, op->floats_per_rect));
		1211	rem = gen6_get_rectangles__flush(sna, op);
		1212	if (unlikely(rem == 0))
		1213	goto flush;
		1214	}
		1215
		1216	if (unlikely(sna->render.vertex_offset == 0)) {
		1217	if (!gen6_rectangle_begin(sna, op))
		1218	goto flush;
		1219	else
		1220	goto start;
		1221	}
		1222
		1223	assert(rem <= vertex_space(sna));
		1224	assert(op->floats_per_rect <= rem);
		1225	if (want > 1 && want * op->floats_per_rect > rem)
		1226	want = rem / op->floats_per_rect;
		1227
		1228	assert(want > 0);
		1229	sna->render.vertex_index += 3*want;
		1230	return want;
		1231
		1232	flush:
		1233	if (sna->render.vertex_offset) {
		1234	gen4_vertex_flush(sna);
		1235	gen6_magic_ca_pass(sna, op);
		1236	}
		1237	sna_vertex_wait__locked(&sna->render);
		1238	_kgem_submit(&sna->kgem);
		1239	emit_state(sna, op);
		1240	goto start;
		1241	}
		1242
		1243	inline static uint32_t gen6_composite_get_binding_table(struct sna sna,
		1244	uint16_t *offset)
		1245	{
		1246	uint32_t *table;
		1247
		1248	sna->kgem.surface -=
		1249	sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1250	/* Clear all surplus entries to zero in case of prefetch */
		1251	table = memset(sna->kgem.batch + sna->kgem.surface,
		1252	0, sizeof(struct gen6_surface_state_padded));
		1253
		1254	DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface));
		1255
		1256	*offset = sna->kgem.surface;
		1257	return table;
		1258	}
		1259
		1260	static bool
		1261	gen6_get_batch(struct sna sna, const struct sna_composite_op op)
		1262	{
		1263	kgem_set_mode(&sna->kgem, KGEM_RENDER, op->dst.bo);
		1264
		1265	if (!kgem_check_batch_with_surfaces(&sna->kgem, 150, 4)) {
		1266	DBG(("%s: flushing batch: %d < %d+%d\n",
		1267	__FUNCTION__, sna->kgem.surface - sna->kgem.nbatch,
		1268	150, 4*8));
		1269	kgem_submit(&sna->kgem);
		1270	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		1271	}
		1272
		1273	if (sna->render_state.gen6.needs_invariant)
		1274	gen6_emit_invariant(sna);
		1275
		1276	return kgem_bo_is_dirty(op->dst.bo);
		1277	}
		1278
		1279	static void gen6_emit_composite_state(struct sna *sna,
		1280	const struct sna_composite_op *op)
		1281	{
		1282	uint32_t *binding_table;
		1283	uint16_t offset;
		1284	bool dirty;
		1285
		1286	dirty = gen6_get_batch(sna, op);
		1287
		1288	binding_table = gen6_composite_get_binding_table(sna, &offset);
		1289
		1290	binding_table[0] =
		1291	gen6_bind_bo(sna,
		1292	op->dst.bo, op->dst.width, op->dst.height,
		1293	gen6_get_dest_format(op->dst.format),
		1294	true);
		1295	binding_table[1] =
		1296	gen6_bind_bo(sna,
		1297	op->src.bo, op->src.width, op->src.height,
		1298	op->src.card_format,
		1299	false);
		1300	if (op->mask.bo) {
		1301	binding_table[2] =
		1302	gen6_bind_bo(sna,
		1303	op->mask.bo,
		1304	op->mask.width,
		1305	op->mask.height,
		1306	op->mask.card_format,
		1307	false);
		1308	}
		1309
		1310	if (sna->kgem.surface == offset &&
		1311	(uint64_t )(sna->kgem.batch + sna->render_state.gen6.surface_table) == (uint64_t)binding_table &&
		1312	(op->mask.bo == NULL \|\|
		1313	sna->kgem.batch[sna->render_state.gen6.surface_table+2] == binding_table[2])) {
		1314	sna->kgem.surface += sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1315	offset = sna->render_state.gen6.surface_table;
		1316	}
		1317
		1318	gen6_emit_state(sna, op, offset \| dirty);
		1319	}
		1320
		1321	static void
		1322	gen6_align_vertex(struct sna sna, const struct sna_composite_op op)
		1323	{
		1324	assert (sna->render.vertex_offset == 0);
		1325	if (op->floats_per_vertex != sna->render_state.gen6.floats_per_vertex) {
4501	Serge	1326	DBG(("aligning vertex: was %d, now %d floats per vertex\n",
4304	Serge	1327	sna->render_state.gen6.floats_per_vertex,
4501	Serge	1328	op->floats_per_vertex));
		1329	gen4_vertex_align(sna, op);
4304	Serge	1330	sna->render_state.gen6.floats_per_vertex = op->floats_per_vertex;
		1331	}
		1332	assert((sna->render.vertex_used % op->floats_per_vertex) == 0);
		1333	}
		1334
		1335	fastcall static void
		1336	gen6_render_composite_blt(struct sna *sna,
		1337	const struct sna_composite_op *op,
		1338	const struct sna_composite_rectangles *r)
		1339	{
		1340	gen6_get_rectangles(sna, op, 1, gen6_emit_composite_state);
		1341	op->prim_emit(sna, op, r);
		1342	}
		1343
		1344	#if 0
		1345	fastcall static void
		1346	gen6_render_composite_box(struct sna *sna,
		1347	const struct sna_composite_op *op,
		1348	const BoxRec *box)
		1349	{
		1350	struct sna_composite_rectangles r;
		1351
		1352	gen6_get_rectangles(sna, op, 1, gen6_emit_composite_state);
		1353
		1354	DBG((" %s: (%d, %d), (%d, %d)\n",
		1355	__FUNCTION__,
		1356	box->x1, box->y1, box->x2, box->y2));
		1357
		1358	r.dst.x = box->x1;
		1359	r.dst.y = box->y1;
		1360	r.width = box->x2 - box->x1;
		1361	r.height = box->y2 - box->y1;
		1362	r.src = r.mask = r.dst;
		1363
		1364	op->prim_emit(sna, op, &r);
		1365	}
		1366
		1367	static void
		1368	gen6_render_composite_boxes__blt(struct sna *sna,
		1369	const struct sna_composite_op *op,
		1370	const BoxRec *box, int nbox)
		1371	{
		1372	DBG(("composite_boxes(%d)\n", nbox));
		1373
		1374	do {
		1375	int nbox_this_time;
		1376
		1377	nbox_this_time = gen6_get_rectangles(sna, op, nbox,
		1378	gen6_emit_composite_state);
		1379	nbox -= nbox_this_time;
		1380
		1381	do {
		1382	struct sna_composite_rectangles r;
		1383
		1384	DBG((" %s: (%d, %d), (%d, %d)\n",
		1385	__FUNCTION__,
		1386	box->x1, box->y1, box->x2, box->y2));
		1387
		1388	r.dst.x = box->x1;
		1389	r.dst.y = box->y1;
		1390	r.width = box->x2 - box->x1;
		1391	r.height = box->y2 - box->y1;
		1392	r.src = r.mask = r.dst;
		1393
		1394	op->prim_emit(sna, op, &r);
		1395	box++;
		1396	} while (--nbox_this_time);
		1397	} while (nbox);
		1398	}
		1399
		1400	static void
		1401	gen6_render_composite_boxes(struct sna *sna,
		1402	const struct sna_composite_op *op,
		1403	const BoxRec *box, int nbox)
		1404	{
		1405	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
		1406
		1407	do {
		1408	int nbox_this_time;
		1409	float *v;
		1410
		1411	nbox_this_time = gen6_get_rectangles(sna, op, nbox,
		1412	gen6_emit_composite_state);
		1413	assert(nbox_this_time);
		1414	nbox -= nbox_this_time;
		1415
		1416	v = sna->render.vertices + sna->render.vertex_used;
		1417	sna->render.vertex_used += nbox_this_time * op->floats_per_rect;
		1418
		1419	op->emit_boxes(op, box, nbox_this_time, v);
		1420	box += nbox_this_time;
		1421	} while (nbox);
		1422	}
		1423
		1424	static void
		1425	gen6_render_composite_boxes__thread(struct sna *sna,
		1426	const struct sna_composite_op *op,
		1427	const BoxRec *box, int nbox)
		1428	{
		1429	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
		1430
		1431	sna_vertex_lock(&sna->render);
		1432	do {
		1433	int nbox_this_time;
		1434	float *v;
		1435
		1436	nbox_this_time = gen6_get_rectangles(sna, op, nbox,
		1437	gen6_emit_composite_state);
		1438	assert(nbox_this_time);
		1439	nbox -= nbox_this_time;
		1440
		1441	v = sna->render.vertices + sna->render.vertex_used;
		1442	sna->render.vertex_used += nbox_this_time * op->floats_per_rect;
		1443
		1444	sna_vertex_acquire__locked(&sna->render);
		1445	sna_vertex_unlock(&sna->render);
		1446
		1447	op->emit_boxes(op, box, nbox_this_time, v);
		1448	box += nbox_this_time;
		1449
		1450	sna_vertex_lock(&sna->render);
		1451	sna_vertex_release__locked(&sna->render);
		1452	} while (nbox);
		1453	sna_vertex_unlock(&sna->render);
		1454	}
		1455	#endif
		1456
		1457	#ifndef MAX
		1458	#define MAX(a,b) ((a) > (b) ? (a) : (b))
		1459	#endif
		1460
		1461	static uint32_t
		1462	gen6_composite_create_blend_state(struct sna_static_stream *stream)
		1463	{
		1464	char base, ptr;
		1465	int src, dst;
		1466
		1467	base = sna_static_stream_map(stream,
		1468	GEN6_BLENDFACTOR_COUNT * GEN6_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE,
		1469	64);
		1470
		1471	ptr = base;
		1472	for (src = 0; src < GEN6_BLENDFACTOR_COUNT; src++) {
		1473	for (dst= 0; dst < GEN6_BLENDFACTOR_COUNT; dst++) {
		1474	struct gen6_blend_state *blend =
		1475	(struct gen6_blend_state *)ptr;
		1476
		1477	blend->blend0.dest_blend_factor = dst;
		1478	blend->blend0.source_blend_factor = src;
		1479	blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
		1480	blend->blend0.blend_enable =
		1481	!(dst == GEN6_BLENDFACTOR_ZERO && src == GEN6_BLENDFACTOR_ONE);
		1482
		1483	blend->blend1.post_blend_clamp_enable = 1;
		1484	blend->blend1.pre_blend_clamp_enable = 1;
		1485
		1486	ptr += GEN6_BLEND_STATE_PADDED_SIZE;
		1487	}
		1488	}
		1489
		1490	return sna_static_stream_offsetof(stream, base);
		1491	}
		1492
		1493	#if 0
		1494	static uint32_t gen6_bind_video_source(struct sna *sna,
		1495	struct kgem_bo *src_bo,
		1496	uint32_t src_offset,
		1497	int src_width,
		1498	int src_height,
		1499	int src_pitch,
		1500	uint32_t src_surf_format)
		1501	{
		1502	struct gen6_surface_state *ss;
		1503
		1504	sna->kgem.surface -= sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1505
		1506	ss = memset(sna->kgem.batch + sna->kgem.surface, 0, sizeof(*ss));
		1507	ss->ss0.surface_type = GEN6_SURFACE_2D;
		1508	ss->ss0.surface_format = src_surf_format;
		1509
		1510	ss->ss1.base_addr =
		1511	kgem_add_reloc(&sna->kgem,
		1512	sna->kgem.surface + 1,
		1513	src_bo,
		1514	I915_GEM_DOMAIN_SAMPLER << 16,
		1515	src_offset);
		1516
		1517	ss->ss2.width = src_width - 1;
		1518	ss->ss2.height = src_height - 1;
		1519	ss->ss3.pitch = src_pitch - 1;
		1520
		1521	return sna->kgem.surface * sizeof(uint32_t);
		1522	}
		1523
		1524	static void gen6_emit_video_state(struct sna *sna,
		1525	const struct sna_composite_op *op)
		1526	{
		1527	struct sna_video_frame *frame = op->priv;
		1528	uint32_t src_surf_format;
		1529	uint32_t src_surf_base[6];
		1530	int src_width[6];
		1531	int src_height[6];
		1532	int src_pitch[6];
		1533	uint32_t *binding_table;
		1534	uint16_t offset;
		1535	bool dirty;
		1536	int n_src, n;
		1537
		1538	dirty = gen6_get_batch(sna, op);
		1539
		1540	src_surf_base[0] = 0;
		1541	src_surf_base[1] = 0;
		1542	src_surf_base[2] = frame->VBufOffset;
		1543	src_surf_base[3] = frame->VBufOffset;
		1544	src_surf_base[4] = frame->UBufOffset;
		1545	src_surf_base[5] = frame->UBufOffset;
		1546
		1547	if (is_planar_fourcc(frame->id)) {
		1548	src_surf_format = GEN6_SURFACEFORMAT_R8_UNORM;
		1549	src_width[1] = src_width[0] = frame->width;
		1550	src_height[1] = src_height[0] = frame->height;
		1551	src_pitch[1] = src_pitch[0] = frame->pitch[1];
		1552	src_width[4] = src_width[5] = src_width[2] = src_width[3] =
		1553	frame->width / 2;
		1554	src_height[4] = src_height[5] = src_height[2] = src_height[3] =
		1555	frame->height / 2;
		1556	src_pitch[4] = src_pitch[5] = src_pitch[2] = src_pitch[3] =
		1557	frame->pitch[0];
		1558	n_src = 6;
		1559	} else {
		1560	if (frame->id == FOURCC_UYVY)
		1561	src_surf_format = GEN6_SURFACEFORMAT_YCRCB_SWAPY;
		1562	else
		1563	src_surf_format = GEN6_SURFACEFORMAT_YCRCB_NORMAL;
		1564
		1565	src_width[0] = frame->width;
		1566	src_height[0] = frame->height;
		1567	src_pitch[0] = frame->pitch[0];
		1568	n_src = 1;
		1569	}
		1570
		1571	binding_table = gen6_composite_get_binding_table(sna, &offset);
		1572
		1573	binding_table[0] =
		1574	gen6_bind_bo(sna,
		1575	op->dst.bo, op->dst.width, op->dst.height,
		1576	gen6_get_dest_format(op->dst.format),
		1577	true);
		1578	for (n = 0; n < n_src; n++) {
		1579	binding_table[1+n] =
		1580	gen6_bind_video_source(sna,
		1581	frame->bo,
		1582	src_surf_base[n],
		1583	src_width[n],
		1584	src_height[n],
		1585	src_pitch[n],
		1586	src_surf_format);
		1587	}
		1588
		1589	gen6_emit_state(sna, op, offset \| dirty);
		1590	}
		1591
		1592	static bool
		1593	gen6_render_video(struct sna *sna,
		1594	struct sna_video *video,
		1595	struct sna_video_frame *frame,
		1596	RegionPtr dstRegion,
		1597	PixmapPtr pixmap)
		1598	{
		1599	struct sna_composite_op tmp;
		1600	int dst_width = dstRegion->extents.x2 - dstRegion->extents.x1;
		1601	int dst_height = dstRegion->extents.y2 - dstRegion->extents.y1;
		1602	int src_width = frame->src.x2 - frame->src.x1;
		1603	int src_height = frame->src.y2 - frame->src.y1;
		1604	float src_offset_x, src_offset_y;
		1605	float src_scale_x, src_scale_y;
		1606	int nbox, pix_xoff, pix_yoff;
		1607	struct sna_pixmap *priv;
		1608	unsigned filter;
		1609	BoxPtr box;
		1610
		1611	DBG(("%s: src=(%d, %d), dst=(%d, %d), %ldx[(%d, %d), (%d, %d)...]\n",
		1612	__FUNCTION__,
		1613	src_width, src_height, dst_width, dst_height,
		1614	(long)REGION_NUM_RECTS(dstRegion),
		1615	REGION_EXTENTS(NULL, dstRegion)->x1,
		1616	REGION_EXTENTS(NULL, dstRegion)->y1,
		1617	REGION_EXTENTS(NULL, dstRegion)->x2,
		1618	REGION_EXTENTS(NULL, dstRegion)->y2));
		1619
		1620	priv = sna_pixmap_force_to_gpu(pixmap, MOVE_READ \| MOVE_WRITE);
		1621	if (priv == NULL)
		1622	return false;
		1623
		1624	memset(&tmp, 0, sizeof(tmp));
		1625
		1626	tmp.dst.pixmap = pixmap;
		1627	tmp.dst.width = pixmap->drawable.width;
		1628	tmp.dst.height = pixmap->drawable.height;
		1629	tmp.dst.format = sna_render_format_for_depth(pixmap->drawable.depth);
		1630	tmp.dst.bo = priv->gpu_bo;
		1631
		1632	tmp.src.bo = frame->bo;
		1633	tmp.mask.bo = NULL;
		1634
		1635	tmp.floats_per_vertex = 3;
		1636	tmp.floats_per_rect = 9;
		1637
		1638	if (src_width == dst_width && src_height == dst_height)
		1639	filter = SAMPLER_FILTER_NEAREST;
		1640	else
		1641	filter = SAMPLER_FILTER_BILINEAR;
		1642
		1643	tmp.u.gen6.flags =
		1644	GEN6_SET_FLAGS(SAMPLER_OFFSET(filter, SAMPLER_EXTEND_PAD,
		1645	SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE),
		1646	NO_BLEND,
		1647	is_planar_fourcc(frame->id) ?
		1648	GEN6_WM_KERNEL_VIDEO_PLANAR :
		1649	GEN6_WM_KERNEL_VIDEO_PACKED,
		1650	2);
		1651	tmp.priv = frame;
		1652
		1653	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp.dst.bo);
		1654	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)) {
		1655	kgem_submit(&sna->kgem);
		1656	assert(kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL));
		1657	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		1658	}
		1659
4501	Serge	1660	gen6_align_vertex(sna, &tmp);
4304	Serge	1661	gen6_emit_video_state(sna, &tmp);
		1662
		1663	/* Set up the offset for translating from the given region (in screen
		1664	* coordinates) to the backing pixmap.
		1665	*/
		1666	#ifdef COMPOSITE
		1667	pix_xoff = -pixmap->screen_x + pixmap->drawable.x;
		1668	pix_yoff = -pixmap->screen_y + pixmap->drawable.y;
		1669	#else
		1670	pix_xoff = 0;
		1671	pix_yoff = 0;
		1672	#endif
		1673
		1674	src_scale_x = (float)src_width / dst_width / frame->width;
		1675	src_offset_x = (float)frame->src.x1 / frame->width - dstRegion->extents.x1 * src_scale_x;
		1676
		1677	src_scale_y = (float)src_height / dst_height / frame->height;
		1678	src_offset_y = (float)frame->src.y1 / frame->height - dstRegion->extents.y1 * src_scale_y;
		1679
		1680	box = REGION_RECTS(dstRegion);
		1681	nbox = REGION_NUM_RECTS(dstRegion);
		1682	while (nbox--) {
		1683	BoxRec r;
		1684
		1685	r.x1 = box->x1 + pix_xoff;
		1686	r.x2 = box->x2 + pix_xoff;
		1687	r.y1 = box->y1 + pix_yoff;
		1688	r.y2 = box->y2 + pix_yoff;
		1689
		1690	gen6_get_rectangles(sna, &tmp, 1, gen6_emit_video_state);
		1691
		1692	OUT_VERTEX(r.x2, r.y2);
		1693	OUT_VERTEX_F(box->x2 * src_scale_x + src_offset_x);
		1694	OUT_VERTEX_F(box->y2 * src_scale_y + src_offset_y);
		1695
		1696	OUT_VERTEX(r.x1, r.y2);
		1697	OUT_VERTEX_F(box->x1 * src_scale_x + src_offset_x);
		1698	OUT_VERTEX_F(box->y2 * src_scale_y + src_offset_y);
		1699
		1700	OUT_VERTEX(r.x1, r.y1);
		1701	OUT_VERTEX_F(box->x1 * src_scale_x + src_offset_x);
		1702	OUT_VERTEX_F(box->y1 * src_scale_y + src_offset_y);
		1703
		1704	if (!DAMAGE_IS_ALL(priv->gpu_damage)) {
		1705	sna_damage_add_box(&priv->gpu_damage, &r);
		1706	sna_damage_subtract_box(&priv->cpu_damage, &r);
		1707	}
		1708	box++;
		1709	}
		1710
		1711	gen4_vertex_flush(sna);
		1712	return true;
		1713	}
		1714
		1715	static int
		1716	gen6_composite_picture(struct sna *sna,
		1717	PicturePtr picture,
		1718	struct sna_composite_channel *channel,
		1719	int x, int y,
		1720	int w, int h,
		1721	int dst_x, int dst_y,
		1722	bool precise)
		1723	{
		1724	PixmapPtr pixmap;
		1725	uint32_t color;
		1726	int16_t dx, dy;
		1727
		1728	DBG(("%s: (%d, %d)x(%d, %d), dst=(%d, %d)\n",
		1729	__FUNCTION__, x, y, w, h, dst_x, dst_y));
		1730
		1731	channel->is_solid = false;
		1732	channel->card_format = -1;
		1733
		1734	if (sna_picture_is_solid(picture, &color))
		1735	return gen4_channel_init_solid(sna, channel, color);
		1736
		1737	if (picture->pDrawable == NULL) {
		1738	int ret;
		1739
		1740	if (picture->pSourcePict->type == SourcePictTypeLinear)
		1741	return gen4_channel_init_linear(sna, picture, channel,
		1742	x, y,
		1743	w, h,
		1744	dst_x, dst_y);
		1745
		1746	DBG(("%s -- fixup, gradient\n", __FUNCTION__));
		1747	ret = -1;
		1748	if (!precise)
		1749	ret = sna_render_picture_approximate_gradient(sna, picture, channel,
		1750	x, y, w, h, dst_x, dst_y);
		1751	if (ret == -1)
		1752	ret = sna_render_picture_fixup(sna, picture, channel,
		1753	x, y, w, h, dst_x, dst_y);
		1754	return ret;
		1755	}
		1756
		1757	if (picture->alphaMap) {
		1758	DBG(("%s -- fixup, alphamap\n", __FUNCTION__));
		1759	return sna_render_picture_fixup(sna, picture, channel,
		1760	x, y, w, h, dst_x, dst_y);
		1761	}
		1762
		1763	if (!gen6_check_repeat(picture))
		1764	return sna_render_picture_fixup(sna, picture, channel,
		1765	x, y, w, h, dst_x, dst_y);
		1766
		1767	if (!gen6_check_filter(picture))
		1768	return sna_render_picture_fixup(sna, picture, channel,
		1769	x, y, w, h, dst_x, dst_y);
		1770
		1771	channel->repeat = picture->repeat ? picture->repeatType : RepeatNone;
		1772	channel->filter = picture->filter;
		1773
		1774	pixmap = get_drawable_pixmap(picture->pDrawable);
		1775	get_drawable_deltas(picture->pDrawable, pixmap, &dx, &dy);
		1776
		1777	x += dx + picture->pDrawable->x;
		1778	y += dy + picture->pDrawable->y;
		1779
		1780	channel->is_affine = sna_transform_is_affine(picture->transform);
		1781	if (sna_transform_is_integer_translation(picture->transform, &dx, &dy)) {
		1782	DBG(("%s: integer translation (%d, %d), removing\n",
		1783	__FUNCTION__, dx, dy));
		1784	x += dx;
		1785	y += dy;
		1786	channel->transform = NULL;
		1787	channel->filter = PictFilterNearest;
		1788	} else
		1789	channel->transform = picture->transform;
		1790
		1791	channel->pict_format = picture->format;
		1792	channel->card_format = gen6_get_card_format(picture->format);
		1793	if (channel->card_format == (unsigned)-1)
		1794	return sna_render_picture_convert(sna, picture, channel, pixmap,
		1795	x, y, w, h, dst_x, dst_y,
		1796	false);
		1797
		1798	if (too_large(pixmap->drawable.width, pixmap->drawable.height)) {
		1799	DBG(("%s: extracting from pixmap %dx%d\n", __FUNCTION__,
		1800	pixmap->drawable.width, pixmap->drawable.height));
		1801	return sna_render_picture_extract(sna, picture, channel,
		1802	x, y, w, h, dst_x, dst_y);
		1803	}
		1804
		1805	return sna_render_pixmap_bo(sna, channel, pixmap,
		1806	x, y, w, h, dst_x, dst_y);
		1807	}
		1808
		1809	inline static void gen6_composite_channel_convert(struct sna_composite_channel *channel)
		1810	{
		1811	channel->repeat = gen6_repeat(channel->repeat);
		1812	channel->filter = gen6_filter(channel->filter);
		1813	if (channel->card_format == (unsigned)-1)
		1814	channel->card_format = gen6_get_card_format(channel->pict_format);
		1815	assert(channel->card_format != (unsigned)-1);
		1816	}
		1817	#endif
		1818
		1819	static void gen6_render_composite_done(struct sna *sna,
		1820	const struct sna_composite_op *op)
		1821	{
		1822	DBG(("%s\n", __FUNCTION__));
		1823
		1824	assert(!sna->render.active);
		1825	if (sna->render.vertex_offset) {
		1826	gen4_vertex_flush(sna);
		1827	gen6_magic_ca_pass(sna, op);
		1828	}
		1829
		1830
		1831	}
		1832
		1833	#if 0
		1834	static bool
		1835	gen6_composite_set_target(struct sna *sna,
		1836	struct sna_composite_op *op,
		1837	PicturePtr dst,
		1838	int x, int y, int w, int h,
		1839	bool partial)
		1840	{
		1841	BoxRec box;
		1842
		1843	op->dst.pixmap = get_drawable_pixmap(dst->pDrawable);
		1844	op->dst.format = dst->format;
		1845	op->dst.width = op->dst.pixmap->drawable.width;
		1846	op->dst.height = op->dst.pixmap->drawable.height;
		1847
		1848	if (w && h) {
		1849	box.x1 = x;
		1850	box.y1 = y;
		1851	box.x2 = x + w;
		1852	box.y2 = y + h;
		1853	} else
		1854	sna_render_picture_extents(dst, &box);
		1855
4501	Serge	1856	op->dst.bo = sna_drawable_use_bo(dst->pDrawable,
		1857	PREFER_GPU \| FORCE_GPU \| RENDER_GPU,
		1858	&box, &op->damage);
4304	Serge	1859	if (op->dst.bo == NULL)
		1860	return false;
		1861
		1862	get_drawable_deltas(dst->pDrawable, op->dst.pixmap,
		1863	&op->dst.x, &op->dst.y);
		1864
		1865	DBG(("%s: pixmap=%p, format=%08x, size=%dx%d, pitch=%d, delta=(%d,%d),damage=%p\n",
		1866	__FUNCTION__,
		1867	op->dst.pixmap, (int)op->dst.format,
		1868	op->dst.width, op->dst.height,
		1869	op->dst.bo->pitch,
		1870	op->dst.x, op->dst.y,
		1871	op->damage ? op->damage : (void )-1));
		1872
		1873	assert(op->dst.bo->proxy == NULL);
		1874
		1875	if (too_large(op->dst.width, op->dst.height) &&
		1876	!sna_render_composite_redirect(sna, op, x, y, w, h))
		1877	return false;
		1878
		1879	return true;
		1880	}
		1881
		1882	static bool
		1883	prefer_blt_composite(struct sna sna, struct sna_composite_op tmp)
		1884	{
		1885	if (untiled_tlb_miss(tmp->dst.bo) \|\|
		1886	untiled_tlb_miss(tmp->src.bo))
		1887	return true;
		1888
		1889	if (kgem_bo_is_render(tmp->dst.bo) \|\|
		1890	kgem_bo_is_render(tmp->src.bo))
		1891	return false;
		1892
		1893	if (!prefer_blt_ring(sna, tmp->dst.bo, 0))
		1894	return false;
		1895
		1896	return prefer_blt_bo(sna, tmp->dst.bo) \|\| prefer_blt_bo(sna, tmp->src.bo);
		1897	}
		1898
		1899	static bool
		1900	gen6_render_composite(struct sna *sna,
		1901	uint8_t op,
		1902	PicturePtr src,
		1903	PicturePtr mask,
		1904	PicturePtr dst,
		1905	int16_t src_x, int16_t src_y,
		1906	int16_t msk_x, int16_t msk_y,
		1907	int16_t dst_x, int16_t dst_y,
		1908	int16_t width, int16_t height,
		1909	struct sna_composite_op *tmp)
		1910	{
		1911	if (op >= ARRAY_SIZE(gen6_blend_op))
		1912	return false;
		1913
		1914	DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__,
		1915	width, height, sna->kgem.ring));
		1916
		1917	if (mask == NULL &&
		1918	try_blt(sna, dst, src, width, height) &&
		1919	sna_blt_composite(sna, op,
		1920	src, dst,
		1921	src_x, src_y,
		1922	dst_x, dst_y,
		1923	width, height,
		1924	tmp, false))
		1925	return true;
		1926
		1927	if (gen6_composite_fallback(sna, src, mask, dst))
4501	Serge	1928	return (mask == NULL &&
		1929	sna_blt_composite(sna, op,
		1930	src, dst,
		1931	src_x, src_y,
		1932	dst_x, dst_y,
		1933	width, height,
		1934	tmp, true));
4304	Serge	1935
		1936	if (need_tiling(sna, width, height))
		1937	return sna_tiling_composite(op, src, mask, dst,
		1938	src_x, src_y,
		1939	msk_x, msk_y,
		1940	dst_x, dst_y,
		1941	width, height,
		1942	tmp);
		1943
		1944	if (op == PictOpClear)
		1945	op = PictOpSrc;
		1946	tmp->op = op;
		1947	if (!gen6_composite_set_target(sna, tmp, dst,
		1948	dst_x, dst_y, width, height,
		1949	op > PictOpSrc \|\| dst->pCompositeClip->data))
		1950	return false;
		1951
		1952	switch (gen6_composite_picture(sna, src, &tmp->src,
		1953	src_x, src_y,
		1954	width, height,
		1955	dst_x, dst_y,
		1956	dst->polyMode == PolyModePrecise)) {
		1957	case -1:
		1958	goto cleanup_dst;
		1959	case 0:
		1960	if (!gen4_channel_init_solid(sna, &tmp->src, 0))
		1961	goto cleanup_dst;
		1962	/* fall through to fixup */
		1963	case 1:
		1964	/* Did we just switch rings to prepare the source? */
		1965	if (mask == NULL &&
		1966	prefer_blt_composite(sna, tmp) &&
		1967	sna_blt_composite__convert(sna,
		1968	dst_x, dst_y, width, height,
		1969	tmp))
		1970	return true;
		1971
		1972	gen6_composite_channel_convert(&tmp->src);
		1973	break;
		1974	}
		1975
		1976	tmp->is_affine = tmp->src.is_affine;
		1977	tmp->has_component_alpha = false;
		1978	tmp->need_magic_ca_pass = false;
		1979
		1980	tmp->mask.bo = NULL;
		1981	tmp->mask.filter = SAMPLER_FILTER_NEAREST;
		1982	tmp->mask.repeat = SAMPLER_EXTEND_NONE;
		1983
		1984	if (mask) {
		1985	if (mask->componentAlpha && PICT_FORMAT_RGB(mask->format)) {
		1986	tmp->has_component_alpha = true;
		1987
		1988	/* Check if it's component alpha that relies on a source alpha and on
		1989	* the source value. We can only get one of those into the single
		1990	* source value that we get to blend with.
		1991	*/
		1992	if (gen6_blend_op[op].src_alpha &&
		1993	(gen6_blend_op[op].src_blend != GEN6_BLENDFACTOR_ZERO)) {
		1994	if (op != PictOpOver)
		1995	goto cleanup_src;
		1996
		1997	tmp->need_magic_ca_pass = true;
		1998	tmp->op = PictOpOutReverse;
		1999	}
		2000	}
		2001
		2002	if (!reuse_source(sna,
		2003	src, &tmp->src, src_x, src_y,
		2004	mask, &tmp->mask, msk_x, msk_y)) {
		2005	switch (gen6_composite_picture(sna, mask, &tmp->mask,
		2006	msk_x, msk_y,
		2007	width, height,
		2008	dst_x, dst_y,
		2009	dst->polyMode == PolyModePrecise)) {
		2010	case -1:
		2011	goto cleanup_src;
		2012	case 0:
		2013	if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
		2014	goto cleanup_src;
		2015	/* fall through to fixup */
		2016	case 1:
		2017	gen6_composite_channel_convert(&tmp->mask);
		2018	break;
		2019	}
		2020	}
		2021
		2022	tmp->is_affine &= tmp->mask.is_affine;
		2023	}
		2024
		2025	tmp->u.gen6.flags =
		2026	GEN6_SET_FLAGS(SAMPLER_OFFSET(tmp->src.filter,
		2027	tmp->src.repeat,
		2028	tmp->mask.filter,
		2029	tmp->mask.repeat),
		2030	gen6_get_blend(tmp->op,
		2031	tmp->has_component_alpha,
		2032	tmp->dst.format),
		2033	gen6_choose_composite_kernel(tmp->op,
		2034	tmp->mask.bo != NULL,
		2035	tmp->has_component_alpha,
		2036	tmp->is_affine),
		2037	gen4_choose_composite_emitter(sna, tmp));
		2038
		2039	tmp->blt = gen6_render_composite_blt;
		2040	tmp->box = gen6_render_composite_box;
		2041	tmp->boxes = gen6_render_composite_boxes__blt;
		2042	if (tmp->emit_boxes) {
		2043	tmp->boxes = gen6_render_composite_boxes;
		2044	tmp->thread_boxes = gen6_render_composite_boxes__thread;
		2045	}
		2046	tmp->done = gen6_render_composite_done;
		2047
		2048	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->dst.bo);
		2049	if (!kgem_check_bo(&sna->kgem,
		2050	tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
		2051	NULL)) {
		2052	kgem_submit(&sna->kgem);
		2053	if (!kgem_check_bo(&sna->kgem,
		2054	tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
		2055	NULL))
		2056	goto cleanup_mask;
		2057	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2058	}
		2059
4501	Serge	2060	gen6_align_vertex(sna, tmp);
4304	Serge	2061	gen6_emit_composite_state(sna, tmp);
		2062	return true;
		2063
		2064	cleanup_mask:
		2065	if (tmp->mask.bo)
		2066	kgem_bo_destroy(&sna->kgem, tmp->mask.bo);
		2067	cleanup_src:
		2068	if (tmp->src.bo)
		2069	kgem_bo_destroy(&sna->kgem, tmp->src.bo);
		2070	cleanup_dst:
		2071	if (tmp->redirect.real_bo)
		2072	kgem_bo_destroy(&sna->kgem, tmp->dst.bo);
		2073	return false;
		2074	}
		2075
		2076	#if !NO_COMPOSITE_SPANS
		2077	fastcall static void
		2078	gen6_render_composite_spans_box(struct sna *sna,
		2079	const struct sna_composite_spans_op *op,
		2080	const BoxRec *box, float opacity)
		2081	{
		2082	DBG(("%s: src=+(%d, %d), opacity=%f, dst=+(%d, %d), box=(%d, %d) x (%d, %d)\n",
		2083	__FUNCTION__,
		2084	op->base.src.offset[0], op->base.src.offset[1],
		2085	opacity,
		2086	op->base.dst.x, op->base.dst.y,
		2087	box->x1, box->y1,
		2088	box->x2 - box->x1,
		2089	box->y2 - box->y1));
		2090
		2091	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_composite_state);
		2092	op->prim_emit(sna, op, box, opacity);
		2093	}
		2094
		2095	static void
		2096	gen6_render_composite_spans_boxes(struct sna *sna,
		2097	const struct sna_composite_spans_op *op,
		2098	const BoxRec *box, int nbox,
		2099	float opacity)
		2100	{
		2101	DBG(("%s: nbox=%d, src=+(%d, %d), opacity=%f, dst=+(%d, %d)\n",
		2102	__FUNCTION__, nbox,
		2103	op->base.src.offset[0], op->base.src.offset[1],
		2104	opacity,
		2105	op->base.dst.x, op->base.dst.y));
		2106
		2107	do {
		2108	int nbox_this_time;
		2109
		2110	nbox_this_time = gen6_get_rectangles(sna, &op->base, nbox,
		2111	gen6_emit_composite_state);
		2112	nbox -= nbox_this_time;
		2113
		2114	do {
		2115	DBG((" %s: (%d, %d) x (%d, %d)\n", __FUNCTION__,
		2116	box->x1, box->y1,
		2117	box->x2 - box->x1,
		2118	box->y2 - box->y1));
		2119
		2120	op->prim_emit(sna, op, box++, opacity);
		2121	} while (--nbox_this_time);
		2122	} while (nbox);
		2123	}
		2124
		2125	fastcall static void
		2126	gen6_render_composite_spans_boxes__thread(struct sna *sna,
		2127	const struct sna_composite_spans_op *op,
		2128	const struct sna_opacity_box *box,
		2129	int nbox)
		2130	{
		2131	DBG(("%s: nbox=%d, src=+(%d, %d), dst=+(%d, %d)\n",
		2132	__FUNCTION__, nbox,
		2133	op->base.src.offset[0], op->base.src.offset[1],
		2134	op->base.dst.x, op->base.dst.y));
		2135
		2136	sna_vertex_lock(&sna->render);
		2137	do {
		2138	int nbox_this_time;
		2139	float *v;
		2140
		2141	nbox_this_time = gen6_get_rectangles(sna, &op->base, nbox,
		2142	gen6_emit_composite_state);
		2143	assert(nbox_this_time);
		2144	nbox -= nbox_this_time;
		2145
		2146	v = sna->render.vertices + sna->render.vertex_used;
		2147	sna->render.vertex_used += nbox_this_time * op->base.floats_per_rect;
		2148
		2149	sna_vertex_acquire__locked(&sna->render);
		2150	sna_vertex_unlock(&sna->render);
		2151
		2152	op->emit_boxes(op, box, nbox_this_time, v);
		2153	box += nbox_this_time;
		2154
		2155	sna_vertex_lock(&sna->render);
		2156	sna_vertex_release__locked(&sna->render);
		2157	} while (nbox);
		2158	sna_vertex_unlock(&sna->render);
		2159	}
		2160
		2161	fastcall static void
		2162	gen6_render_composite_spans_done(struct sna *sna,
		2163	const struct sna_composite_spans_op *op)
		2164	{
		2165	DBG(("%s()\n", __FUNCTION__));
		2166	assert(!sna->render.active);
		2167
		2168	if (sna->render.vertex_offset)
		2169	gen4_vertex_flush(sna);
		2170
		2171	if (op->base.src.bo)
		2172	kgem_bo_destroy(&sna->kgem, op->base.src.bo);
		2173
		2174	sna_render_composite_redirect_done(sna, &op->base);
		2175	}
		2176
		2177	static bool
		2178	gen6_check_composite_spans(struct sna *sna,
		2179	uint8_t op, PicturePtr src, PicturePtr dst,
		2180	int16_t width, int16_t height,
		2181	unsigned flags)
		2182	{
		2183	DBG(("%s: op=%d, width=%d, height=%d, flags=%x\n",
		2184	__FUNCTION__, op, width, height, flags));
		2185
		2186	if (op >= ARRAY_SIZE(gen6_blend_op))
		2187	return false;
		2188
		2189	if (gen6_composite_fallback(sna, src, NULL, dst)) {
		2190	DBG(("%s: operation would fallback\n", __FUNCTION__));
		2191	return false;
		2192	}
		2193
		2194	if (need_tiling(sna, width, height) &&
		2195	!is_gpu(sna, dst->pDrawable, PREFER_GPU_SPANS)) {
		2196	DBG(("%s: fallback, tiled operation not on GPU\n",
		2197	__FUNCTION__));
		2198	return false;
		2199	}
		2200
		2201	if ((flags & COMPOSITE_SPANS_RECTILINEAR) == 0) {
		2202	struct sna_pixmap *priv = sna_pixmap_from_drawable(dst->pDrawable);
		2203	assert(priv);
		2204
		2205	if (priv->cpu_bo && kgem_bo_is_busy(priv->cpu_bo))
		2206	return true;
		2207
		2208	if (flags & COMPOSITE_SPANS_INPLACE_HINT)
		2209	return false;
		2210
		2211	return priv->gpu_bo && kgem_bo_is_busy(priv->gpu_bo);
		2212	}
		2213
		2214	return true;
		2215	}
		2216
		2217	static bool
		2218	gen6_render_composite_spans(struct sna *sna,
		2219	uint8_t op,
		2220	PicturePtr src,
		2221	PicturePtr dst,
		2222	int16_t src_x, int16_t src_y,
		2223	int16_t dst_x, int16_t dst_y,
		2224	int16_t width, int16_t height,
		2225	unsigned flags,
		2226	struct sna_composite_spans_op *tmp)
		2227	{
		2228	DBG(("%s: %dx%d with flags=%x, current mode=%d\n", __FUNCTION__,
		2229	width, height, flags, sna->kgem.ring));
		2230
		2231	assert(gen6_check_composite_spans(sna, op, src, dst, width, height, flags));
		2232
		2233	if (need_tiling(sna, width, height)) {
		2234	DBG(("%s: tiling, operation (%dx%d) too wide for pipeline\n",
		2235	__FUNCTION__, width, height));
		2236	return sna_tiling_composite_spans(op, src, dst,
		2237	src_x, src_y, dst_x, dst_y,
		2238	width, height, flags, tmp);
		2239	}
		2240
		2241	tmp->base.op = op;
		2242	if (!gen6_composite_set_target(sna, &tmp->base, dst,
		2243	dst_x, dst_y, width, height, true))
		2244	return false;
		2245
		2246	switch (gen6_composite_picture(sna, src, &tmp->base.src,
		2247	src_x, src_y,
		2248	width, height,
		2249	dst_x, dst_y,
		2250	dst->polyMode == PolyModePrecise)) {
		2251	case -1:
		2252	goto cleanup_dst;
		2253	case 0:
		2254	if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
		2255	goto cleanup_dst;
		2256	/* fall through to fixup */
		2257	case 1:
		2258	gen6_composite_channel_convert(&tmp->base.src);
		2259	break;
		2260	}
		2261	tmp->base.mask.bo = NULL;
		2262
		2263	tmp->base.is_affine = tmp->base.src.is_affine;
		2264	tmp->base.need_magic_ca_pass = false;
		2265
		2266	tmp->base.u.gen6.flags =
		2267	GEN6_SET_FLAGS(SAMPLER_OFFSET(tmp->base.src.filter,
		2268	tmp->base.src.repeat,
		2269	SAMPLER_FILTER_NEAREST,
		2270	SAMPLER_EXTEND_PAD),
		2271	gen6_get_blend(tmp->base.op, false, tmp->base.dst.format),
		2272	GEN6_WM_KERNEL_OPACITY \| !tmp->base.is_affine,
		2273	gen4_choose_spans_emitter(sna, tmp));
		2274
		2275	tmp->box = gen6_render_composite_spans_box;
		2276	tmp->boxes = gen6_render_composite_spans_boxes;
		2277	if (tmp->emit_boxes)
		2278	tmp->thread_boxes = gen6_render_composite_spans_boxes__thread;
		2279	tmp->done = gen6_render_composite_spans_done;
		2280
		2281	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->base.dst.bo);
		2282	if (!kgem_check_bo(&sna->kgem,
		2283	tmp->base.dst.bo, tmp->base.src.bo,
		2284	NULL)) {
		2285	kgem_submit(&sna->kgem);
		2286	if (!kgem_check_bo(&sna->kgem,
		2287	tmp->base.dst.bo, tmp->base.src.bo,
		2288	NULL))
		2289	goto cleanup_src;
		2290	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2291	}
		2292
4501	Serge	2293	gen6_align_vertex(sna, &tmp->base);
4304	Serge	2294	gen6_emit_composite_state(sna, &tmp->base);
		2295	return true;
		2296
		2297	cleanup_src:
		2298	if (tmp->base.src.bo)
		2299	kgem_bo_destroy(&sna->kgem, tmp->base.src.bo);
		2300	cleanup_dst:
		2301	if (tmp->base.redirect.real_bo)
		2302	kgem_bo_destroy(&sna->kgem, tmp->base.dst.bo);
		2303	return false;
		2304	}
		2305	#endif
		2306
		2307	static void
		2308	gen6_emit_copy_state(struct sna *sna,
		2309	const struct sna_composite_op *op)
		2310	{
		2311	uint32_t *binding_table;
		2312	uint16_t offset;
		2313	bool dirty;
		2314
		2315	dirty = gen6_get_batch(sna, op);
		2316
		2317	binding_table = gen6_composite_get_binding_table(sna, &offset);
		2318
		2319	binding_table[0] =
		2320	gen6_bind_bo(sna,
		2321	op->dst.bo, op->dst.width, op->dst.height,
		2322	gen6_get_dest_format(op->dst.format),
		2323	true);
		2324	binding_table[1] =
		2325	gen6_bind_bo(sna,
		2326	op->src.bo, op->src.width, op->src.height,
		2327	op->src.card_format,
		2328	false);
		2329
		2330	if (sna->kgem.surface == offset &&
		2331	(uint64_t )(sna->kgem.batch + sna->render_state.gen6.surface_table) == (uint64_t)binding_table) {
		2332	sna->kgem.surface += sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		2333	offset = sna->render_state.gen6.surface_table;
		2334	}
		2335
		2336	gen6_emit_state(sna, op, offset \| dirty);
		2337	}
		2338
		2339	static inline bool prefer_blt_copy(struct sna *sna,
		2340	struct kgem_bo *src_bo,
		2341	struct kgem_bo *dst_bo,
		2342	unsigned flags)
		2343	{
		2344	if (flags & COPY_SYNC)
		2345	return false;
		2346
		2347	if (PREFER_RENDER)
		2348	return PREFER_RENDER > 0;
		2349
		2350	if (sna->kgem.ring == KGEM_BLT)
		2351	return true;
		2352
		2353	if (src_bo == dst_bo && can_switch_to_blt(sna, dst_bo, flags))
		2354	return true;
		2355
		2356	if (untiled_tlb_miss(src_bo) \|\|
		2357	untiled_tlb_miss(dst_bo))
		2358	return true;
		2359
4501	Serge	2360	if (force_blt_ring(sna))
		2361	return true;
		2362
4304	Serge	2363	if (kgem_bo_is_render(dst_bo) \|\|
		2364	kgem_bo_is_render(src_bo))
		2365	return false;
		2366
4501	Serge	2367	if (prefer_render_ring(sna, dst_bo))
		2368	return false;
		2369
4304	Serge	2370	if (!prefer_blt_ring(sna, dst_bo, flags))
		2371	return false;
		2372
		2373	return prefer_blt_bo(sna, src_bo) \|\| prefer_blt_bo(sna, dst_bo);
		2374	}
		2375
		2376	inline static void boxes_extents(const BoxRec box, int n, BoxRec extents)
		2377	{
		2378	*extents = box[0];
		2379	while (--n) {
		2380	box++;
		2381
		2382	if (box->x1 < extents->x1)
		2383	extents->x1 = box->x1;
		2384	if (box->x2 > extents->x2)
		2385	extents->x2 = box->x2;
		2386
		2387	if (box->y1 < extents->y1)
		2388	extents->y1 = box->y1;
		2389	if (box->y2 > extents->y2)
		2390	extents->y2 = box->y2;
		2391	}
		2392	}
		2393
		2394	static inline bool
		2395	overlaps(struct sna *sna,
		2396	struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
		2397	struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy,
		2398	const BoxRec box, int n, BoxRec extents)
		2399	{
		2400	if (src_bo != dst_bo)
		2401	return false;
		2402
		2403	boxes_extents(box, n, extents);
		2404	return (extents->x2 + src_dx > extents->x1 + dst_dx &&
		2405	extents->x1 + src_dx < extents->x2 + dst_dx &&
		2406	extents->y2 + src_dy > extents->y1 + dst_dy &&
		2407	extents->y1 + src_dy < extents->y2 + dst_dy);
		2408	}
		2409
		2410	static bool
		2411	gen6_render_copy_boxes(struct sna *sna, uint8_t alu,
		2412	PixmapPtr src, struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
		2413	PixmapPtr dst, struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy,
		2414	const BoxRec *box, int n, unsigned flags)
		2415	{
		2416	struct sna_composite_op tmp;
		2417	BoxRec extents;
		2418
		2419	DBG(("%s (%d, %d)->(%d, %d) x %d, alu=%x, self-copy=%d, overlaps? %d\n",
		2420	__FUNCTION__, src_dx, src_dy, dst_dx, dst_dy, n, alu,
		2421	src_bo == dst_bo,
		2422	overlaps(sna,
		2423	src_bo, src_dx, src_dy,
		2424	dst_bo, dst_dx, dst_dy,
		2425	box, n, &extents)));
		2426
		2427	if (prefer_blt_copy(sna, src_bo, dst_bo, flags) &&
		2428	sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2429	sna_blt_copy_boxes(sna, alu,
		2430	src_bo, src_dx, src_dy,
		2431	dst_bo, dst_dx, dst_dy,
		2432	dst->drawable.bitsPerPixel,
		2433	box, n))
		2434	return true;
		2435
		2436	if (!(alu == GXcopy \|\| alu == GXclear)) {
		2437	fallback_blt:
		2438	if (!sna_blt_compare_depth(&src->drawable, &dst->drawable))
		2439	return false;
		2440
		2441	return sna_blt_copy_boxes_fallback(sna, alu,
		2442	src, src_bo, src_dx, src_dy,
		2443	dst, dst_bo, dst_dx, dst_dy,
		2444	box, n);
		2445	}
		2446
		2447	if (overlaps(sna,
		2448	src_bo, src_dx, src_dy,
		2449	dst_bo, dst_dx, dst_dy,
		2450	box, n, &extents)) {
		2451	if (too_large(extents.x2-extents.x1, extents.y2-extents.y1))
		2452	goto fallback_blt;
		2453
		2454	if (can_switch_to_blt(sna, dst_bo, flags) &&
		2455	sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2456	sna_blt_copy_boxes(sna, alu,
		2457	src_bo, src_dx, src_dy,
		2458	dst_bo, dst_dx, dst_dy,
		2459	dst->drawable.bitsPerPixel,
		2460	box, n))
		2461	return true;
		2462
		2463	return sna_render_copy_boxes__overlap(sna, alu,
		2464	src, src_bo, src_dx, src_dy,
		2465	dst, dst_bo, dst_dx, dst_dy,
		2466	box, n, &extents);
		2467	}
		2468
		2469	if (dst->drawable.depth == src->drawable.depth) {
		2470	tmp.dst.format = sna_render_format_for_depth(dst->drawable.depth);
		2471	tmp.src.pict_format = tmp.dst.format;
		2472	} else {
		2473	tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
		2474	tmp.src.pict_format = sna_format_for_depth(src->drawable.depth);
		2475	}
		2476	if (!gen6_check_format(tmp.src.pict_format))
		2477	goto fallback_blt;
		2478
		2479	tmp.dst.pixmap = dst;
		2480	tmp.dst.width = dst->drawable.width;
		2481	tmp.dst.height = dst->drawable.height;
		2482	tmp.dst.bo = dst_bo;
		2483	tmp.dst.x = tmp.dst.y = 0;
		2484	tmp.damage = NULL;
		2485
		2486	sna_render_composite_redirect_init(&tmp);
		2487	if (too_large(tmp.dst.width, tmp.dst.height)) {
		2488	int i;
		2489
		2490	extents = box[0];
		2491	for (i = 1; i < n; i++) {
		2492	if (box[i].x1 < extents.x1)
		2493	extents.x1 = box[i].x1;
		2494	if (box[i].y1 < extents.y1)
		2495	extents.y1 = box[i].y1;
		2496
		2497	if (box[i].x2 > extents.x2)
		2498	extents.x2 = box[i].x2;
		2499	if (box[i].y2 > extents.y2)
		2500	extents.y2 = box[i].y2;
		2501	}
		2502
		2503	if (!sna_render_composite_redirect(sna, &tmp,
		2504	extents.x1 + dst_dx,
		2505	extents.y1 + dst_dy,
		2506	extents.x2 - extents.x1,
		2507	extents.y2 - extents.y1,
		2508	n > 1))
		2509	goto fallback_tiled;
		2510
		2511	dst_dx += tmp.dst.x;
		2512	dst_dy += tmp.dst.y;
		2513
		2514	tmp.dst.x = tmp.dst.y = 0;
		2515	}
		2516
		2517	tmp.src.card_format = gen6_get_card_format(tmp.src.pict_format);
		2518	if (too_large(src->drawable.width, src->drawable.height)) {
		2519	int i;
		2520
		2521	extents = box[0];
		2522	for (i = 1; i < n; i++) {
		2523	if (box[i].x1 < extents.x1)
		2524	extents.x1 = box[i].x1;
		2525	if (box[i].y1 < extents.y1)
		2526	extents.y1 = box[i].y1;
		2527
		2528	if (box[i].x2 > extents.x2)
		2529	extents.x2 = box[i].x2;
		2530	if (box[i].y2 > extents.y2)
		2531	extents.y2 = box[i].y2;
		2532	}
		2533
		2534	if (!sna_render_pixmap_partial(sna, src, src_bo, &tmp.src,
		2535	extents.x1 + src_dx,
		2536	extents.y1 + src_dy,
		2537	extents.x2 - extents.x1,
		2538	extents.y2 - extents.y1)) {
		2539	DBG(("%s: unable to extract partial pixmap\n", __FUNCTION__));
		2540	goto fallback_tiled_dst;
		2541	}
		2542
		2543	src_dx += tmp.src.offset[0];
		2544	src_dy += tmp.src.offset[1];
		2545	} else {
		2546	tmp.src.bo = src_bo;
		2547	tmp.src.width = src->drawable.width;
		2548	tmp.src.height = src->drawable.height;
		2549	}
		2550
		2551	tmp.mask.bo = NULL;
		2552
		2553	tmp.floats_per_vertex = 2;
		2554	tmp.floats_per_rect = 6;
		2555	tmp.need_magic_ca_pass = 0;
		2556
		2557	tmp.u.gen6.flags = COPY_FLAGS(alu);
		2558	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		2559	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == COPY_SAMPLER);
		2560	assert(GEN6_VERTEX(tmp.u.gen6.flags) == COPY_VERTEX);
		2561
		2562	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp.dst.bo);
		2563	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, tmp.src.bo, NULL)) {
		2564	kgem_submit(&sna->kgem);
		2565	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, tmp.src.bo, NULL)) {
		2566	DBG(("%s: too large for a single operation\n",
		2567	__FUNCTION__));
4501	Serge	2568	if (tmp.src.bo != src_bo)
		2569	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		2570	if (tmp.redirect.real_bo)
		2571	kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
		2572	goto fallback_blt;
4304	Serge	2573	}
		2574	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2575	}
		2576
4501	Serge	2577	gen6_align_vertex(sna, &tmp);
4304	Serge	2578	gen6_emit_copy_state(sna, &tmp);
		2579
		2580	do {
		2581	int16_t *v;
		2582	int n_this_time;
		2583
		2584	n_this_time = gen6_get_rectangles(sna, &tmp, n,
		2585	gen6_emit_copy_state);
		2586	n -= n_this_time;
		2587
		2588	v = (int16_t *)(sna->render.vertices + sna->render.vertex_used);
		2589	sna->render.vertex_used += 6 * n_this_time;
		2590	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2591	do {
		2592
		2593	DBG((" (%d, %d) -> (%d, %d) + (%d, %d)\n",
		2594	box->x1 + src_dx, box->y1 + src_dy,
		2595	box->x1 + dst_dx, box->y1 + dst_dy,
		2596	box->x2 - box->x1, box->y2 - box->y1));
		2597	v[0] = box->x2 + dst_dx;
		2598	v[2] = box->x2 + src_dx;
		2599	v[1] = v[5] = box->y2 + dst_dy;
		2600	v[3] = v[7] = box->y2 + src_dy;
		2601	v[8] = v[4] = box->x1 + dst_dx;
		2602	v[10] = v[6] = box->x1 + src_dx;
		2603	v[9] = box->y1 + dst_dy;
		2604	v[11] = box->y1 + src_dy;
		2605	v += 12; box++;
		2606	} while (--n_this_time);
		2607	} while (n);
		2608
		2609	gen4_vertex_flush(sna);
		2610	sna_render_composite_redirect_done(sna, &tmp);
		2611	if (tmp.src.bo != src_bo)
		2612	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		2613	return true;
		2614
		2615	fallback_tiled_dst:
		2616	if (tmp.redirect.real_bo)
		2617	kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
		2618	fallback_tiled:
		2619	if (sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2620	sna_blt_copy_boxes(sna, alu,
		2621	src_bo, src_dx, src_dy,
		2622	dst_bo, dst_dx, dst_dy,
		2623	dst->drawable.bitsPerPixel,
		2624	box, n))
		2625	return true;
		2626
		2627	return sna_tiling_copy_boxes(sna, alu,
		2628	src, src_bo, src_dx, src_dy,
		2629	dst, dst_bo, dst_dx, dst_dy,
		2630	box, n);
		2631	}
		2632
		2633	static void
		2634	gen6_render_copy_blt(struct sna *sna,
		2635	const struct sna_copy_op *op,
		2636	int16_t sx, int16_t sy,
		2637	int16_t w, int16_t h,
		2638	int16_t dx, int16_t dy)
		2639	{
		2640	int16_t *v;
		2641
		2642	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_copy_state);
		2643
		2644	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		2645	sna->render.vertex_used += 6;
		2646	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2647
		2648	v[0] = dx+w; v[1] = dy+h;
		2649	v[2] = sx+w; v[3] = sy+h;
		2650	v[4] = dx; v[5] = dy+h;
		2651	v[6] = sx; v[7] = sy+h;
		2652	v[8] = dx; v[9] = dy;
		2653	v[10] = sx; v[11] = sy;
		2654	}
		2655
		2656	static void
		2657	gen6_render_copy_done(struct sna sna, const struct sna_copy_op op)
		2658	{
		2659	DBG(("%s()\n", __FUNCTION__));
		2660
		2661	assert(!sna->render.active);
		2662	if (sna->render.vertex_offset)
		2663	gen4_vertex_flush(sna);
		2664	}
		2665
		2666	static bool
		2667	gen6_render_copy(struct sna *sna, uint8_t alu,
		2668	PixmapPtr src, struct kgem_bo *src_bo,
		2669	PixmapPtr dst, struct kgem_bo *dst_bo,
		2670	struct sna_copy_op *op)
		2671	{
		2672	DBG(("%s (alu=%d, src=(%dx%d), dst=(%dx%d))\n",
		2673	__FUNCTION__, alu,
		2674	src->drawable.width, src->drawable.height,
		2675	dst->drawable.width, dst->drawable.height));
		2676
		2677	if (prefer_blt_copy(sna, src_bo, dst_bo, 0) &&
		2678	sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2679	sna_blt_copy(sna, alu,
		2680	src_bo, dst_bo,
		2681	dst->drawable.bitsPerPixel,
		2682	op))
		2683	return true;
		2684
		2685	if (!(alu == GXcopy \|\| alu == GXclear) \|\| src_bo == dst_bo \|\|
		2686	too_large(src->drawable.width, src->drawable.height) \|\|
		2687	too_large(dst->drawable.width, dst->drawable.height)) {
		2688	fallback:
		2689	if (!sna_blt_compare_depth(&src->drawable, &dst->drawable))
		2690	return false;
		2691
		2692	return sna_blt_copy(sna, alu, src_bo, dst_bo,
		2693	dst->drawable.bitsPerPixel,
		2694	op);
		2695	}
		2696
		2697	if (dst->drawable.depth == src->drawable.depth) {
		2698	op->base.dst.format = sna_render_format_for_depth(dst->drawable.depth);
		2699	op->base.src.pict_format = op->base.dst.format;
		2700	} else {
		2701	op->base.dst.format = sna_format_for_depth(dst->drawable.depth);
		2702	op->base.src.pict_format = sna_format_for_depth(src->drawable.depth);
		2703	}
		2704	if (!gen6_check_format(op->base.src.pict_format))
		2705	goto fallback;
		2706
		2707	op->base.dst.pixmap = dst;
		2708	op->base.dst.width = dst->drawable.width;
		2709	op->base.dst.height = dst->drawable.height;
		2710	op->base.dst.bo = dst_bo;
		2711
		2712	op->base.src.bo = src_bo;
		2713	op->base.src.card_format =
		2714	gen6_get_card_format(op->base.src.pict_format);
		2715	op->base.src.width = src->drawable.width;
		2716	op->base.src.height = src->drawable.height;
		2717
		2718	op->base.mask.bo = NULL;
		2719
		2720	op->base.floats_per_vertex = 2;
		2721	op->base.floats_per_rect = 6;
		2722
		2723	op->base.u.gen6.flags = COPY_FLAGS(alu);
		2724	assert(GEN6_KERNEL(op->base.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		2725	assert(GEN6_SAMPLER(op->base.u.gen6.flags) == COPY_SAMPLER);
		2726	assert(GEN6_VERTEX(op->base.u.gen6.flags) == COPY_VERTEX);
		2727
		2728	kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
		2729	if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
		2730	kgem_submit(&sna->kgem);
		2731	if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL))
		2732	goto fallback;
		2733	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2734	}
		2735
4501	Serge	2736	gen6_align_vertex(sna, &op->base);
4304	Serge	2737	gen6_emit_copy_state(sna, &op->base);
		2738
		2739	op->blt = gen6_render_copy_blt;
		2740	op->done = gen6_render_copy_done;
		2741	return true;
		2742	}
		2743
		2744	static void
		2745	gen6_emit_fill_state(struct sna sna, const struct sna_composite_op op)
		2746	{
		2747	uint32_t *binding_table;
		2748	uint16_t offset;
		2749	bool dirty;
		2750
		2751	dirty = gen6_get_batch(sna, op);
		2752
		2753	binding_table = gen6_composite_get_binding_table(sna, &offset);
		2754
		2755	binding_table[0] =
		2756	gen6_bind_bo(sna,
		2757	op->dst.bo, op->dst.width, op->dst.height,
		2758	gen6_get_dest_format(op->dst.format),
		2759	true);
		2760	binding_table[1] =
		2761	gen6_bind_bo(sna,
		2762	op->src.bo, 1, 1,
		2763	GEN6_SURFACEFORMAT_B8G8R8A8_UNORM,
		2764	false);
		2765
		2766	if (sna->kgem.surface == offset &&
		2767	(uint64_t )(sna->kgem.batch + sna->render_state.gen6.surface_table) == (uint64_t)binding_table) {
		2768	sna->kgem.surface +=
		2769	sizeof(struct gen6_surface_state_padded)/sizeof(uint32_t);
		2770	offset = sna->render_state.gen6.surface_table;
		2771	}
		2772
		2773	gen6_emit_state(sna, op, offset \| dirty);
		2774	}
		2775
		2776	static bool
		2777	gen6_render_fill_boxes(struct sna *sna,
		2778	CARD8 op,
		2779	PictFormat format,
		2780	const xRenderColor *color,
		2781	PixmapPtr dst, struct kgem_bo *dst_bo,
		2782	const BoxRec *box, int n)
		2783	{
		2784	struct sna_composite_op tmp;
		2785	uint32_t pixel;
		2786
		2787	DBG(("%s (op=%d, color=(%04x, %04x, %04x, %04x) [%08x])\n",
		2788	__FUNCTION__, op,
		2789	color->red, color->green, color->blue, color->alpha, (int)format));
		2790
		2791	if (op >= ARRAY_SIZE(gen6_blend_op)) {
		2792	DBG(("%s: fallback due to unhandled blend op: %d\n",
		2793	__FUNCTION__, op));
		2794	return false;
		2795	}
		2796
4501	Serge	2797	if (prefer_blt_fill(sna, dst_bo, FILL_BOXES) \|\|
		2798	!gen6_check_dst_format(format)) {
4304	Serge	2799	uint8_t alu = GXinvalid;
		2800
		2801	if (op <= PictOpSrc) {
		2802	pixel = 0;
		2803	if (op == PictOpClear)
		2804	alu = GXclear;
		2805	else if (sna_get_pixel_from_rgba(&pixel,
		2806	color->red,
		2807	color->green,
		2808	color->blue,
		2809	color->alpha,
		2810	format))
		2811	alu = GXcopy;
		2812	}
		2813
		2814	if (alu != GXinvalid &&
		2815	sna_blt_fill_boxes(sna, alu,
		2816	dst_bo, dst->drawable.bitsPerPixel,
		2817	pixel, box, n))
		2818	return true;
		2819
		2820	if (!gen6_check_dst_format(format))
		2821	return false;
		2822	}
		2823
		2824	if (op == PictOpClear) {
		2825	pixel = 0;
		2826	op = PictOpSrc;
		2827	} else if (!sna_get_pixel_from_rgba(&pixel,
		2828	color->red,
		2829	color->green,
		2830	color->blue,
		2831	color->alpha,
		2832	PICT_a8r8g8b8))
		2833	return false;
		2834
		2835	DBG(("%s(%08x x %d [(%d, %d), (%d, %d) ...])\n",
		2836	__FUNCTION__, pixel, n,
		2837	box[0].x1, box[0].y1, box[0].x2, box[0].y2));
		2838
		2839	tmp.dst.pixmap = dst;
		2840	tmp.dst.width = dst->drawable.width;
		2841	tmp.dst.height = dst->drawable.height;
		2842	tmp.dst.format = format;
		2843	tmp.dst.bo = dst_bo;
		2844	tmp.dst.x = tmp.dst.y = 0;
		2845	tmp.damage = NULL;
		2846
		2847	sna_render_composite_redirect_init(&tmp);
		2848	if (too_large(dst->drawable.width, dst->drawable.height)) {
		2849	BoxRec extents;
		2850
		2851	boxes_extents(box, n, &extents);
		2852	if (!sna_render_composite_redirect(sna, &tmp,
		2853	extents.x1, extents.y1,
		2854	extents.x2 - extents.x1,
		2855	extents.y2 - extents.y1,
		2856	n > 1))
		2857	return sna_tiling_fill_boxes(sna, op, format, color,
		2858	dst, dst_bo, box, n);
		2859	}
		2860
		2861	tmp.src.bo = sna_render_get_solid(sna, pixel);
		2862	tmp.mask.bo = NULL;
		2863
		2864	tmp.floats_per_vertex = 2;
		2865	tmp.floats_per_rect = 6;
		2866	tmp.need_magic_ca_pass = false;
		2867
		2868	tmp.u.gen6.flags = FILL_FLAGS(op, format);
		2869	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		2870	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == FILL_SAMPLER);
		2871	assert(GEN6_VERTEX(tmp.u.gen6.flags) == FILL_VERTEX);
		2872
4501	Serge	2873	kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
4304	Serge	2874	if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
		2875	kgem_submit(&sna->kgem);
		2876	assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
		2877	}
		2878
4501	Serge	2879	gen6_align_vertex(sna, &tmp);
4304	Serge	2880	gen6_emit_fill_state(sna, &tmp);
		2881
		2882	do {
		2883	int n_this_time;
		2884	int16_t *v;
		2885
		2886	n_this_time = gen6_get_rectangles(sna, &tmp, n,
		2887	gen6_emit_fill_state);
		2888	n -= n_this_time;
		2889
		2890	v = (int16_t *)(sna->render.vertices + sna->render.vertex_used);
		2891	sna->render.vertex_used += 6 * n_this_time;
		2892	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2893	do {
		2894	DBG((" (%d, %d), (%d, %d)\n",
		2895	box->x1, box->y1, box->x2, box->y2));
		2896
		2897	v[0] = box->x2;
		2898	v[5] = v[1] = box->y2;
		2899	v[8] = v[4] = box->x1;
		2900	v[9] = box->y1;
		2901	v[2] = v[3] = v[7] = 1;
		2902	v[6] = v[10] = v[11] = 0;
		2903	v += 12; box++;
		2904	} while (--n_this_time);
		2905	} while (n);
		2906
		2907	gen4_vertex_flush(sna);
		2908	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		2909	sna_render_composite_redirect_done(sna, &tmp);
		2910	return true;
		2911	}
		2912
		2913	static void
		2914	gen6_render_op_fill_blt(struct sna *sna,
		2915	const struct sna_fill_op *op,
		2916	int16_t x, int16_t y, int16_t w, int16_t h)
		2917	{
		2918	int16_t *v;
		2919
		2920	DBG(("%s: (%d, %d)x(%d, %d)\n", __FUNCTION__, x, y, w, h));
		2921
		2922	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_fill_state);
		2923
		2924	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		2925	sna->render.vertex_used += 6;
		2926	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2927
		2928	v[0] = x+w;
		2929	v[4] = v[8] = x;
		2930	v[1] = v[5] = y+h;
		2931	v[9] = y;
		2932
		2933	v[2] = v[3] = v[7] = 1;
		2934	v[6] = v[10] = v[11] = 0;
		2935	}
		2936
		2937	fastcall static void
		2938	gen6_render_op_fill_box(struct sna *sna,
		2939	const struct sna_fill_op *op,
		2940	const BoxRec *box)
		2941	{
		2942	int16_t *v;
		2943
		2944	DBG(("%s: (%d, %d),(%d, %d)\n", __FUNCTION__,
		2945	box->x1, box->y1, box->x2, box->y2));
		2946
		2947	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_fill_state);
		2948
		2949	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		2950	sna->render.vertex_used += 6;
		2951	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2952
		2953	v[0] = box->x2;
		2954	v[8] = v[4] = box->x1;
		2955	v[5] = v[1] = box->y2;
		2956	v[9] = box->y1;
		2957
		2958	v[7] = v[2] = v[3] = 1;
		2959	v[6] = v[10] = v[11] = 0;
		2960	}
		2961
		2962	fastcall static void
		2963	gen6_render_op_fill_boxes(struct sna *sna,
		2964	const struct sna_fill_op *op,
		2965	const BoxRec *box,
		2966	int nbox)
		2967	{
		2968	DBG(("%s: (%d, %d),(%d, %d)... x %d\n", __FUNCTION__,
		2969	box->x1, box->y1, box->x2, box->y2, nbox));
		2970
		2971	do {
		2972	int nbox_this_time;
		2973	int16_t *v;
		2974
		2975	nbox_this_time = gen6_get_rectangles(sna, &op->base, nbox,
		2976	gen6_emit_fill_state);
		2977	nbox -= nbox_this_time;
		2978
		2979	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		2980	sna->render.vertex_used += 6 * nbox_this_time;
		2981	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2982
		2983	do {
		2984	v[0] = box->x2;
		2985	v[8] = v[4] = box->x1;
		2986	v[5] = v[1] = box->y2;
		2987	v[9] = box->y1;
		2988	v[7] = v[2] = v[3] = 1;
		2989	v[6] = v[10] = v[11] = 0;
		2990	box++; v += 12;
		2991	} while (--nbox_this_time);
		2992	} while (nbox);
		2993	}
		2994
		2995	static void
		2996	gen6_render_op_fill_done(struct sna sna, const struct sna_fill_op op)
		2997	{
		2998	DBG(("%s()\n", __FUNCTION__));
		2999
		3000	assert(!sna->render.active);
		3001	if (sna->render.vertex_offset)
		3002	gen4_vertex_flush(sna);
		3003	kgem_bo_destroy(&sna->kgem, op->base.src.bo);
		3004	}
		3005
		3006	static bool
		3007	gen6_render_fill(struct sna *sna, uint8_t alu,
		3008	PixmapPtr dst, struct kgem_bo *dst_bo,
4501	Serge	3009	uint32_t color, unsigned flags,
4304	Serge	3010	struct sna_fill_op *op)
		3011	{
		3012	DBG(("%s: (alu=%d, color=%x)\n", __FUNCTION__, alu, color));
		3013
4501	Serge	3014	if (prefer_blt_fill(sna, dst_bo, flags) &&
4304	Serge	3015	sna_blt_fill(sna, alu,
		3016	dst_bo, dst->drawable.bitsPerPixel,
		3017	color,
		3018	op))
		3019	return true;
		3020
		3021	if (!(alu == GXcopy \|\| alu == GXclear) \|\|
		3022	too_large(dst->drawable.width, dst->drawable.height))
		3023	return sna_blt_fill(sna, alu,
		3024	dst_bo, dst->drawable.bitsPerPixel,
		3025	color,
		3026	op);
		3027
		3028	if (alu == GXclear)
		3029	color = 0;
		3030
		3031	op->base.dst.pixmap = dst;
		3032	op->base.dst.width = dst->drawable.width;
		3033	op->base.dst.height = dst->drawable.height;
		3034	op->base.dst.format = sna_format_for_depth(dst->drawable.depth);
		3035	op->base.dst.bo = dst_bo;
		3036	op->base.dst.x = op->base.dst.y = 0;
		3037
		3038	op->base.src.bo =
		3039	sna_render_get_solid(sna,
		3040	sna_rgba_for_color(color,
		3041	dst->drawable.depth));
		3042	op->base.mask.bo = NULL;
		3043
		3044	op->base.need_magic_ca_pass = false;
		3045	op->base.floats_per_vertex = 2;
		3046	op->base.floats_per_rect = 6;
		3047
		3048	op->base.u.gen6.flags = FILL_FLAGS_NOBLEND;
		3049	assert(GEN6_KERNEL(op->base.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		3050	assert(GEN6_SAMPLER(op->base.u.gen6.flags) == FILL_SAMPLER);
		3051	assert(GEN6_VERTEX(op->base.u.gen6.flags) == FILL_VERTEX);
		3052
4501	Serge	3053	kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
4304	Serge	3054	if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
		3055	kgem_submit(&sna->kgem);
		3056	assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
		3057	}
		3058
4501	Serge	3059	gen6_align_vertex(sna, &op->base);
4304	Serge	3060	gen6_emit_fill_state(sna, &op->base);
		3061
		3062	op->blt = gen6_render_op_fill_blt;
		3063	op->box = gen6_render_op_fill_box;
		3064	op->boxes = gen6_render_op_fill_boxes;
		3065	op->done = gen6_render_op_fill_done;
		3066	return true;
		3067	}
		3068
		3069	static bool
		3070	gen6_render_fill_one_try_blt(struct sna sna, PixmapPtr dst, struct kgem_bo bo,
		3071	uint32_t color,
		3072	int16_t x1, int16_t y1, int16_t x2, int16_t y2,
		3073	uint8_t alu)
		3074	{
		3075	BoxRec box;
		3076
		3077	box.x1 = x1;
		3078	box.y1 = y1;
		3079	box.x2 = x2;
		3080	box.y2 = y2;
		3081
		3082	return sna_blt_fill_boxes(sna, alu,
		3083	bo, dst->drawable.bitsPerPixel,
		3084	color, &box, 1);
		3085	}
		3086
		3087	static bool
		3088	gen6_render_fill_one(struct sna sna, PixmapPtr dst, struct kgem_bo bo,
		3089	uint32_t color,
		3090	int16_t x1, int16_t y1,
		3091	int16_t x2, int16_t y2,
		3092	uint8_t alu)
		3093	{
		3094	struct sna_composite_op tmp;
		3095	int16_t *v;
		3096
		3097	/* Prefer to use the BLT if already engaged */
4501	Serge	3098	if (prefer_blt_fill(sna, bo, FILL_BOXES) &&
4304	Serge	3099	gen6_render_fill_one_try_blt(sna, dst, bo, color,
		3100	x1, y1, x2, y2, alu))
		3101	return true;
		3102
		3103	/* Must use the BLT if we can't RENDER... */
		3104	if (!(alu == GXcopy \|\| alu == GXclear) \|\|
		3105	too_large(dst->drawable.width, dst->drawable.height))
		3106	return gen6_render_fill_one_try_blt(sna, dst, bo, color,
		3107	x1, y1, x2, y2, alu);
		3108
		3109	if (alu == GXclear)
		3110	color = 0;
		3111
		3112	tmp.dst.pixmap = dst;
		3113	tmp.dst.width = dst->drawable.width;
		3114	tmp.dst.height = dst->drawable.height;
		3115	tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
		3116	tmp.dst.bo = bo;
		3117	tmp.dst.x = tmp.dst.y = 0;
		3118
		3119	tmp.src.bo =
		3120	sna_render_get_solid(sna,
		3121	sna_rgba_for_color(color,
		3122	dst->drawable.depth));
		3123	tmp.mask.bo = NULL;
		3124
		3125	tmp.floats_per_vertex = 2;
		3126	tmp.floats_per_rect = 6;
		3127	tmp.need_magic_ca_pass = false;
		3128
		3129	tmp.u.gen6.flags = FILL_FLAGS_NOBLEND;
		3130	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		3131	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == FILL_SAMPLER);
		3132	assert(GEN6_VERTEX(tmp.u.gen6.flags) == FILL_VERTEX);
		3133
4501	Serge	3134	kgem_set_mode(&sna->kgem, KGEM_RENDER, bo);
4304	Serge	3135	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3136	kgem_submit(&sna->kgem);
		3137	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3138	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3139	return false;
		3140	}
		3141	}
		3142
4501	Serge	3143	gen6_align_vertex(sna, &tmp);
4304	Serge	3144	gen6_emit_fill_state(sna, &tmp);
		3145
		3146	gen6_get_rectangles(sna, &tmp, 1, gen6_emit_fill_state);
		3147
		3148	DBG((" (%d, %d), (%d, %d)\n", x1, y1, x2, y2));
		3149
		3150	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		3151	sna->render.vertex_used += 6;
		3152	assert(sna->render.vertex_used <= sna->render.vertex_size);
		3153
		3154	v[0] = x2;
		3155	v[8] = v[4] = x1;
		3156	v[5] = v[1] = y2;
		3157	v[9] = y1;
		3158	v[7] = v[2] = v[3] = 1;
		3159	v[6] = v[10] = v[11] = 0;
		3160
		3161	gen4_vertex_flush(sna);
		3162	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3163
		3164	return true;
		3165	}
		3166
		3167	static bool
		3168	gen6_render_clear_try_blt(struct sna sna, PixmapPtr dst, struct kgem_bo bo)
		3169	{
		3170	BoxRec box;
		3171
		3172	box.x1 = 0;
		3173	box.y1 = 0;
		3174	box.x2 = dst->drawable.width;
		3175	box.y2 = dst->drawable.height;
		3176
		3177	return sna_blt_fill_boxes(sna, GXclear,
		3178	bo, dst->drawable.bitsPerPixel,
		3179	0, &box, 1);
		3180	}
		3181
		3182	static bool
		3183	gen6_render_clear(struct sna sna, PixmapPtr dst, struct kgem_bo bo)
		3184	{
		3185	struct sna_composite_op tmp;
		3186	int16_t *v;
		3187
		3188	DBG(("%s: %dx%d\n",
		3189	__FUNCTION__,
		3190	dst->drawable.width,
		3191	dst->drawable.height));
		3192
		3193	/* Prefer to use the BLT if, and only if, already engaged */
		3194	if (sna->kgem.ring == KGEM_BLT &&
		3195	gen6_render_clear_try_blt(sna, dst, bo))
		3196	return true;
		3197
		3198	/* Must use the BLT if we can't RENDER... */
		3199	if (too_large(dst->drawable.width, dst->drawable.height))
		3200	return gen6_render_clear_try_blt(sna, dst, bo);
		3201
		3202	tmp.dst.pixmap = dst;
		3203	tmp.dst.width = dst->drawable.width;
		3204	tmp.dst.height = dst->drawable.height;
		3205	tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
		3206	tmp.dst.bo = bo;
		3207	tmp.dst.x = tmp.dst.y = 0;
		3208
		3209	tmp.src.bo = sna_render_get_solid(sna, 0);
		3210	tmp.mask.bo = NULL;
		3211
		3212	tmp.floats_per_vertex = 2;
		3213	tmp.floats_per_rect = 6;
		3214	tmp.need_magic_ca_pass = false;
		3215
		3216	tmp.u.gen6.flags = FILL_FLAGS_NOBLEND;
		3217	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		3218	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == FILL_SAMPLER);
		3219	assert(GEN6_VERTEX(tmp.u.gen6.flags) == FILL_VERTEX);
		3220
4501	Serge	3221	kgem_set_mode(&sna->kgem, KGEM_RENDER, bo);
4304	Serge	3222	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3223	kgem_submit(&sna->kgem);
		3224	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3225	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3226	return false;
		3227	}
		3228	}
		3229
4501	Serge	3230	gen6_align_vertex(sna, &tmp);
4304	Serge	3231	gen6_emit_fill_state(sna, &tmp);
		3232
		3233	gen6_get_rectangles(sna, &tmp, 1, gen6_emit_fill_state);
		3234
		3235	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		3236	sna->render.vertex_used += 6;
		3237	assert(sna->render.vertex_used <= sna->render.vertex_size);
		3238
		3239	v[0] = dst->drawable.width;
		3240	v[5] = v[1] = dst->drawable.height;
		3241	v[8] = v[4] = 0;
		3242	v[9] = 0;
		3243
		3244	v[7] = v[2] = v[3] = 1;
		3245	v[6] = v[10] = v[11] = 0;
		3246
		3247	gen4_vertex_flush(sna);
		3248	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3249
		3250	return true;
		3251	}
		3252	#endif
		3253
		3254	static void gen6_render_reset(struct sna *sna)
		3255	{
		3256	sna->render_state.gen6.needs_invariant = true;
		3257	sna->render_state.gen6.first_state_packet = true;
		3258	sna->render_state.gen6.ve_id = 3 << 2;
		3259	sna->render_state.gen6.last_primitive = -1;
		3260
		3261	sna->render_state.gen6.num_sf_outputs = 0;
		3262	sna->render_state.gen6.samplers = -1;
		3263	sna->render_state.gen6.blend = -1;
		3264	sna->render_state.gen6.kernel = -1;
		3265	sna->render_state.gen6.drawrect_offset = -1;
		3266	sna->render_state.gen6.drawrect_limit = -1;
		3267	sna->render_state.gen6.surface_table = -1;
		3268
4501	Serge	3269	if (sna->render.vbo && !kgem_bo_can_map(&sna->kgem, sna->render.vbo)) {
		3270	DBG(("%s: discarding unmappable vbo\n", __FUNCTION__));
		3271	discard_vbo(sna);
		3272	}
		3273
4304	Serge	3274	sna->render.vertex_offset = 0;
		3275	sna->render.nvertex_reloc = 0;
		3276	sna->render.vb_id = 0;
		3277	}
		3278
		3279	static void gen6_render_fini(struct sna *sna)
		3280	{
		3281	kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo);
		3282	}
		3283
4501	Serge	3284	static bool is_gt2(struct sna *sna, int devid)
4304	Serge	3285	{
4501	Serge	3286	return devid & 0x30;
4304	Serge	3287	}
		3288
4501	Serge	3289	static bool is_mobile(struct sna *sna, int devid)
4304	Serge	3290	{
4501	Serge	3291	return (devid & 0xf) == 0x6;
4304	Serge	3292	}
		3293
4501	Serge	3294	static bool gen6_render_setup(struct sna *sna, int devid)
4304	Serge	3295	{
		3296	struct gen6_render_state *state = &sna->render_state.gen6;
		3297	struct sna_static_stream general;
		3298	struct gen6_sampler_state *ss;
		3299	int i, j, k, l, m;
		3300
		3301	state->info = >1_info;
4501	Serge	3302	if (is_gt2(sna, devid))
4304	Serge	3303	state->info = >2_info; /* XXX requires GT_MODE WiZ disabled */
4501	Serge	3304	state->gt = state->info->gt;
4304	Serge	3305
		3306	sna_static_stream_init(&general);
		3307
		3308	/* Zero pad the start. If you see an offset of 0x0 in the batchbuffer
		3309	* dumps, you know it points to zero.
		3310	*/
		3311	null_create(&general);
		3312	scratch_create(&general);
		3313
		3314	for (m = 0; m < GEN6_KERNEL_COUNT; m++) {
		3315	if (wm_kernels[m].size) {
		3316	state->wm_kernel[m][1] =
		3317	sna_static_stream_add(&general,
		3318	wm_kernels[m].data,
		3319	wm_kernels[m].size,
		3320	64);
		3321	} else {
		3322	if (USE_8_PIXEL_DISPATCH) {
		3323	state->wm_kernel[m][0] =
		3324	sna_static_stream_compile_wm(sna, &general,
		3325	wm_kernels[m].data, 8);
		3326	}
		3327
		3328	if (USE_16_PIXEL_DISPATCH) {
		3329	state->wm_kernel[m][1] =
		3330	sna_static_stream_compile_wm(sna, &general,
		3331	wm_kernels[m].data, 16);
		3332	}
		3333
		3334	if (USE_32_PIXEL_DISPATCH) {
		3335	state->wm_kernel[m][2] =
		3336	sna_static_stream_compile_wm(sna, &general,
		3337	wm_kernels[m].data, 32);
		3338	}
		3339	}
		3340	if ((state->wm_kernel[m][0]\|state->wm_kernel[m][1]\|state->wm_kernel[m][2]) == 0) {
		3341	state->wm_kernel[m][1] =
		3342	sna_static_stream_compile_wm(sna, &general,
		3343	wm_kernels[m].data, 16);
		3344	}
		3345	}
		3346
		3347	ss = sna_static_stream_map(&general,
		3348	2 * sizeof(ss)
		3349	(2 +
		3350	FILTER_COUNT * EXTEND_COUNT *
		3351	FILTER_COUNT * EXTEND_COUNT),
		3352	32);
		3353	state->wm_state = sna_static_stream_offsetof(&general, ss);
		3354	sampler_copy_init(ss); ss += 2;
		3355	sampler_fill_init(ss); ss += 2;
		3356	for (i = 0; i < FILTER_COUNT; i++) {
		3357	for (j = 0; j < EXTEND_COUNT; j++) {
		3358	for (k = 0; k < FILTER_COUNT; k++) {
		3359	for (l = 0; l < EXTEND_COUNT; l++) {
		3360	sampler_state_init(ss++, i, j);
		3361	sampler_state_init(ss++, k, l);
		3362	}
		3363	}
		3364	}
		3365	}
		3366
		3367	state->cc_blend = gen6_composite_create_blend_state(&general);
		3368
		3369	state->general_bo = sna_static_stream_fini(sna, &general);
		3370	return state->general_bo != NULL;
		3371	}
		3372
		3373	const char gen6_render_init(struct sna sna, const char *backend)
		3374	{
4501	Serge	3375	int devid = intel_get_device_id(sna);
		3376
		3377	if (!gen6_render_setup(sna, devid))
4304	Serge	3378	return backend;
		3379
		3380	sna->kgem.context_switch = gen6_render_context_switch;
		3381	sna->kgem.retire = gen6_render_retire;
4501	Serge	3382	sna->kgem.expire = gen4_render_expire;
4304	Serge	3383
		3384	#if 0
		3385	#if !NO_COMPOSITE
		3386	sna->render.composite = gen6_render_composite;
		3387	sna->render.prefer_gpu \|= PREFER_GPU_RENDER;
		3388	#endif
		3389
		3390	#if !NO_COMPOSITE_SPANS
		3391	sna->render.check_composite_spans = gen6_check_composite_spans;
		3392	sna->render.composite_spans = gen6_render_composite_spans;
4501	Serge	3393	if (is_mobile(sna, devid))
4304	Serge	3394	sna->render.prefer_gpu \|= PREFER_GPU_SPANS;
		3395	#endif
		3396	sna->render.video = gen6_render_video;
		3397
		3398	#if !NO_COPY_BOXES
		3399	sna->render.copy_boxes = gen6_render_copy_boxes;
		3400	#endif
		3401	#if !NO_COPY
		3402	sna->render.copy = gen6_render_copy;
		3403	#endif
		3404
		3405	#if !NO_FILL_BOXES
		3406	sna->render.fill_boxes = gen6_render_fill_boxes;
		3407	#endif
		3408	#if !NO_FILL
		3409	sna->render.fill = gen6_render_fill;
		3410	#endif
		3411	#if !NO_FILL_ONE
		3412	sna->render.fill_one = gen6_render_fill_one;
		3413	#endif
		3414	#if !NO_FILL_CLEAR
		3415	sna->render.clear = gen6_render_clear;
		3416	#endif
		3417	#endif
		3418
		3419	sna->render.caps = HW_BIT_BLIT \| HW_TEX_BLIT;
		3420	sna->render.blit_tex = gen6_blit_tex;
		3421
4501	Serge	3422	sna->render.flush = gen4_render_flush;
4304	Serge	3423	sna->render.reset = gen6_render_reset;
		3424	sna->render.fini = gen6_render_fini;
		3425
		3426	sna->render.max_3d_size = GEN6_MAX_SIZE;
		3427	sna->render.max_3d_pitch = 1 << 18;
		3428	return sna->render_state.gen6.info->name;
		3429	}
		3430
		3431	static bool
		3432	gen6_blit_tex(struct sna *sna,
		3433	uint8_t op, bool scale,
		3434	PixmapPtr src, struct kgem_bo *src_bo,
		3435	PixmapPtr mask,struct kgem_bo *mask_bo,
		3436	PixmapPtr dst, struct kgem_bo *dst_bo,
		3437	int32_t src_x, int32_t src_y,
		3438	int32_t msk_x, int32_t msk_y,
		3439	int32_t dst_x, int32_t dst_y,
		3440	int32_t width, int32_t height,
		3441	struct sna_composite_op *tmp)
		3442	{
		3443
		3444	DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__,
		3445	width, height, sna->kgem.ring));
		3446
		3447	tmp->op = PictOpSrc;
		3448
		3449	tmp->dst.pixmap = dst;
		3450	tmp->dst.bo = dst_bo;
		3451	tmp->dst.width = dst->drawable.width;
		3452	tmp->dst.height = dst->drawable.height;
		3453	tmp->dst.format = PICT_a8r8g8b8;
		3454
		3455
		3456	tmp->src.repeat = SAMPLER_EXTEND_NONE;
		3457	tmp->src.is_affine = true;
		3458
		3459	tmp->src.bo = src_bo;
		3460	tmp->src.pict_format = PICT_x8r8g8b8;
		3461	tmp->src.card_format = gen6_get_card_format(tmp->src.pict_format);
		3462	tmp->src.width = src->drawable.width;
		3463	tmp->src.height = src->drawable.height;
		3464
		3465	if ( (tmp->src.width == width) &&
		3466	(tmp->src.height == height) )
		3467	tmp->src.filter = SAMPLER_FILTER_NEAREST;
		3468	else
		3469	tmp->src.filter = SAMPLER_FILTER_BILINEAR;
		3470
		3471	tmp->is_affine = tmp->src.is_affine;
		3472	tmp->has_component_alpha = false;
		3473	tmp->need_magic_ca_pass = false;
		3474
		3475	tmp->mask.repeat = SAMPLER_EXTEND_NONE;
		3476	tmp->mask.filter = SAMPLER_FILTER_NEAREST;
		3477	tmp->mask.is_affine = true;
		3478
		3479	tmp->mask.bo = mask_bo;
		3480	tmp->mask.pict_format = PIXMAN_a8;
		3481	tmp->mask.card_format = gen6_get_card_format(tmp->mask.pict_format);
		3482	tmp->mask.width = mask->drawable.width;
		3483	tmp->mask.height = mask->drawable.height;
		3484
		3485
		3486	if( scale )
		3487	{
		3488	tmp->src.scale[0] = 1.f/width;
		3489	tmp->src.scale[1] = 1.f/height;
		3490	}
		3491	else
		3492	{
		3493	tmp->src.scale[0] = 1.f/src->drawable.width;
		3494	tmp->src.scale[1] = 1.f/src->drawable.height;
		3495	}
		3496	// tmp->src.offset[0] = -dst_x;
		3497	// tmp->src.offset[1] = -dst_y;
		3498
		3499
		3500	tmp->mask.scale[0] = 1.f/mask->drawable.width;
		3501	tmp->mask.scale[1] = 1.f/mask->drawable.height;
		3502	// tmp->mask.offset[0] = -dst_x;
		3503	// tmp->mask.offset[1] = -dst_y;
		3504
		3505	tmp->u.gen6.flags =
		3506	GEN6_SET_FLAGS(SAMPLER_OFFSET(tmp->src.filter,
		3507	tmp->src.repeat,
		3508	tmp->mask.filter,
		3509	tmp->mask.repeat),
		3510	gen6_get_blend(tmp->op,
		3511	tmp->has_component_alpha,
		3512	tmp->dst.format),
		3513	/* gen6_choose_composite_kernel(tmp->op,
		3514	tmp->mask.bo != NULL,
		3515	tmp->has_component_alpha,
		3516	tmp->is_affine),
		3517	*/
		3518	GEN6_WM_KERNEL_MASK,
		3519	gen4_choose_composite_emitter(sna, tmp));
		3520
		3521	tmp->blt = gen6_render_composite_blt;
		3522	// tmp->box = gen6_render_composite_box;
		3523	tmp->done = gen6_render_composite_done;
		3524
4501	Serge	3525	kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
4304	Serge	3526	if (!kgem_check_bo(&sna->kgem,
		3527	tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
		3528	NULL)) {
		3529	kgem_submit(&sna->kgem);
		3530	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		3531	}
		3532
4501	Serge	3533	gen6_align_vertex(sna, tmp);
4304	Serge	3534	gen6_emit_composite_state(sna, tmp);
4501	Serge	3535
4304	Serge	3536	return true;
		3537	}

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(root)/contrib/sdk/sources/Intel-2D/sna/gen6_render.c – Rev 4501