Rev 881 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 808 | serge | 1 | |
| 881 | serge | 2 | #include "radeon_chipset_gen.h" |
| 3 | #include "radeon_chipinfo_gen.h" |
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| 4 | |||
| 808 | serge | 5 | |
| 812 | serge | 6 | |
| 7 | |||
| 808 | serge | 8 | xf86TokenToString(SymTabPtr table, int token) |
| 9 | { |
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| 10 | int i; |
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| 11 | |||
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | return NULL; |
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| 16 | else |
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| 17 | return(table[i].name); |
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| 18 | } |
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| 19 | |||
| 20 | |||
| 881 | serge | 21 | |
| 22 | |||
| 23 | { |
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| 24 | while(list->pci_device_id) |
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| 25 | { |
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| 26 | if(dev == list->pci_device_id) |
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| 27 | return list; |
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| 28 | list++; |
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| 29 | } |
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| 30 | return 0; |
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| 31 | } |
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| 32 | |||
| 33 | |||
| 34 | |||
| 808 | serge | 35 | { |
| 36 | const RADEONCardInfo *dev; |
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| 881 | serge | 37 | u32_t bus, last_bus; |
| 877 | serge | 38 | |
| 808 | serge | 39 | |
| 40 | return 0; |
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| 41 | |||
| 42 | |||
| 43 | { |
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| 44 | u32_t devfn; |
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| 877 | serge | 45 | |
| 808 | serge | 46 | |
| 47 | { |
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| 48 | u32_t id; |
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| 877 | serge | 49 | id = PciRead32(bus,devfn, 0); |
| 808 | serge | 50 | |
| 51 | |||
| 877 | serge | 52 | continue; |
| 808 | serge | 53 | |
| 54 | |||
| 881 | serge | 55 | |
| 56 | |||
| 57 | { |
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| 808 | serge | 58 | u32_t reg2C; |
| 877 | serge | 59 | int i; |
| 808 | serge | 60 | |
| 61 | |||
| 881 | serge | 62 | if (!rhd.chipset) |
| 63 | { |
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| 64 | dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
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| 65 | return FALSE; |
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| 66 | } |
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| 67 | dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",rhd.chipset,rhd.PciDeviceID); |
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| 68 | |||
| 808 | serge | 69 | |
| 70 | rhd.devfn = devfn; |
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| 71 | rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
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| 72 | |||
| 73 | |||
| 883 | serge | 74 | rhd.IsMobility = dev->mobility; |
| 881 | serge | 75 | rhd.IsIGP = dev->igp; |
| 76 | rhd.HasCRTC2 = !dev->nocrtc2; |
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| 883 | serge | 77 | |
| 808 | serge | 78 | |
| 79 | |||
| 80 | |||
| 81 | rhd.subdevice_id = reg2C >> 16; |
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| 82 | |||
| 83 | |||
| 881 | serge | 84 | dbgprintf("R600 unsupported yet.\nExit\n"); |
| 85 | |||
| 86 | |||
| 87 | |||
| 808 | serge | 88 | { |
| 89 | u32_t base; |
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| 877 | serge | 90 | Bool validSize; |
| 808 | serge | 91 | |
| 92 | |||
| 93 | if(base) |
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| 94 | { |
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| 95 | if (base & PCI_MAP_IO) |
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| 96 | { |
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| 97 | rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
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| 877 | serge | 98 | rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
| 808 | serge | 99 | } |
| 100 | else |
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| 101 | { |
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| 102 | rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
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| 877 | serge | 103 | rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
| 808 | serge | 104 | } |
| 105 | } |
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| 106 | rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
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| 107 | } |
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| 108 | return &rhd; |
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| 109 | } |
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| 110 | }; |
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| 111 | }; |
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| 112 | return NULL; |
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| 113 | } |
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| 114 | |||
| 115 | |||
| 116 | |||
| 117 | |||
| 877 | serge | 118 | { |
| 808 | serge | 119 | int offset; |
| 120 | u32_t addr1; |
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| 877 | serge | 121 | u32_t addr2; |
| 122 | u32_t mask1; |
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| 123 | u32_t mask2; |
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| 124 | int bits = 0; |
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| 808 | serge | 125 | |
| 126 | |||
| 127 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
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| 128 | * the 6 base address registers, and 6 is the ROM base address register. |
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| 129 | */ |
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| 130 | if (index < 0 || index > 6) |
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| 131 | return 0; |
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| 132 | |||
| 133 | |||
| 134 | *min = destructive; |
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| 135 | |||
| 136 | |||
| 137 | if (index == 6) |
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| 138 | offset = PCI_MAP_ROM_REG; |
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| 139 | else |
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| 140 | offset = PCI_MAP_REG_START + (index << 2); |
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| 141 | |||
| 142 | |||
| 143 | /* |
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| 144 | * Check if this is the second part of a 64 bit address. |
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| 145 | * XXX need to check how endianness affects 64 bit addresses. |
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| 146 | */ |
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| 147 | if (index > 0 && index < 6) { |
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| 148 | addr2 = PciRead32(bus, devfn, offset - 4); |
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| 149 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
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| 150 | return 0; |
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| 151 | } |
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| 152 | |||
| 153 | |||
| 154 | PciWrite32(bus, devfn, offset, 0xffffffff); |
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| 155 | mask1 = PciRead32(bus, devfn, offset); |
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| 156 | PciWrite32(bus, devfn, offset, addr1); |
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| 157 | } else { |
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| 158 | mask1 = addr1; |
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| 159 | } |
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| 160 | |||
| 161 | |||
| 162 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
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| 163 | { |
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| 164 | if (PCIGETMEMORY(mask1) == 0) |
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| 165 | { |
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| 166 | addr2 = PciRead32(bus, devfn, offset + 4); |
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| 167 | if (destructive) |
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| 168 | { |
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| 169 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
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| 170 | mask2 = PciRead32(bus, devfn, offset + 4); |
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| 171 | PciWrite32(bus, devfn, offset + 4, addr2); |
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| 172 | } |
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| 173 | else |
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| 174 | { |
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| 175 | mask2 = addr2; |
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| 176 | } |
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| 177 | if (mask2 == 0) |
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| 178 | return 0; |
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| 179 | bits = 32; |
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| 180 | while ((mask2 & 1) == 0) |
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| 181 | { |
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| 182 | bits++; |
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| 183 | mask2 >>= 1; |
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| 184 | } |
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| 185 | if (bits > 32) |
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| 186 | return bits; |
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| 187 | } |
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| 188 | } |
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| 189 | if (index < 6) |
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| 190 | if (PCI_MAP_IS_MEM(mask1)) |
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| 191 | mask1 = PCIGETMEMORY(mask1); |
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| 192 | else |
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| 193 | mask1 = PCIGETIO(mask1); |
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| 194 | else |
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| 195 | mask1 = PCIGETROM(mask1); |
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| 196 | if (mask1 == 0) |
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| 197 | return 0; |
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| 198 | bits = 0; |
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| 199 | while ((mask1 & 1) == 0) { |
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| 200 | bits++; |
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| 201 | mask1 >>= 1; |
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| 202 | } |
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| 203 | /* I/O maps can be no larger than 8 bits */ |
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| 204 | |||
| 205 | |||
| 206 | bits = 8; |
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| 207 | /* ROM maps can be no larger than 24 bits */ |
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| 208 | if (index == 6 && bits > 24) |
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| 209 | bits = 24; |
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| 210 | return bits; |
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| 211 | } |
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| 212 | > |
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| 213 | |||
| 214 |