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Rev | Author | Line No. | Line |
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261 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; RTL8139.INC ;; |
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4 | ;; ;; |
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5 | ;; Ethernet driver for Menuet OS ;; |
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6 | ;; ;; |
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7 | ;; Version 0.2 11 August 2003 ;; |
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8 | ;; ;; |
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9 | ;; Driver for chips of RealTek 8139 family ;; |
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10 | ;; References: ;; |
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11 | ;; www.realtek.com.hw - data sheets ;; |
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12 | ;; rtl8139.c - linux driver ;; |
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13 | ;; 8139too.c - linux driver ;; |
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14 | ;; ethernet driver template by Mike Hibbett ;; |
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15 | ;; ;; |
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16 | ;; The copyright statement is ;; |
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17 | ;; ;; |
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18 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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19 | ;; Version 2, June 1991 ;; |
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20 | ;; ;; |
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21 | ;; Copyright 2003 Endre Kozma, ;; |
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22 | ;; endre.kozma@axelero.hu ;; |
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23 | ;; ;; |
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24 | ;; See file COPYING for details ;; |
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25 | ;; ;; |
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330 | heavyiron | 26 | ;; 10.01.2007 Bugfix for l8139_transmit from Paolo Franchetti ;; |
261 | hidnplayr | 27 | ;; ;; |
28 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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302 | hidnplayr | 29 | ETH_ALEN equ 6 |
30 | ETH_HLEN equ (2 * ETH_ALEN + 2) |
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31 | ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for |
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32 | ; mininmum 64bytes frame length |
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261 | hidnplayr | 33 | |
302 | hidnplayr | 34 | PCI_REG_COMMAND equ 0x04 ; command register |
35 | PCI_BIT_PIO equ 0 ; bit0: io space control |
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36 | PCI_BIT_MMIO equ 1 ; bit1: memory space control |
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37 | PCI_BIT_MASTER equ 2 ; bit2: device acts as a PCI master |
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261 | hidnplayr | 38 | |
302 | hidnplayr | 39 | RTL8139_REG_MAR0 equ 0x08 ; multicast filter register 0 |
40 | RTL8139_REG_MAR4 equ 0x0c ; multicast filter register 4 |
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41 | RTL8139_REG_TSD0 equ 0x10 ; transmit status of descriptor |
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42 | RTL8139_REG_TSAD0 equ 0x20 ; transmit start address of descriptor |
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43 | RTL8139_REG_RBSTART equ 0x30 ; RxBuffer start address |
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44 | RTL8139_REG_COMMAND equ 0x37 ; command register |
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45 | RTL8139_REG_CAPR equ 0x38 ; current address of packet read |
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46 | RTL8139_REG_IMR equ 0x3c ; interrupt mask register |
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47 | RTL8139_REG_ISR equ 0x3e ; interrupt status register |
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48 | RTL8139_REG_TXCONFIG equ 0x40 ; transmit configuration register |
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49 | RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0 |
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50 | RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1 |
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51 | RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2 |
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52 | RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3 |
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53 | RTL8139_REG_RXCONFIG equ 0x44 ; receive configuration register 0 |
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54 | RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0 |
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55 | RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1 |
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56 | RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2 |
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57 | RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3 |
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58 | RTL8139_REG_MPC equ 0x4c ; missed packet counter |
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59 | RTL8139_REG_9346CR equ 0x50 ; serial eeprom 93C46 command register |
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60 | RTL8139_REG_CONFIG1 equ 0x52 ; configuration register 1 |
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61 | RTL8139_REG_CONFIG4 equ 0x5a ; configuration register 4 |
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62 | RTL8139_REG_HLTCLK equ 0x5b ; undocumented halt clock register |
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63 | RTL8139_REG_BMCR equ 0x62 ; basic mode control register |
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64 | RTL8139_REG_ANAR equ 0x66 ; auto negotiation advertisement register |
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261 | hidnplayr | 65 | |
66 | ; 5.1 packet header |
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302 | hidnplayr | 67 | RTL8139_BIT_RUNT equ 4 ; total packet length < 64 bytes |
68 | RTL8139_BIT_LONG equ 3 ; total packet length > 4k |
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69 | RTL8139_BIT_CRC equ 2 ; crc error occured |
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70 | RTL8139_BIT_FAE equ 1 ; frame alignment error occured |
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71 | RTL8139_BIT_ROK equ 0 ; received packet is ok |
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261 | hidnplayr | 72 | ; 5.4 command register |
302 | hidnplayr | 73 | RTL8139_BIT_RST equ 4 ; reset bit |
74 | RTL8139_BIT_RE equ 3 ; receiver enabled |
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75 | RTL8139_BIT_TE equ 2 ; transmitter enabled |
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76 | RTL8139_BIT_BUFE equ 0 ; rx buffer is empty, no packet stored |
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261 | hidnplayr | 77 | ; 5.6 interrupt status register |
302 | hidnplayr | 78 | RTL8139_BIT_ISR_TOK equ 2 ; transmit ok |
79 | RTL8139_BIT_ISR_RER equ 1 ; receive error interrupt |
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80 | RTL8139_BIT_ISR_ROK equ 0 ; receive ok |
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261 | hidnplayr | 81 | ; 5.7 transmit configyration register |
302 | hidnplayr | 82 | RTL8139_BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst |
83 | RTL8139_BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16) |
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261 | hidnplayr | 84 | ; 5.8 receive configuration register |
302 | hidnplayr | 85 | RTL8139_BIT_RXFTH equ 13 ; Rx fifo threshold |
86 | RTL8139_BIT_RBLEN equ 11 ; Ring buffer length indicator |
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87 | RTL8139_BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst |
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88 | RTL8139_BIT_NOWRAP equ 7 ; transfered data wrapping |
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89 | RTL8139_BIT_9356SEL equ 6 ; eeprom selector 9346/9356 |
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90 | RTL8139_BIT_AER equ 5 ; accept error packets |
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91 | RTL8139_BIT_AR equ 4 ; accept runt packets |
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92 | RTL8139_BIT_AB equ 3 ; accept broadcast packets |
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93 | RTL8139_BIT_AM equ 2 ; accept multicast packets |
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94 | RTL8139_BIT_APM equ 1 ; accept physical match packets |
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95 | RTL8139_BIT_AAP equ 0 ; accept all packets |
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261 | hidnplayr | 96 | ; 5.9 93C46/93C56 command register |
302 | hidnplayr | 97 | RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1 |
98 | RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0 |
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99 | RTL8139_BIT_93C46_EECS equ 3 ; chip select |
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100 | RTL8139_BIT_93C46_EESK equ 2 ; serial data clock |
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101 | RTL8139_BIT_93C46_EEDI equ 1 ; serial data input |
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102 | RTL8139_BIT_93C46_EEDO equ 0 ; serial data output |
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261 | hidnplayr | 103 | ; 5.11 configuration register 1 |
302 | hidnplayr | 104 | RTL8139_BIT_LWACT equ 4 ; see RTL8139_REG_CONFIG1 |
105 | RTL8139_BIT_SLEEP equ 1 ; sleep bit at older chips |
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106 | RTL8139_BIT_PWRDWN equ 0 ; power down bit at older chips |
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107 | RTL8139_BIT_PMEn equ 0 ; power management enabled |
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261 | hidnplayr | 108 | ; 5.14 configuration register 4 |
302 | hidnplayr | 109 | RTL8139_BIT_LWPTN equ 2 ; see RTL8139_REG_CONFIG4 |
261 | hidnplayr | 110 | ; 6.2 transmit status register |
302 | hidnplayr | 111 | RTL8139_BIT_ERTXTH equ 16 ; early TX threshold |
112 | RTL8139_BIT_TOK equ 15 ; transmit ok |
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113 | RTL8139_BIT_OWN equ 13 ; tx DMA operation is completed |
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261 | hidnplayr | 114 | ; 6.18 basic mode control register |
302 | hidnplayr | 115 | RTL8139_BIT_ANE equ 12 ; auto negotiation enable |
261 | hidnplayr | 116 | ; 6.20 auto negotiation advertisement register |
302 | hidnplayr | 117 | RTL8139_BIT_TXFD equ 8 ; 100base-T full duplex |
118 | RTL8139_BIT_TX equ 7 ; 100base-T |
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119 | RTL8139_BIT_10FD equ 6 ; 10base-T full duplex |
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120 | RTL8139_BIT_10 equ 5 ; 10base-T |
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121 | RTL8139_BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001 |
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261 | hidnplayr | 122 | ; RX/TX buffer size |
302 | hidnplayr | 123 | RTL8139_RBLEN equ 0 ; 0==8K 1==16k 2==32k 3==64k |
124 | RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN) |
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125 | MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC |
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126 | RTL8139_NUM_TX_DESC equ 4 |
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127 | RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC) |
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128 | RTL8139_TXRR equ 8 ; total retries = 16+(TXRR*16) |
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129 | RTL8139_TX_MXDMA equ 6 ; 0==16 1==32 2==64 3==128 |
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130 | ; 4==256 5==512 6==1024 7==2048 |
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131 | RTL8139_ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256 |
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132 | RTL8139_RX_MXDMA equ 7 ; 0==16 1==32 2==64 3==128 |
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133 | ; 4==256 5==512 6==1024 7==unlimited |
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134 | RTL8139_RXFTH equ 7 ; 0==16 1==32 2==64 3==128 |
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135 | ; 4==256 5==512 6==1024 7==no threshold |
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136 | RTL8139_RX_CONFIG equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \ |
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137 | or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \ |
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138 | or (1 shl RTL8139_BIT_NOWRAP) \ |
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139 | or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \ |
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140 | or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \ |
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141 | or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \ |
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142 | or (1 shl RTL8139_BIT_AM)) |
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143 | RTL8139_TX_TIMEOUT equ 30 ; 300 milliseconds timeout |
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261 | hidnplayr | 144 | |
302 | hidnplayr | 145 | EE_93C46_REG_ETH_ID equ 7 ; MAC offset |
146 | EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address |
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147 | EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address |
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148 | EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address |
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149 | EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress |
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261 | hidnplayr | 150 | |
302 | hidnplayr | 151 | VER_RTL8139 equ 1100000b |
152 | VER_RTL8139A equ 1110000b |
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261 | hidnplayr | 153 | ; VER_RTL8139AG equ 1110100b |
302 | hidnplayr | 154 | VER_RTL8139B equ 1111000b |
155 | VER_RTL8130 equ VER_RTL8139B |
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156 | VER_RTL8139C equ 1110100b |
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157 | VER_RTL8100 equ 1111010b |
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158 | VER_RTL8100B equ 1110101b |
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159 | VER_RTL8139D equ VER_RTL8100B |
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160 | VER_RTL8139CP equ 1110110b |
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161 | VER_RTL8101 equ 1110111b |
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261 | hidnplayr | 162 | |
302 | hidnplayr | 163 | IDX_RTL8139 equ 0 |
164 | IDX_RTL8139A equ 1 |
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165 | IDX_RTL8139B equ 2 |
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166 | IDX_RTL8139C equ 3 |
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167 | IDX_RTL8100 equ 4 |
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168 | IDX_RTL8139D equ 5 |
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169 | IDX_RTL8139D equ 6 |
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170 | IDX_RTL8101 equ 7 |
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261 | hidnplayr | 171 | |
172 | |||
173 | ; These two must be 4 byte aligned ( which they are ) |
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174 | rtl8139_rx_buff equ eth_data_start |
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175 | rtl8139_tx_buff equ rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE) |
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176 | |||
177 | uglobal |
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302 | hidnplayr | 178 | align 4 |
261 | hidnplayr | 179 | rtl8139_rx_buff_offset: dd 0 |
180 | curr_tx_desc: dd 0 |
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181 | endg |
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182 | |||
183 | iglobal |
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184 | hw_ver_array: db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C |
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302 | hidnplayr | 185 | db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101 |
261 | hidnplayr | 186 | HW_VER_ARRAY_SIZE = $-hw_ver_array |
187 | endg |
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188 | |||
189 | uglobal |
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190 | hw_ver_id: db 0 |
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191 | endg |
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192 | |||
193 | ;*************************************************************************** |
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194 | ; Function |
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195 | ; rtl8139_probe |
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196 | ; Description |
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197 | ; Searches for an ethernet card, enables it and clears the rx buffer |
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198 | ; If a card was found, it enables the ethernet -> TCPIP link |
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199 | ; Destroyed registers |
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200 | ; eax, ebx, ecx, edx |
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201 | ; |
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202 | ;*************************************************************************** |
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203 | rtl8139_probe: |
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204 | ; enable the device |
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302 | hidnplayr | 205 | mov al, 2 |
206 | mov ah, [pci_bus] |
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207 | mov bh, [pci_dev] |
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208 | mov bl, PCI_REG_COMMAND |
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209 | call pci_read_reg |
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210 | mov cx, ax |
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211 | or cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO) |
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212 | and cl, not (1 shl PCI_BIT_MMIO) |
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213 | mov al, 2 |
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214 | mov ah, [pci_bus] |
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215 | mov bh, [pci_dev] |
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216 | mov bl, PCI_REG_COMMAND |
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217 | call pci_write_reg |
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261 | hidnplayr | 218 | ; get chip version |
302 | hidnplayr | 219 | mov edx, [io_addr] |
220 | add edx, RTL8139_REG_TXCONFIG_2 |
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221 | in ax, dx |
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222 | shr ah, 2 |
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223 | shr ax, 6 |
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224 | and al, 01111111b |
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225 | mov ecx, HW_VER_ARRAY_SIZE-1 |
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261 | hidnplayr | 226 | .chip_ver_loop: |
302 | hidnplayr | 227 | cmp al, [hw_ver_array+ecx] |
228 | je .chip_ver_found |
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229 | dec ecx |
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230 | jns .chip_ver_loop |
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231 | xor cl, cl ; default RTL8139 |
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261 | hidnplayr | 232 | .chip_ver_found: |
302 | hidnplayr | 233 | mov [hw_ver_id], cl |
261 | hidnplayr | 234 | ; wake up the chip |
302 | hidnplayr | 235 | mov edx, [io_addr] |
236 | add edx, RTL8139_REG_HLTCLK |
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237 | mov al, 'R' ; run the clock |
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238 | out dx, al |
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261 | hidnplayr | 239 | ; unlock config and BMCR registers |
302 | hidnplayr | 240 | add edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK |
241 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0) |
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242 | out dx, al |
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261 | hidnplayr | 243 | ; enable power management |
302 | hidnplayr | 244 | add edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR |
245 | in al, dx |
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246 | cmp byte [hw_ver_id], IDX_RTL8139B |
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247 | jl .old_chip |
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261 | hidnplayr | 248 | ; set LWAKE pin to active high (default value). |
249 | ; it is for Wake-On-LAN functionality of some motherboards. |
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250 | ; this signal is used to inform the motherboard to execute a wake-up process. |
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251 | ; only at newer chips. |
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302 | hidnplayr | 252 | or al, (1 shl RTL8139_BIT_PMEn) |
253 | and al, not (1 shl RTL8139_BIT_LWACT) |
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254 | out dx, al |
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255 | add edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1 |
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256 | in al, dx |
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257 | and al, not (1 shl RTL8139_BIT_LWPTN) |
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258 | out dx, al |
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259 | jmp .finish_wake_up |
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261 | hidnplayr | 260 | .old_chip: |
261 | ; wake up older chips |
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302 | hidnplayr | 262 | and al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN)) |
263 | out dx, al |
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261 | hidnplayr | 264 | .finish_wake_up: |
265 | ; lock config and BMCR registers |
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302 | hidnplayr | 266 | xor al, al |
267 | mov edx, [io_addr] |
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268 | add edx, RTL8139_REG_9346CR |
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269 | out dx, al |
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261 | hidnplayr | 270 | ;*************************************************************************** |
271 | ; Function |
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272 | ; rt8139_reset |
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273 | ; Description |
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274 | ; Place the chip (ie, the ethernet card) into a virgin state |
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275 | ; Destroyed registers |
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276 | ; eax, ebx, ecx, edx |
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277 | ; |
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278 | ;*************************************************************************** |
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279 | rtl8139_reset: |
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302 | hidnplayr | 280 | mov edx, [io_addr] |
281 | add edx, RTL8139_REG_COMMAND |
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282 | mov al, 1 shl RTL8139_BIT_RST |
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283 | out dx, al |
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284 | mov cx, 1000 ; wait no longer for the reset |
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261 | hidnplayr | 285 | .wait_for_reset: |
302 | hidnplayr | 286 | in al, dx |
287 | test al, 1 shl RTL8139_BIT_RST |
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288 | jz .reset_completed ; RST remains 1 during reset |
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289 | dec cx |
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290 | jns .wait_for_reset |
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261 | hidnplayr | 291 | .reset_completed: |
292 | ; get MAC (hardware address) |
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302 | hidnplayr | 293 | mov ecx, 2 |
261 | hidnplayr | 294 | .mac_read_loop: |
302 | hidnplayr | 295 | lea eax, [EE_93C46_REG_ETH_ID+ecx] |
296 | push ecx |
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297 | call rtl8139_read_eeprom |
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298 | pop ecx |
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299 | mov [node_addr+ecx*2], ax |
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300 | dec ecx |
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301 | jns .mac_read_loop |
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261 | hidnplayr | 302 | ; unlock config and BMCR registers |
302 | hidnplayr | 303 | mov edx, [io_addr] |
304 | add edx, RTL8139_REG_9346CR |
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305 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0) |
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306 | out dx, al |
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261 | hidnplayr | 307 | ; initialize multicast registers (no filtering) |
302 | hidnplayr | 308 | mov eax, 0xffffffff |
309 | add edx, RTL8139_REG_MAR0 - RTL8139_REG_9346CR |
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310 | out dx, eax |
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311 | add edx, RTL8139_REG_MAR4 - RTL8139_REG_MAR0 |
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312 | out dx, eax |
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261 | hidnplayr | 313 | ; enable Rx/Tx |
302 | hidnplayr | 314 | mov al, (1 shl RTL8139_BIT_RE) or (1 shl RTL8139_BIT_TE) |
315 | add edx, RTL8139_REG_COMMAND - RTL8139_REG_MAR4 |
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316 | out dx, al |
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261 | hidnplayr | 317 | ; 32k Rxbuffer, unlimited dma burst, no wrapping, no rx threshold |
318 | ; accept broadcast packets, accept physical match packets |
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302 | hidnplayr | 319 | mov ax, RTL8139_RX_CONFIG |
320 | add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND |
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321 | out dx, ax |
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261 | hidnplayr | 322 | ; 1024 bytes DMA burst, total retries = 16 + 8 * 16 = 144 |
302 | hidnplayr | 323 | mov ax, (RTL8139_TX_MXDMA shl RTL8139_BIT_TX_MXDMA) \ |
324 | or (RTL8139_TXRR shl RTL8139_BIT_TXRR) |
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325 | add edx, RTL8139_REG_TXCONFIG - RTL8139_REG_RXCONFIG |
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326 | out dx, ax |
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261 | hidnplayr | 327 | ; enable auto negotiation |
302 | hidnplayr | 328 | add edx, RTL8139_REG_BMCR - RTL8139_REG_TXCONFIG |
329 | in ax, dx |
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330 | or ax, (1 shl RTL8139_BIT_ANE) |
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331 | out dx, ax |
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261 | hidnplayr | 332 | ; set auto negotiation advertisement |
302 | hidnplayr | 333 | add edx, RTL8139_REG_ANAR - RTL8139_REG_BMCR |
334 | in ax, dx |
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335 | or ax, (1 shl RTL8139_BIT_SELECTOR) or (1 shl RTL8139_BIT_10) \ |
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336 | or (1 shl RTL8139_BIT_10FD) or (1 shl RTL8139_BIT_TX) \ |
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337 | or (1 shl RTL8139_BIT_TXFD) |
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338 | out dx, ax |
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261 | hidnplayr | 339 | ; lock config and BMCR registers |
302 | hidnplayr | 340 | xor eax, eax |
341 | add edx, RTL8139_REG_9346CR - RTL8139_REG_ANAR |
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342 | out dx, al |
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261 | hidnplayr | 343 | ; init RX/TX pointers |
302 | hidnplayr | 344 | mov [rtl8139_rx_buff_offset], eax |
345 | mov [curr_tx_desc], eax |
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261 | hidnplayr | 346 | ; clear missing packet counter |
302 | hidnplayr | 347 | add edx, RTL8139_REG_MPC - RTL8139_REG_9346CR |
348 | out dx, eax |
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261 | hidnplayr | 349 | ; disable all interrupts |
302 | hidnplayr | 350 | add edx, RTL8139_REG_IMR - RTL8139_REG_MPC |
351 | out dx, ax |
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261 | hidnplayr | 352 | ; set RxBuffer address, init RX buffer offset, init TX ring |
302 | hidnplayr | 353 | mov eax, rtl8139_rx_buff |
354 | add edx, RTL8139_REG_RBSTART - RTL8139_REG_IMR |
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355 | out dx, eax |
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261 | hidnplayr | 356 | ; Indicate that we have successfully reset the card |
302 | hidnplayr | 357 | mov eax, [pci_data] |
358 | mov [eth_status], eax |
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359 | ret |
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261 | hidnplayr | 360 | |
361 | ;*************************************************************************** |
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362 | ; Function |
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363 | ; rtl8139_read_eeprom |
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364 | ; Description |
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365 | ; reads eeprom type 93c46 and 93c56 |
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366 | ; Parameters |
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367 | ; al - word to be read (6bit in case of 93c46 and 8bit otherwise) |
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368 | ; Return value |
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369 | ; ax - word read in |
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370 | ; Destroyed register(s) |
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371 | ; eax, cx, ebx, edx |
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372 | ; |
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373 | ;*************************************************************************** |
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374 | rtl8139_read_eeprom: |
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302 | hidnplayr | 375 | movzx ebx, al |
376 | mov edx, [io_addr] |
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377 | add edx, RTL8139_REG_RXCONFIG |
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378 | in al, dx |
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379 | test al, (1 shl RTL8139_BIT_9356SEL) |
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380 | jz .type_93c46 |
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261 | hidnplayr | 381 | ; and bl, 01111111b ; don't care first bit |
302 | hidnplayr | 382 | or bx, EE_93C56_READ_CMD ; it contains start bit |
383 | mov cx, EE_93C56_CMD_LENGTH-1 ; cmd_loop counter |
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384 | jmp .read_eeprom |
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261 | hidnplayr | 385 | .type_93c46: |
302 | hidnplayr | 386 | and bl, 00111111b |
387 | or bx, EE_93C46_READ_CMD ; it contains start bit |
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388 | mov cx, EE_93C46_CMD_LENGTH-1 ; cmd_loop counter |
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261 | hidnplayr | 389 | .read_eeprom: |
302 | hidnplayr | 390 | add edx, RTL8139_REG_9346CR - RTL8139_REG_RXCONFIG_0 |
261 | hidnplayr | 391 | ; mov al, (1 shl RTL8139_BIT_93C46_EEM1) |
392 | ; out dx, al |
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302 | hidnplayr | 393 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) \ |
394 | or (1 shl RTL8139_BIT_93C46_EECS) ; wake up the eeprom |
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395 | out dx, al |
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261 | hidnplayr | 396 | .cmd_loop: |
302 | hidnplayr | 397 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS) |
398 | bt bx, cx |
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399 | jnc .zero_bit |
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400 | or al, (1 shl RTL8139_BIT_93C46_EEDI) |
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261 | hidnplayr | 401 | .zero_bit: |
302 | hidnplayr | 402 | out dx, al |
261 | hidnplayr | 403 | ; push eax |
404 | ; in eax, dx ; eeprom delay |
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405 | ; pop eax |
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302 | hidnplayr | 406 | or al, (1 shl RTL8139_BIT_93C46_EESK) |
407 | out dx, al |
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261 | hidnplayr | 408 | ; in eax, dx ; eeprom delay |
302 | hidnplayr | 409 | dec cx |
410 | jns .cmd_loop |
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261 | hidnplayr | 411 | ; in eax, dx ; eeprom delay |
302 | hidnplayr | 412 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS) |
413 | out dx, al |
||
414 | mov cl, 0xf |
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261 | hidnplayr | 415 | .read_loop: |
302 | hidnplayr | 416 | shl ebx, 1 |
417 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) \ |
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418 | or (1 shl RTL8139_BIT_93C46_EECS) \ |
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419 | or (1 shl RTL8139_BIT_93C46_EESK) |
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420 | out dx, al |
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261 | hidnplayr | 421 | ; in eax, dx ; eeprom delay |
302 | hidnplayr | 422 | in al, dx |
423 | and al, (1 shl RTL8139_BIT_93C46_EEDO) |
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424 | jz .dont_set |
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425 | inc ebx |
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261 | hidnplayr | 426 | .dont_set: |
302 | hidnplayr | 427 | mov al, (1 shl RTL8139_BIT_93C46_EEM1) \ |
428 | or (1 shl RTL8139_BIT_93C46_EECS) |
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429 | out dx, al |
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261 | hidnplayr | 430 | ; in eax, dx ; eeprom delay |
302 | hidnplayr | 431 | dec cl |
432 | jns .read_loop |
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433 | xor al, al |
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434 | out dx, al |
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435 | mov ax, bx |
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436 | ret |
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261 | hidnplayr | 437 | |
438 | ;*************************************************************************** |
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439 | ; Function |
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440 | ; rtl8139_transmit |
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441 | ; Description |
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442 | ; Transmits a packet of data via the ethernet card |
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443 | ; Pointer to 48 bit destination address in edi |
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444 | ; Type of packet in bx |
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445 | ; size of packet in ecx |
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446 | ; pointer to packet data in esi |
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447 | ; Destroyed registers |
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448 | ; eax, edx, esi, edi |
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449 | ; ToDo |
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450 | ; for waiting of timeout the rtl8139 internal timer |
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451 | ; should be used |
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452 | ; |
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453 | ;*************************************************************************** |
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454 | rtl8139_transmit: |
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302 | hidnplayr | 455 | cmp ecx, MAX_ETH_FRAME_SIZE |
456 | jg .finish ; packet is too long |
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457 | push ecx |
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261 | hidnplayr | 458 | ; check descriptor |
302 | hidnplayr | 459 | mov ecx, [curr_tx_desc] |
460 | mov edx, [io_addr] |
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461 | lea edx, [edx+ecx*4+RTL8139_REG_TSD0] |
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462 | push edx ebx |
||
463 | in ax, dx |
||
323 | hidnplayr | 464 | test ax, 0x1fff ; or no size given |
465 | jz .send_packet |
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466 | and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN) |
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302 | hidnplayr | 467 | cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN) |
468 | jz .send_packet |
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261 | hidnplayr | 469 | ; wait for timeout |
302 | hidnplayr | 470 | mov ebx, RTL8139_TX_TIMEOUT |
471 | mov eax, 0x5 ; delay x/100 secs |
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472 | int 0x40 |
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473 | in ax, dx |
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474 | and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN) |
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475 | cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN) |
||
476 | jz .send_packet |
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261 | hidnplayr | 477 | ; chip hung, reset it |
302 | hidnplayr | 478 | call rtl8139_reset |
261 | hidnplayr | 479 | ; reset the card |
480 | .send_packet: |
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481 | ; calculate tx_buffer address |
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302 | hidnplayr | 482 | pop ebx |
483 | push esi |
||
484 | mov eax, MAX_ETH_FRAME_SIZE |
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485 | mul dword [curr_tx_desc] |
||
486 | mov esi, edi |
||
487 | lea edi, [rtl8139_tx_buff+eax] |
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488 | mov eax, edi |
||
489 | cld |
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261 | hidnplayr | 490 | ; copy destination address |
302 | hidnplayr | 491 | movsd |
492 | movsw |
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261 | hidnplayr | 493 | ; copy source address |
302 | hidnplayr | 494 | mov esi, node_addr |
495 | movsd |
||
496 | movsw |
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261 | hidnplayr | 497 | ; copy packet type |
302 | hidnplayr | 498 | mov [edi], bx |
499 | add edi, 2 |
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261 | hidnplayr | 500 | ; copy the packet data |
302 | hidnplayr | 501 | pop esi edx ecx |
502 | push ecx |
||
503 | shr ecx, 2 |
||
504 | rep movsd |
||
505 | pop ecx |
||
506 | push ecx |
||
507 | and ecx, 3 |
||
508 | rep movsb |
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261 | hidnplayr | 509 | ; set address |
302 | hidnplayr | 510 | add edx, RTL8139_REG_TSAD0 - RTL8139_REG_TSD0 |
511 | out dx, eax |
||
261 | hidnplayr | 512 | ; set size and early threshold |
302 | hidnplayr | 513 | pop eax ; pick up the size |
514 | add eax, ETH_HLEN |
||
515 | cmp eax, ETH_ZLEN |
||
516 | jnc .no_pad |
||
517 | mov eax, ETH_ZLEN |
||
261 | hidnplayr | 518 | .no_pad: |
302 | hidnplayr | 519 | or eax, (RTL8139_ERTXTH shl RTL8139_BIT_ERTXTH) |
520 | add edx, RTL8139_REG_TSD0 - RTL8139_REG_TSAD0 |
||
521 | out dx, eax |
||
261 | hidnplayr | 522 | ; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ... |
302 | hidnplayr | 523 | inc dword [curr_tx_desc] |
524 | and dword [curr_tx_desc], 3 |
||
261 | hidnplayr | 525 | .finish: |
302 | hidnplayr | 526 | ret |
261 | hidnplayr | 527 | |
528 | ;*************************************************************************** |
||
529 | ; Function |
||
530 | ; rtl8139_poll |
||
531 | ; |
||
532 | ; Description |
||
533 | ; Polls the ethernet card for a received packet |
||
534 | ; Received data, if any, ends up in Ether_buffer |
||
535 | ; Destroyed register(s) |
||
536 | ; eax, edx, ecx |
||
537 | ; |
||
538 | ;*************************************************************************** |
||
539 | rtl8139_poll: |
||
302 | hidnplayr | 540 | mov word [eth_rx_data_len], 0 |
541 | mov edx, [io_addr] |
||
542 | add edx, RTL8139_REG_COMMAND |
||
543 | in al, dx |
||
544 | test al, (1 shl RTL8139_BIT_BUFE) |
||
545 | jnz .finish |
||
261 | hidnplayr | 546 | ; new packet received copy it from rx_buffer into Ether_buffer |
302 | hidnplayr | 547 | mov eax, rtl8139_rx_buff |
548 | add eax, [rtl8139_rx_buff_offset] |
||
261 | hidnplayr | 549 | ; check if packet is ok |
302 | hidnplayr | 550 | test byte [eax], (1 shl RTL8139_BIT_ROK) |
551 | jz .reset_rx |
||
261 | hidnplayr | 552 | ; packet is ok copy it into the Ether_buffer |
302 | hidnplayr | 553 | movzx ecx, word [eax+2] ; packet length |
554 | sub ecx, 4 ; don't copy CRC |
||
555 | mov word [eth_rx_data_len], cx |
||
556 | push ecx |
||
557 | shr ecx, 2 ; first copy dword-wise |
||
558 | lea esi, [eax+4] ; don't copy the packet header |
||
559 | mov edi, Ether_buffer |
||
560 | cld |
||
561 | rep movsd ; copy the dwords |
||
562 | pop ecx |
||
563 | and ecx, 3 |
||
564 | rep movsb ; copy the rest bytes |
||
261 | hidnplayr | 565 | ; update rtl8139_rx_buff_offset |
302 | hidnplayr | 566 | movzx eax, word [eax+2] ; packet length |
567 | add eax, [rtl8139_rx_buff_offset] |
||
568 | add eax, 4+3 ; packet header is 4 bytes long + dword alignment |
||
569 | and eax, not 3 ; dword alignment |
||
570 | cmp eax, RTL8139_RX_BUFFER_SIZE |
||
571 | jl .no_wrap |
||
572 | sub eax, RTL8139_RX_BUFFER_SIZE |
||
261 | hidnplayr | 573 | .no_wrap: |
302 | hidnplayr | 574 | mov [rtl8139_rx_buff_offset], eax |
261 | hidnplayr | 575 | ; update CAPR register |
302 | hidnplayr | 576 | sub eax, 0x10 ; value 0x10 is a constant for CAPR |
577 | add edx, RTL8139_REG_CAPR - RTL8139_REG_COMMAND |
||
578 | out dx, ax |
||
261 | hidnplayr | 579 | .finish: |
580 | ; clear active interrupt sources |
||
302 | hidnplayr | 581 | mov edx, [io_addr] |
582 | add edx, RTL8139_REG_ISR |
||
583 | in ax, dx |
||
584 | out dx, ax |
||
585 | ret |
||
261 | hidnplayr | 586 | .reset_rx: |
302 | hidnplayr | 587 | in al, dx ; read command register |
588 | push eax |
||
589 | and al, not (1 shl RTL8139_BIT_RE) |
||
590 | out dx, al |
||
591 | pop eax |
||
592 | out dx, al |
||
593 | add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND |
||
594 | mov ax, RTL8139_RX_CONFIG |
||
595 | out dx, ax |
||
596 | ret |
||
597 | |||
598 | rtl8139_cable: |
||
599 | pusha |
||
600 | mov edx, [io_addr] |
||
601 | add edx, 0x58 |
||
602 | in al,dx |
||
603 | test al,1 SHL 2 |
||
604 | jnz .notconnected |
||
605 | popa |
||
606 | xor al,al |
||
607 | inc al |
||
608 | ret |
||
609 | .notconnected: |
||
610 | popa |
||
611 | xor al,al |
||
612 | ret> |