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Rev | Author | Line No. | Line |
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4610 | clevermous | 1 | ; Simple test for ring-3 debugging of mtrr.inc. |
2 | ; Contains some inputs taken from real-life MTRRs and expected outputs. |
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3 | format PE console |
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4 | ;include 'win32a.inc' |
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5 | macro $Revision [args] |
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6 | { |
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7 | } |
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7133 | dunkaist | 8 | macro ignore_empty_revision_keyword { |
9 | macro $Revi#sion$ \{\} |
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10 | } |
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11 | ignore_empty_revision_keyword |
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4610 | clevermous | 12 | include '../proc32.inc' |
13 | include '../struct.inc' |
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14 | entry start |
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15 | |||
16 | ; one test has 8, another test has 10 |
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17 | ; this is the maximal value for storing/copying, real value is in MTRRCAP |
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18 | MAX_VARIABLE_MTRR = 10 |
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19 | |||
20 | start: |
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21 | ; Copy test inputs, run init_mtrr, compare with test outputs. Repeat. |
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22 | mov esi, test1_in_data |
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23 | mov edi, mtrrdata |
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24 | mov ecx, mtrrdata_size / 4 |
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25 | rep movsd |
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26 | call init_mtrr |
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27 | mov esi, test1_out_data |
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28 | mov edi, mtrrdata |
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29 | mov ecx, mtrrdata_size / 4 |
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30 | repz cmpsd |
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31 | jnz .fail |
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32 | mov esi, test2_in_data |
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33 | mov edi, mtrrdata |
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34 | mov ecx, mtrrdata_size / 4 |
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35 | rep movsd |
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36 | call init_mtrr |
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37 | mov esi, test2_out_data |
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38 | mov edi, mtrrdata |
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39 | mov ecx, mtrrdata_size / 4 |
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40 | repz cmpsd |
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41 | jnz .fail |
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42 | ret |
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43 | |||
44 | .fail: |
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45 | int3 |
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46 | jmp $ |
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47 | |||
48 | ; Helper procedure for _rdmsr/_wrmsr, replacements of rdmsr/wrmsr. |
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49 | ; Returns pointer to memory containing the given MSR. |
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50 | ; in: ecx = MSR |
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51 | ; out: esi -> MSR data |
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52 | proc get_msr_ptr |
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53 | mov esi, mtrrcap |
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54 | cmp ecx, 0xFE |
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55 | jz .ok |
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56 | mov esi, mtrr_def_type |
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57 | cmp ecx, 0x2FF |
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58 | jz .ok |
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59 | lea esi, [ecx-0x200] |
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60 | cmp esi, MAX_VARIABLE_MTRR*2 |
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61 | jae .fail |
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62 | lea esi, [mtrr+esi*8] |
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63 | .ok: |
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64 | ret |
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65 | .fail: |
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66 | int3 |
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67 | ret |
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68 | endp |
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69 | |||
70 | ; Emulates rdmsr. |
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71 | proc _rdmsr |
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72 | push esi |
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73 | call get_msr_ptr |
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74 | mov eax, [esi] |
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75 | mov edx, [esi+4] |
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76 | pop esi |
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77 | ret |
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78 | endp |
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79 | |||
80 | ; Emulates wrmsr. |
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81 | proc _wrmsr |
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82 | push esi |
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83 | call get_msr_ptr |
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84 | mov [esi], eax |
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85 | mov [esi+4], edx |
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86 | pop esi |
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87 | ret |
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88 | endp |
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89 | |||
90 | ; Macro to substitute rdmsr/wrmsr with emulating code. |
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91 | macro rdmsr |
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92 | { |
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93 | call _rdmsr |
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94 | } |
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95 | macro wrmsr |
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96 | { |
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97 | call _wrmsr |
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98 | } |
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99 | ; Our emulation of rdmsr/wrmsr has nothing to do with real cache |
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100 | ; and system-wide settings, |
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101 | ; remove all attempts to wbinvd and disable/enable cache in cr0. |
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102 | macro wbinvd |
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103 | { |
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104 | } |
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105 | macro mov a,b |
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106 | { |
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107 | if ~(a eq cr0) & ~(b eq cr0) |
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108 | mov a, b |
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109 | end if |
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110 | } |
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111 | macro movi r,i |
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112 | { |
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113 | push i |
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114 | pop r |
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115 | } |
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116 | |||
117 | include '../kglobals.inc' |
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7136 | dunkaist | 118 | CAPS_MTRR = 12 |
119 | MSR_MTRR_DEF_TYPE = 0x2FF |
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120 | CAPS_PGE = 13 |
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121 | CAPS_PAT = 16 |
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122 | MSR_CR_PAT = 0x277 |
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123 | PAT_VALUE = 0x00070106 ; (UC<<24)|(UCM<<16)|(WC<<8)|WB |
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124 | MEM_WB = 6 ;write-back memory |
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125 | MEM_WC = 1 ;write combined memory |
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126 | MEM_UC = 0 ;uncached memory |
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4610 | clevermous | 127 | include 'mtrr.inc' |
128 | |||
129 | BOOT_VARS = 0 |
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7132 | dunkaist | 130 | BOOT.mtrr db 1 |
4610 | clevermous | 131 | align 4 |
132 | cpu_caps dd 1 shl CAPS_MTRR |
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133 | LFBAddress dd 0xE0000000 |
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134 | LFBSize dd 0x10000000 |
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135 | MEM_AMOUNT dd 0 ; not used, needed for compilation |
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136 | |||
137 | align 4 |
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138 | ; Test 1: input |
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139 | test1_in_data: |
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140 | test1_phys_addr_width db 36 |
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141 | rb 3 |
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142 | test1_in_mtrrcap dq 0xD08 |
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143 | test1_in_mtrr_def_type dq 0xC00 |
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144 | test1_in_mtrrs: |
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145 | dq 0x000000006, 0xF00000800 |
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146 | dq 0x100000006, 0xFC0000800 |
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147 | dq 0x0BC000000, 0xFFC000800 |
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148 | dq 0x0C0000000, 0xFC0000800 |
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149 | dq 0x138000000, 0xFF8000800 |
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150 | dq 0, 0 |
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151 | dq 0, 0 |
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152 | dq 0, 0 |
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153 | dq -1, -1 ; not used |
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154 | dq -1, -1 ; not used |
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155 | ; Test 1: output |
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156 | test1_out_data: |
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157 | dd 36 ; phys_addr_width, readonly |
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158 | dq 0xD08 ; MTRRCAP, readonly |
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159 | dq 0xC00 ; MTRR_DEF_TYPE, should be the same |
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160 | dq 0x000000006, 0xF80000800 |
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161 | dq 0x080000006, 0xFC0000800 |
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162 | dq 0x0BC000000, 0xFFC000800 |
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163 | dq 0x100000006, 0xFC0000800 |
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164 | dq 0x138000000, 0xFF8000800 |
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165 | dq 0x0E0000001, 0xFFF000800 ; added for [LFBAddress] |
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166 | dq 0, 0 |
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167 | dq 0, 0 |
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168 | dq -1, -1 ; not used |
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169 | dq -1, -1 ; not used |
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170 | |||
171 | ; Test 2: input |
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172 | test2_in_data: |
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173 | test2_phys_addr_width db 39 |
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174 | rb 3 |
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175 | test2_in_mtrrcap dq 0xD0A |
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176 | test2_in_mtrr_def_type dq 0xC00 |
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177 | test2_in_mtrrs: |
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178 | dq 0x0000000006, 0x7F00000800 |
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179 | dq 0x0100000006, 0x7FE0000800 |
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180 | dq 0x00E0000000, 0x7FE0000800 |
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181 | dq 0x00DC000000, 0x7FFC000800 |
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182 | dq 0x00DBC00000, 0x7FFFC00800 |
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183 | dq 0x011F800000, 0x7FFF800800 |
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184 | dq 0x011F400000, 0x7FFFC00800 |
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185 | dq 0x011F200000, 0x7FFFE00800 |
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186 | dq 0, 0 |
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187 | dq 0, 0 |
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188 | |||
189 | ; Test 2: output |
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190 | test2_out_data: |
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191 | dd 39 ; phys_addr_width, readonly |
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192 | dq 0xD0A ; MTRRCAP, readonly |
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193 | dq 0xC00 ; MTRR_DEF_TYPE, should be the same |
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194 | dq 0x0000000006, 0x7F80000800 |
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195 | dq 0x0080000006, 0x7FC0000800 |
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196 | dq 0x00C0000006, 0x7FE0000800 |
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197 | dq 0x00DC000000, 0x7FFC000800 |
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198 | dq 0x00DBC00000, 0x7FFFC00800 |
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199 | dq 0x0100000006, 0x7FE0000800 |
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200 | dq 0x011F800000, 0x7FFF800800 |
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201 | dq 0x011F400000, 0x7FFFC00800 |
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202 | dq 0x011F200000, 0x7FFFE00800 |
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203 | dq 0x00E0000001, 0x7FFF000800 ; added for [LFBAddress] |
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204 | IncludeIGlobals |
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205 | align 4 |
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206 | mtrrdata: |
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207 | cpu_phys_addr_width db ? |
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208 | rb 3 |
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209 | mtrrcap dq ? |
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210 | mtrr_def_type dq ? |
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211 | mtrr rq MAX_VARIABLE_MTRR*2 |
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212 | mtrrdata_size = $ - mtrrdata |
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213 | IncludeUGlobals8)|WB |