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2288 | clevermous | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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2455 | mario79 | 3 | ;; Copyright (C) KolibriOS team 2010-2011. All rights reserved. ;; |
2288 | clevermous | 4 | ;; Distributed under terms of the GNU General Public License ;; |
5 | ;; ;; |
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6 | ;; ;; |
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7 | ;; PCIe.INC ;; |
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8 | ;; ;; |
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9 | ;; Extended PCI express services ;; |
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10 | ;; ;; |
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11 | ;; art_zh |
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12 | ;; ;; |
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13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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14 | |||
15 | $Revision: 1463 $ |
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16 | |||
17 | ;*************************************************************************** |
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18 | ; Function |
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19 | ; pci_ext_config: |
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20 | ; |
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21 | ; Description |
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22 | ; PCIe extended (memory-mapped) config space detection |
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23 | ; |
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24 | ; WARNINGs: |
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25 | ; 1) Very Experimental! |
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26 | ; 2) direct HT-detection (no ACPI or BIOS service used) |
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27 | ; 3) Only AMD/HT processors currently supported |
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28 | ; |
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29 | ;*************************************************************************** |
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30 | |||
31 | PCIe_CONFIG_SPACE equ 0xF0000000 ; to be moved to const.inc |
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32 | mmio_pcie_cfg_addr dd 0x0 ; intel pcie space may be defined here |
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33 | mmio_pcie_cfg_lim dd 0x0 ; upper pcie space address |
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34 | |||
35 | |||
36 | align 4 |
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37 | |||
38 | pci_ext_config: |
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39 | |||
40 | mov ebx, [mmio_pcie_cfg_addr] |
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41 | or ebx, ebx |
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42 | jz @f |
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43 | or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
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44 | jnz .pcie_failed |
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45 | add ebx, 0x0FFFFC |
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46 | cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
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47 | ja .pcie_failed |
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48 | jmp .pcie_cfg_mapped |
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49 | @@: |
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50 | mov ebx, [cpu_vendor] |
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51 | cmp ebx, dword [AMD_str] |
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52 | jne .pcie_failed |
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53 | mov bx, 0xC184 ; dev = 24, fn = 01, reg = 84h |
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54 | |||
55 | .check_HT_mmio: |
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56 | mov cx, bx |
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57 | mov ax, 0x0002 ; bus = 0, 1dword to read |
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58 | call pci_read_reg |
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59 | mov bx, cx |
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60 | sub bl, 4 |
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61 | and al, 0x80 ; check the NP bit |
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62 | jz .no_pcie_cfg |
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63 | shl eax, 8 ; bus:[27..20], dev:[19:15] |
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64 | or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
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65 | mov [mmio_pcie_cfg_lim], eax |
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66 | mov cl, bl |
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67 | mov ax, 0x0002 ; bus = 0, 1dword to read |
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68 | call pci_read_reg |
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69 | mov bx, cx |
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70 | test al, 0x03 ; MMIO Base RW enabled? |
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71 | jz .no_pcie_cfg |
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72 | test al, 0x0C ; MMIO Base locked? |
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73 | jnz .no_pcie_cfg |
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74 | xor al, al |
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75 | shl eax, 8 |
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76 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
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77 | jnz .no_pcie_cfg |
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78 | mov [mmio_pcie_cfg_addr], eax |
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79 | add eax, 0x000FFFFC |
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80 | sub eax, [mmio_pcie_cfg_lim]; MMIO must cover at least one bus |
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81 | ja .no_pcie_cfg |
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82 | |||
83 | ; -- it looks like a true PCIe config space; |
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84 | mov eax, [mmio_pcie_cfg_addr] ; physical address |
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85 | or eax, (PG_SHARED + PG_LARGE + PG_USER) |
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86 | mov ebx, PCIe_CONFIG_SPACE ; linear address |
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87 | mov ecx, ebx |
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88 | shr ebx, 20 |
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89 | add ebx, sys_pgdir ; PgDir entry @ |
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90 | @@: |
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91 | mov dword[ebx], eax ; map 4 buses |
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92 | invlpg [ecx] |
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93 | cmp bl, 4 |
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94 | jz .pcie_cfg_mapped ; fix it later |
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95 | add bl, 4 ; next PgDir entry |
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96 | add eax, 0x400000 ; eax += 4M |
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97 | add ecx, 0x400000 |
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98 | jmp @b |
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99 | |||
100 | .pcie_cfg_mapped: |
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101 | |||
102 | ; -- glad to have the extended PCIe config field found |
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103 | ; mov esi, boot_pcie_ok |
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104 | ; call boot_log |
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105 | ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
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106 | |||
107 | .no_pcie_cfg: |
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108 | |||
109 | xor eax, eax |
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110 | mov [mmio_pcie_cfg_addr], eax |
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111 | mov [mmio_pcie_cfg_lim], eax |
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112 | add bl, 12 |
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113 | cmp bl, 0xC0 ; MMIO regs lay below this offset |
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114 | jb .check_HT_mmio |
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115 | .pcie_failed: |
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116 | ; mov esi, boot_pcie_fail |
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117 | ; call boot_log |
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118 | ret ; <<<<<<<<< FAILURE >>>>>>>>>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<><<<<<<<<<><<<<<<<<<<> |
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119 |