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Rev | Author | Line No. | Line |
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2886 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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7 | ;; Version 2, June 1991 ;; |
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8 | ;; ;; |
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9 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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10 | |||
11 | |||
12 | ; PCI Bus defines |
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13 | |||
14 | PCI_HEADER_TYPE = 0x0e ; 8 bit |
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15 | PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit |
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2935 | hidnplayr | 16 | PCI_BASE_ADDRESS_1 = 0x14 ; 32 bits |
17 | PCI_BASE_ADDRESS_2 = 0x18 ; 32 bits |
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18 | PCI_BASE_ADDRESS_3 = 0x1c ; 32 bits |
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19 | PCI_BASE_ADDRESS_4 = 0x20 ; 32 bits |
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2886 | hidnplayr | 20 | PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits |
21 | PCI_BASE_ADDRESS_SPACE_IO = 0x01 |
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22 | PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC |
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2935 | hidnplayr | 23 | PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0 |
2886 | hidnplayr | 24 | |
25 | ; PCI programming |
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26 | |||
2935 | hidnplayr | 27 | PCI_VENDOR_ID = 0x00 ; 16 bit |
28 | PCI_DEVICE_ID = 0x02 ; 16 bits |
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2886 | hidnplayr | 29 | PCI_REG_COMMAND = 0x4 ; command register |
30 | PCI_REG_STATUS = 0x6 ; status register |
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2935 | hidnplayr | 31 | PCI_REVISION_ID = 0x08 ; 8 bits |
2886 | hidnplayr | 32 | PCI_REG_LATENCY = 0xd ; latency timer register |
33 | PCI_REG_CAP_PTR = 0x34 ; capabilities pointer |
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2935 | hidnplayr | 34 | PCI_REG_IRQ = 0x3c |
2886 | hidnplayr | 35 | PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block |
36 | PCI_REG_PM_STATUS = 0x4 ; power management status register |
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37 | PCI_REG_PM_CTRL = 0x4 ; power management control register |
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38 | PCI_BIT_PIO = 1 ; bit0: io space control |
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39 | PCI_BIT_MMIO = 2 ; bit1: memory space control |
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40 | PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master |
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41 | |||
42 | |||
3205 | hidnplayr | 43 | macro PCI_find_io { |
2886 | hidnplayr | 44 | |
45 | local .check, .inc, .got |
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46 | |||
47 | xor eax, eax |
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48 | mov esi, PCI_BASE_ADDRESS_0 |
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49 | .check: |
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3205 | hidnplayr | 50 | stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi |
2886 | hidnplayr | 51 | |
52 | test eax, PCI_BASE_ADDRESS_IO_MASK |
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53 | jz .inc |
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54 | |||
55 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
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56 | jz .inc |
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57 | |||
58 | and eax, PCI_BASE_ADDRESS_IO_MASK |
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59 | jmp .got |
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60 | |||
61 | .inc: |
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62 | add esi, 4 |
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63 | cmp esi, PCI_BASE_ADDRESS_5 |
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2922 | hidnplayr | 64 | jbe .check |
65 | xor eax, eax |
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2886 | hidnplayr | 66 | |
67 | .got: |
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3205 | hidnplayr | 68 | mov [device.io_addr], eax |
2886 | hidnplayr | 69 | |
70 | } |
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71 | |||
72 | |||
3205 | hidnplayr | 73 | macro PCI_find_mmio32 { |
2886 | hidnplayr | 74 | |
2922 | hidnplayr | 75 | local .check, .inc, .got |
2886 | hidnplayr | 76 | |
77 | mov esi, PCI_BASE_ADDRESS_0 |
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78 | .check: |
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3205 | hidnplayr | 79 | stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi |
2886 | hidnplayr | 80 | |
2922 | hidnplayr | 81 | test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address? |
82 | jnz .inc |
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2886 | hidnplayr | 83 | |
2922 | hidnplayr | 84 | test eax, 100b ; 64 bit? |
85 | jnz .inc |
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86 | and eax, not 1111b |
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87 | jmp .got |
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88 | |||
89 | .inc: |
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2886 | hidnplayr | 90 | add esi, 4 |
91 | cmp esi, PCI_BASE_ADDRESS_5 |
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2922 | hidnplayr | 92 | jbe .check |
93 | xor eax, eax |
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2886 | hidnplayr | 94 | |
95 | .got: |
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3205 | hidnplayr | 96 | mov [device.mmio_addr], eax |
2886 | hidnplayr | 97 | } |
98 | |||
3205 | hidnplayr | 99 | macro PCI_find_irq { |
2886 | hidnplayr | 100 | |
3205 | hidnplayr | 101 | stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_IRQ |
102 | mov [device.irq_line], al |
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2886 | hidnplayr | 103 | |
104 | } |
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105 | |||
3205 | hidnplayr | 106 | macro PCI_find_rev { |
2886 | hidnplayr | 107 | |
3205 | hidnplayr | 108 | stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REVISION_ID |
109 | mov [device.revision], al |
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2886 | hidnplayr | 110 | |
111 | } |
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112 | |||
3205 | hidnplayr | 113 | macro PCI_make_bus_master bus, dev { |
2886 | hidnplayr | 114 | |
3205 | hidnplayr | 115 | stdcall PciRead32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND |
2911 | hidnplayr | 116 | or al, PCI_BIT_MASTER |
3205 | hidnplayr | 117 | stdcall PciWrite32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND, eax |
2886 | hidnplayr | 118 | |
2911 | hidnplayr | 119 | } |
2886 | hidnplayr | 120 | |
3205 | hidnplayr | 121 | macro PCI_adjust_latency min { |
2911 | hidnplayr | 122 | |
3205 | hidnplayr | 123 | local .not |
124 | |||
125 | stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY |
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2911 | hidnplayr | 126 | cmp al, min |
3205 | hidnplayr | 127 | ja .not |
2911 | hidnplayr | 128 | mov al, min |
3205 | hidnplayr | 129 | stdcall PciWrite8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY, eax |
130 | .not: |
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2911 | hidnplayr | 131 | |
132 | } |