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2886 hidnplayr 1 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                                                                 ;;
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;; Copyright (C) KolibriOS team 2004-2012. All rights reserved.    ;;
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;; Distributed under terms of the GNU General Public License       ;;
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;;                                                                 ;;
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;;          GNU GENERAL PUBLIC LICENSE                             ;;
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;;             Version 2, June 1991                                ;;
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;;                                                                 ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; PCI Bus defines
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        PCI_HEADER_TYPE                 = 0x0e          ; 8 bit
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        PCI_BASE_ADDRESS_0              = 0x10          ; 32 bit
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        PCI_BASE_ADDRESS_1              = 0x14          ; 32 bits
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        PCI_BASE_ADDRESS_2              = 0x18          ; 32 bits
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        PCI_BASE_ADDRESS_3              = 0x1c          ; 32 bits
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        PCI_BASE_ADDRESS_4              = 0x20          ; 32 bits
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        PCI_BASE_ADDRESS_5              = 0x24          ; 32 bits
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        PCI_BASE_ADDRESS_SPACE_IO       = 0x01
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        PCI_BASE_ADDRESS_IO_MASK        = 0xFFFFFFFC
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        PCI_BASE_ADDRESS_MEM_MASK       = 0xFFFFFFF0
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; PCI programming
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        PCI_VENDOR_ID                   = 0x00          ; 16 bit
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        PCI_DEVICE_ID                   = 0x02          ; 16 bits
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        PCI_REG_COMMAND                 = 0x4           ; command register
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        PCI_REG_STATUS                  = 0x6           ; status register
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        PCI_REVISION_ID                 = 0x08          ; 8 bits
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        PCI_REG_LATENCY                 = 0xd           ; latency timer register
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        PCI_REG_CAP_PTR                 = 0x34          ; capabilities pointer
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        PCI_REG_IRQ                     = 0x3c
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        PCI_REG_CAPABILITY_ID           = 0x0           ; capapility ID in pm register block
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        PCI_REG_PM_STATUS               = 0x4           ; power management status register
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        PCI_REG_PM_CTRL                 = 0x4           ; power management control register
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        PCI_BIT_PIO                     = 1             ; bit0: io space control
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        PCI_BIT_MMIO                    = 2             ; bit1: memory space control
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        PCI_BIT_MASTER                  = 4             ; bit2: device acts as a PCI master
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macro   find_io bus, dev, io {
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        local   .check, .inc, .got
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        xor     eax, eax
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        mov     esi, PCI_BASE_ADDRESS_0
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        movzx   ecx, bus
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        movzx   edx, dev
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  .check:
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        push    ecx edx
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        stdcall PciRead32, ecx ,edx ,esi
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        pop     edx ecx
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        test    eax, PCI_BASE_ADDRESS_IO_MASK
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        jz      .inc
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        test    eax, PCI_BASE_ADDRESS_SPACE_IO
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        jz      .inc
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        and     eax, PCI_BASE_ADDRESS_IO_MASK
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        jmp     .got
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  .inc:
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        add     esi, 4
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        cmp     esi, PCI_BASE_ADDRESS_5
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        jbe     .check
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        xor     eax, eax
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  .got:
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        mov     io, eax
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}
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macro   find_mmio32 bus, dev, io {
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        local   .check, .inc, .got
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        mov     esi, PCI_BASE_ADDRESS_0
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  .check:
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        stdcall PciRead32, bus, dev, esi
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        test    eax, PCI_BASE_ADDRESS_SPACE_IO  ; mmio address?
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        jnz     .inc
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        test    eax, 100b       ; 64 bit?
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        jnz     .inc
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        and     eax, not 1111b
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        jmp     .got
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  .inc:
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        add     esi, 4
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        cmp     esi, PCI_BASE_ADDRESS_5
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        jbe     .check
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        xor     eax, eax
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  .got:
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        mov     io, eax
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}
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macro   find_irq bus, dev, irq {
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        push    eax edx ecx
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        movzx   ecx, bus
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        movzx   edx, dev
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        stdcall PciRead8, ecx, edx, PCI_REG_IRQ
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        mov     irq, al
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        pop     ecx edx eax
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}
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macro   find_rev bus, dev, rev {
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        push    eax edx ecx
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        movzx   ecx, bus
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        movzx   edx, dev
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        stdcall PciRead8, ecx ,edx ,0x8
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        mov     rev, al
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        pop     ecx edx eax
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}
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macro   make_bus_master bus, dev {
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        movzx   ecx, bus
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        movzx   edx, dev
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        stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND
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        or      al, PCI_BIT_MASTER
2886 hidnplayr 131 
        stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
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}
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macro   adjust_latency bus, dev, min {
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        movzx   ecx, bus
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        movzx   edx, dev
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        stdcall PciRead8, ecx ,edx, PCI_REG_LATENCY
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        cmp     al, min
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        ja      @f
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        mov     al, min
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        stdcall PciWrite8, ecx, edx, PCI_REG_LATENCY, eax
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  @@:
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}