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3769 | Serge | 1 | /* |
2 | * Copyright © 2010-2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the |
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6 | * "Software"), to deal in the Software without restriction, including |
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7 | * without limitation the rights to use, copy, modify, merge, publish, |
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8 | * distribute, sub license, and/or sell copies of the Software, and to |
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9 | * permit persons to whom the Software is furnished to do so, subject to |
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10 | * the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the |
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13 | * next paragraph) shall be included in all copies or substantial portions |
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14 | * of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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19 | * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
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20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Zhou Chang |
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26 | * |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | |||
34 | #include "assert.h" |
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35 | #include "intel_batchbuffer.h" |
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36 | #include "i965_defines.h" |
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37 | #include "i965_structs.h" |
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38 | #include "i965_drv_video.h" |
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39 | #include "i965_encoder.h" |
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40 | |||
41 | static void |
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42 | gen6_mfc_pipe_mode_select(VADriverContextP ctx, |
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43 | struct gen6_encoder_context *gen6_encoder_context, |
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44 | struct intel_batchbuffer *batch) |
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45 | { |
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46 | if (batch == NULL) |
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47 | batch = gen6_encoder_context->base.batch; |
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48 | |||
49 | BEGIN_BCS_BATCH(batch, 4); |
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50 | |||
51 | OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2)); |
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52 | OUT_BCS_BATCH(batch, |
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53 | (0 << 10) | /* disable Stream-Out */ |
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54 | (1 << 9) | /* Post Deblocking Output */ |
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55 | (0 << 8) | /* Pre Deblocking Output */ |
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56 | (0 << 7) | /* disable TLB prefectch */ |
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57 | (0 << 5) | /* not in stitch mode */ |
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58 | (1 << 4) | /* encoding mode */ |
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59 | (2 << 0)); /* Standard Select: AVC */ |
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60 | OUT_BCS_BATCH(batch, |
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61 | (0 << 20) | /* round flag in PB slice */ |
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62 | (0 << 19) | /* round flag in Intra8x8 */ |
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63 | (0 << 7) | /* expand NOA bus flag */ |
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64 | (1 << 6) | /* must be 1 */ |
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65 | (0 << 5) | /* disable clock gating for NOA */ |
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66 | (0 << 4) | /* terminate if AVC motion and POC table error occurs */ |
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67 | (0 << 3) | /* terminate if AVC mbdata error occurs */ |
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68 | (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ |
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69 | (0 << 1) | /* AVC long field motion vector */ |
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70 | (0 << 0)); /* always calculate AVC ILDB boundary strength */ |
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71 | OUT_BCS_BATCH(batch, 0); |
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72 | |||
73 | ADVANCE_BCS_BATCH(batch); |
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74 | } |
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75 | |||
76 | static void |
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77 | gen7_mfc_pipe_mode_select(VADriverContextP ctx, |
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78 | int standard_select, |
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79 | struct gen6_encoder_context *gen6_encoder_context, |
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80 | struct intel_batchbuffer *batch) |
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81 | { |
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82 | if (batch == NULL) |
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83 | batch = gen6_encoder_context->base.batch; |
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84 | |||
85 | assert(standard_select == MFX_FORMAT_MPEG2 || |
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86 | standard_select == MFX_FORMAT_AVC); |
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87 | |||
88 | BEGIN_BCS_BATCH(batch, 5); |
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89 | OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); |
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90 | OUT_BCS_BATCH(batch, |
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91 | (MFX_LONG_MODE << 17) | /* Must be long format for encoder */ |
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92 | (MFD_MODE_VLD << 15) | /* VLD mode */ |
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93 | (0 << 10) | /* disable Stream-Out */ |
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94 | (1 << 9) | /* Post Deblocking Output */ |
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95 | (0 << 8) | /* Pre Deblocking Output */ |
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96 | (0 << 5) | /* not in stitch mode */ |
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97 | (1 << 4) | /* encoding mode */ |
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98 | (standard_select << 0)); /* standard select: avc or mpeg2 */ |
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99 | OUT_BCS_BATCH(batch, |
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100 | (0 << 7) | /* expand NOA bus flag */ |
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101 | (0 << 6) | /* disable slice-level clock gating */ |
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102 | (0 << 5) | /* disable clock gating for NOA */ |
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103 | (0 << 4) | /* terminate if AVC motion and POC table error occurs */ |
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104 | (0 << 3) | /* terminate if AVC mbdata error occurs */ |
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105 | (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ |
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106 | (0 << 1) | |
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107 | (0 << 0)); |
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108 | OUT_BCS_BATCH(batch, 0); |
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109 | OUT_BCS_BATCH(batch, 0); |
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110 | |||
111 | ADVANCE_BCS_BATCH(batch); |
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112 | } |
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113 | |||
114 | static void |
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115 | gen6_mfc_surface_state(VADriverContextP ctx, |
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116 | struct gen6_encoder_context *gen6_encoder_context, |
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117 | struct intel_batchbuffer *batch) |
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118 | { |
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119 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
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120 | |||
121 | if (batch == NULL) |
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122 | batch = gen6_encoder_context->base.batch; |
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123 | |||
124 | BEGIN_BCS_BATCH(batch, 6); |
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125 | |||
126 | OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); |
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127 | OUT_BCS_BATCH(batch, 0); |
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128 | OUT_BCS_BATCH(batch, |
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129 | ((mfc_context->surface_state.height - 1) << 19) | |
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130 | ((mfc_context->surface_state.width - 1) << 6)); |
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131 | OUT_BCS_BATCH(batch, |
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132 | (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ |
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133 | (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ |
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134 | (0 << 22) | /* surface object control state, FIXME??? */ |
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135 | ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */ |
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136 | (0 << 2) | /* must be 0 for interleave U/V */ |
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137 | (1 << 1) | /* must be y-tiled */ |
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138 | (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */ |
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139 | OUT_BCS_BATCH(batch, |
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140 | (0 << 16) | /* must be 0 for interleave U/V */ |
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141 | (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */ |
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142 | OUT_BCS_BATCH(batch, 0); |
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143 | ADVANCE_BCS_BATCH(batch); |
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144 | } |
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145 | |||
146 | static void |
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147 | gen7_mfc_surface_state(VADriverContextP ctx, |
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148 | struct gen6_encoder_context *gen6_encoder_context, |
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149 | struct intel_batchbuffer *batch) |
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150 | { |
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151 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
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152 | |||
153 | if (batch == NULL) |
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154 | batch = gen6_encoder_context->base.batch; |
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155 | |||
156 | BEGIN_BCS_BATCH(batch, 6); |
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157 | |||
158 | OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); |
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159 | OUT_BCS_BATCH(batch, 0); |
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160 | OUT_BCS_BATCH(batch, |
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161 | ((mfc_context->surface_state.height - 1) << 18) | |
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162 | ((mfc_context->surface_state.width - 1) << 4)); |
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163 | OUT_BCS_BATCH(batch, |
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164 | (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ |
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165 | (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ |
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166 | (0 << 22) | /* surface object control state, FIXME??? */ |
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167 | ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */ |
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168 | (0 << 2) | /* must be 0 for interleave U/V */ |
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169 | (1 << 1) | /* must be tiled */ |
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170 | (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */ |
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171 | OUT_BCS_BATCH(batch, |
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172 | (0 << 16) | /* must be 0 for interleave U/V */ |
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173 | (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */ |
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174 | OUT_BCS_BATCH(batch, 0); |
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175 | ADVANCE_BCS_BATCH(batch); |
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176 | } |
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177 | |||
178 | static void |
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179 | gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, |
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180 | struct gen6_encoder_context *gen6_encoder_context, |
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181 | struct intel_batchbuffer *batch) |
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182 | { |
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183 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
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184 | int i; |
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185 | |||
186 | if (batch == NULL) |
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187 | batch = gen6_encoder_context->base.batch; |
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188 | |||
189 | BEGIN_BCS_BATCH(batch, 24); |
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190 | |||
191 | OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); |
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192 | |||
193 | OUT_BCS_BATCH(batch, 0); /* pre output addr */ |
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194 | |||
195 | OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, |
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196 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
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197 | 0); /* post output addr */ |
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198 | |||
199 | OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, |
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200 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
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201 | 0); /* uncompressed data */ |
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202 | |||
203 | OUT_BCS_BATCH(batch, 0); /* StreamOut data*/ |
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204 | OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, |
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205 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
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206 | 0); |
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207 | OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, |
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208 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
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209 | 0); |
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210 | /* 7..22 Reference pictures*/ |
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211 | for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { |
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212 | if ( mfc_context->reference_surfaces[i].bo != NULL) { |
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213 | OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo, |
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214 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
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215 | 0); |
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216 | } else { |
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217 | OUT_BCS_BATCH(batch, 0); |
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218 | } |
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219 | } |
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220 | OUT_BCS_BATCH(batch, 0); /* no block status */ |
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221 | |||
222 | ADVANCE_BCS_BATCH(batch); |
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223 | } |
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224 | |||
225 | static void |
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226 | gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, |
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227 | struct gen6_encoder_context *gen6_encoder_context, |
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228 | struct intel_batchbuffer *batch) |
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229 | { |
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230 | struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context; |
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231 | |||
232 | if (batch == NULL) |
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233 | batch = gen6_encoder_context->base.batch; |
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234 | |||
235 | BEGIN_BCS_BATCH(batch, 11); |
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236 | |||
237 | OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); |
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238 | OUT_BCS_BATCH(batch, 0); |
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239 | OUT_BCS_BATCH(batch, 0); |
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240 | /* MFX Indirect MV Object Base Address */ |
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241 | OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
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242 | OUT_BCS_BATCH(batch, 0); |
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243 | OUT_BCS_BATCH(batch, 0); |
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244 | OUT_BCS_BATCH(batch, 0); |
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245 | OUT_BCS_BATCH(batch, 0); |
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246 | OUT_BCS_BATCH(batch, 0); |
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247 | /*MFC Indirect PAK-BSE Object Base Address for Encoder*/ |
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248 | OUT_BCS_BATCH(batch, 0); |
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249 | OUT_BCS_BATCH(batch, 0); |
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250 | |||
251 | ADVANCE_BCS_BATCH(batch); |
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252 | } |
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253 | |||
254 | static void |
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255 | gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, |
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256 | struct gen6_encoder_context *gen6_encoder_context, |
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257 | struct intel_batchbuffer *batch) |
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258 | { |
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259 | struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context; |
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260 | |||
261 | if (batch == NULL) |
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262 | batch = gen6_encoder_context->base.batch; |
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263 | |||
264 | BEGIN_BCS_BATCH(batch, 11); |
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265 | |||
266 | OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); |
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267 | OUT_BCS_BATCH(batch, 0); |
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268 | OUT_BCS_BATCH(batch, 0); |
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269 | /* MFX Indirect MV Object Base Address */ |
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270 | OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
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271 | OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ |
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272 | OUT_BCS_BATCH(batch, 0); |
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273 | OUT_BCS_BATCH(batch, 0); |
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274 | OUT_BCS_BATCH(batch, 0); |
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275 | OUT_BCS_BATCH(batch, 0); |
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276 | /*MFC Indirect PAK-BSE Object Base Address for Encoder*/ |
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277 | OUT_BCS_BATCH(batch, 0); |
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278 | OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ |
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279 | |||
280 | ADVANCE_BCS_BATCH(batch); |
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281 | } |
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282 | |||
283 | static void |
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284 | gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, |
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285 | struct gen6_encoder_context *gen6_encoder_context, |
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286 | struct intel_batchbuffer *batch) |
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287 | { |
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288 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
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289 | |||
290 | if (batch == NULL) |
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291 | batch = gen6_encoder_context->base.batch; |
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292 | |||
293 | BEGIN_BCS_BATCH(batch, 4); |
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294 | |||
295 | OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); |
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296 | OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo, |
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297 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
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298 | 0); |
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299 | OUT_BCS_BATCH(batch, 0); |
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300 | OUT_BCS_BATCH(batch, 0); |
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301 | |||
302 | ADVANCE_BCS_BATCH(batch); |
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303 | } |
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304 | |||
305 | static void |
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306 | gen6_mfc_avc_img_state(VADriverContextP ctx, |
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307 | struct gen6_encoder_context *gen6_encoder_context, |
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308 | struct intel_batchbuffer *batch) |
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309 | { |
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310 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
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311 | int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; |
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312 | int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; |
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313 | |||
314 | if (batch == NULL) |
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315 | batch = gen6_encoder_context->base.batch; |
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316 | |||
317 | BEGIN_BCS_BATCH(batch, 13); |
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318 | OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2)); |
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319 | OUT_BCS_BATCH(batch, |
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320 | ((width_in_mbs * height_in_mbs) & 0xFFFF)); |
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321 | OUT_BCS_BATCH(batch, |
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322 | (height_in_mbs << 16) | |
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323 | (width_in_mbs << 0)); |
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324 | OUT_BCS_BATCH(batch, |
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325 | (0 << 24) | /*Second Chroma QP Offset*/ |
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326 | (0 << 16) | /*Chroma QP Offset*/ |
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327 | (0 << 14) | /*Max-bit conformance Intra flag*/ |
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328 | (0 << 13) | /*Max Macroblock size conformance Inter flag*/ |
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329 | (1 << 12) | /*Should always be written as "1" */ |
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330 | (0 << 10) | /*QM Preset FLag */ |
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331 | (0 << 8) | /*Image Structure*/ |
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332 | (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/ |
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333 | OUT_BCS_BATCH(batch, |
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334 | (0 << 16) | /*Mininum Frame size*/ |
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335 | (0 << 15) | /*Disable reading of Macroblock Status Buffer*/ |
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336 | (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/ |
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337 | (0 << 13) | /*CABAC 0 word insertion test enable*/ |
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338 | (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/ |
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339 | (1 << 10) | /*Chroma Format IDC, 4:2:0*/ |
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340 | (1 << 7) | /*0:CAVLC encoding mode,1:CABAC*/ |
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341 | (0 << 6) | /*Only valid for VLD decoding mode*/ |
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342 | (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/ |
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343 | (0 << 4) | /*Direct 8x8 inference flag*/ |
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344 | (0 << 3) | /*Only 8x8 IDCT Transform Mode Flag*/ |
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345 | (1 << 2) | /*Frame MB only flag*/ |
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346 | (0 << 1) | /*MBAFF mode is in active*/ |
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347 | (0 << 0) ); /*Field picture flag*/ |
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348 | OUT_BCS_BATCH(batch, 0); /*Mainly about MB rate control and debug, just ignoring*/ |
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349 | OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/ |
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350 | (0xBB8 << 16) | /*InterMbMaxSz*/ |
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351 | (0xEE8) ); /*IntraMbMaxSz*/ |
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352 | OUT_BCS_BATCH(batch, 0); /*Reserved*/ |
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353 | OUT_BCS_BATCH(batch, 0); /*Slice QP Delta for bitrate control*/ |
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354 | OUT_BCS_BATCH(batch, 0); /*Slice QP Delta for bitrate control*/ |
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355 | OUT_BCS_BATCH(batch, 0x8C000000); |
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356 | OUT_BCS_BATCH(batch, 0x00010000); |
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357 | OUT_BCS_BATCH(batch, 0); |
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358 | |||
359 | ADVANCE_BCS_BATCH(batch); |
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360 | } |
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361 | |||
362 | static void |
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363 | gen7_mfc_avc_img_state(VADriverContextP ctx, |
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364 | struct gen6_encoder_context *gen6_encoder_context, |
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365 | struct intel_batchbuffer *batch) |
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366 | { |
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367 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
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368 | int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; |
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369 | int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; |
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370 | |||
371 | if (batch == NULL) |
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372 | batch = gen6_encoder_context->base.batch; |
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373 | |||
374 | BEGIN_BCS_BATCH(batch, 16); |
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375 | OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); |
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376 | OUT_BCS_BATCH(batch, |
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377 | ((width_in_mbs * height_in_mbs) & 0xFFFF)); |
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378 | OUT_BCS_BATCH(batch, |
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379 | ((height_in_mbs - 1) << 16) | |
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380 | ((width_in_mbs - 1) << 0)); |
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381 | OUT_BCS_BATCH(batch, |
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382 | (0 << 24) | /* Second Chroma QP Offset */ |
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383 | (0 << 16) | /* Chroma QP Offset */ |
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384 | (0 << 14) | /* Max-bit conformance Intra flag */ |
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385 | (0 << 13) | /* Max Macroblock size conformance Inter flag */ |
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386 | (0 << 12) | /* FIXME: Weighted_Pred_Flag */ |
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387 | (0 << 10) | /* FIXME: Weighted_BiPred_Idc */ |
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388 | (0 << 8) | /* FIXME: Image Structure */ |
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389 | (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */ |
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390 | OUT_BCS_BATCH(batch, |
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391 | (0 << 16) | /* Mininum Frame size */ |
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392 | (0 << 15) | /* Disable reading of Macroblock Status Buffer */ |
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393 | (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */ |
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394 | (0 << 13) | /* CABAC 0 word insertion test enable */ |
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395 | (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */ |
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396 | (1 << 10) | /* Chroma Format IDC, 4:2:0 */ |
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397 | (0 << 9) | /* FIXME: MbMvFormatFlag */ |
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398 | (1 << 7) | /* 0:CAVLC encoding mode,1:CABAC */ |
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399 | (0 << 6) | /* Only valid for VLD decoding mode */ |
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400 | (0 << 5) | /* Constrained Intra Predition Flag, from PPS */ |
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401 | (0 << 4) | /* Direct 8x8 inference flag */ |
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402 | (0 << 3) | /* Only 8x8 IDCT Transform Mode Flag */ |
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403 | (1 << 2) | /* Frame MB only flag */ |
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404 | (0 << 1) | /* MBAFF mode is in active */ |
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405 | (0 << 0)); /* Field picture flag */ |
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406 | OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */ |
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407 | OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */ |
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408 | (0xBB8 << 16) | /* InterMbMaxSz */ |
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409 | (0xEE8) ); /* IntraMbMaxSz */ |
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410 | OUT_BCS_BATCH(batch, 0); /* Reserved */ |
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411 | OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ |
||
412 | OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ |
||
413 | OUT_BCS_BATCH(batch, 0x8C000000); |
||
414 | OUT_BCS_BATCH(batch, 0x00010000); |
||
415 | OUT_BCS_BATCH(batch, 0); |
||
416 | OUT_BCS_BATCH(batch, 0); |
||
417 | OUT_BCS_BATCH(batch, 0); |
||
418 | OUT_BCS_BATCH(batch, 0); |
||
419 | |||
420 | ADVANCE_BCS_BATCH(batch); |
||
421 | } |
||
422 | |||
423 | static void gen6_mfc_avc_slice_state(VADriverContextP ctx, |
||
424 | int intra_slice, |
||
425 | struct gen6_encoder_context *gen6_encoder_context, |
||
426 | struct intel_batchbuffer *batch) |
||
427 | { |
||
428 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
||
429 | |||
430 | if (batch == NULL) |
||
431 | batch = gen6_encoder_context->base.batch; |
||
432 | |||
433 | BEGIN_BCS_BATCH(batch, 11);; |
||
434 | |||
435 | OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) ); |
||
436 | |||
437 | if ( intra_slice ) |
||
438 | OUT_BCS_BATCH(batch, 2); /*Slice Type: I Slice*/ |
||
439 | else |
||
440 | OUT_BCS_BATCH(batch, 0); /*Slice Type: P Slice*/ |
||
441 | |||
442 | if ( intra_slice ) |
||
443 | OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/ |
||
444 | else |
||
445 | OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/ |
||
446 | |||
447 | OUT_BCS_BATCH(batch, (0<<24) | /*Enable deblocking operation*/ |
||
448 | (26<<16) | /*Slice Quantization Parameter*/ |
||
449 | 0x0202 ); |
||
450 | OUT_BCS_BATCH(batch, 0); /*First MB X&Y , the postion of current slice*/ |
||
451 | OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) ); |
||
452 | |||
453 | OUT_BCS_BATCH(batch, |
||
454 | (0<<31) | /*RateControlCounterEnable = disable*/ |
||
455 | (1<<30) | /*ResetRateControlCounter*/ |
||
456 | (2<<28) | /*RC Triggle Mode = Loose Rate Control*/ |
||
457 | (1<<19) | /*IsLastSlice*/ |
||
458 | (0<<18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ |
||
459 | (0<<17) | /*HeaderPresentFlag*/ |
||
460 | (1<<16) | /*SliceData PresentFlag*/ |
||
461 | (0<<15) | /*TailPresentFlag*/ |
||
462 | (1<<13) | /*RBSP NAL TYPE*/ |
||
463 | (0<<12) ); /*CabacZeroWordInsertionEnable*/ |
||
464 | |||
465 | OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, |
||
466 | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, |
||
467 | mfc_context->mfc_indirect_pak_bse_object.offset); |
||
468 | |||
469 | OUT_BCS_BATCH(batch, 0); |
||
470 | OUT_BCS_BATCH(batch, 0); |
||
471 | OUT_BCS_BATCH(batch, 0); |
||
472 | |||
473 | ADVANCE_BCS_BATCH(batch); |
||
474 | } |
||
475 | static void gen6_mfc_avc_qm_state(VADriverContextP ctx, |
||
476 | struct gen6_encoder_context *gen6_encoder_context, |
||
477 | struct intel_batchbuffer *batch) |
||
478 | { |
||
479 | int i; |
||
480 | |||
481 | if (batch == NULL) |
||
482 | batch = gen6_encoder_context->base.batch; |
||
483 | |||
484 | BEGIN_BCS_BATCH(batch, 58); |
||
485 | |||
486 | OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56); |
||
487 | OUT_BCS_BATCH(batch, 0xFF ) ; |
||
488 | for( i = 0; i < 56; i++) { |
||
489 | OUT_BCS_BATCH(batch, 0x10101010); |
||
490 | } |
||
491 | |||
492 | ADVANCE_BCS_BATCH(batch); |
||
493 | } |
||
494 | |||
495 | static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, |
||
496 | struct gen6_encoder_context *gen6_encoder_context, |
||
497 | struct intel_batchbuffer *batch) |
||
498 | { |
||
499 | int i; |
||
500 | |||
501 | if (batch == NULL) |
||
502 | batch = gen6_encoder_context->base.batch; |
||
503 | |||
504 | BEGIN_BCS_BATCH(batch, 113); |
||
505 | OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2)); |
||
506 | |||
507 | for(i = 0; i < 112;i++) { |
||
508 | OUT_BCS_BATCH(batch, 0x10001000); |
||
509 | } |
||
510 | |||
511 | ADVANCE_BCS_BATCH(batch); |
||
512 | } |
||
513 | |||
514 | static void |
||
515 | gen7_mfc_qm_state(VADriverContextP ctx, |
||
516 | int qm_type, |
||
517 | unsigned int *qm, |
||
518 | int qm_length, |
||
519 | struct gen6_encoder_context *gen6_encoder_context, |
||
520 | struct intel_batchbuffer *batch) |
||
521 | { |
||
522 | unsigned int qm_buffer[16]; |
||
523 | |||
524 | if (batch == NULL) |
||
525 | batch = gen6_encoder_context->base.batch; |
||
526 | |||
527 | assert(qm_length <= 16); |
||
528 | assert(sizeof(*qm) == 4); |
||
529 | memcpy(qm_buffer, qm, qm_length * 4); |
||
530 | |||
531 | BEGIN_BCS_BATCH(batch, 18); |
||
532 | OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); |
||
533 | OUT_BCS_BATCH(batch, qm_type << 0); |
||
534 | intel_batchbuffer_data(batch, qm_buffer, 16 * 4); |
||
535 | ADVANCE_BCS_BATCH(batch); |
||
536 | } |
||
537 | |||
538 | static void gen7_mfc_avc_qm_state(VADriverContextP ctx, |
||
539 | struct gen6_encoder_context *gen6_encoder_context, |
||
540 | struct intel_batchbuffer *batch) |
||
541 | { |
||
542 | unsigned int qm[16] = { |
||
543 | 0x10101010, 0x10101010, 0x10101010, 0x10101010, |
||
544 | 0x10101010, 0x10101010, 0x10101010, 0x10101010, |
||
545 | 0x10101010, 0x10101010, 0x10101010, 0x10101010, |
||
546 | 0x10101010, 0x10101010, 0x10101010, 0x10101010 |
||
547 | }; |
||
548 | |||
549 | gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context, batch); |
||
550 | gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context, batch); |
||
551 | gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context, batch); |
||
552 | gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context, batch); |
||
553 | } |
||
554 | |||
555 | static void |
||
556 | gen7_mfc_fqm_state(VADriverContextP ctx, |
||
557 | int fqm_type, |
||
558 | unsigned int *fqm, |
||
559 | int fqm_length, |
||
560 | struct gen6_encoder_context *gen6_encoder_context, |
||
561 | struct intel_batchbuffer *batch) |
||
562 | { |
||
563 | unsigned int fqm_buffer[32]; |
||
564 | |||
565 | if (batch == NULL) |
||
566 | batch = gen6_encoder_context->base.batch; |
||
567 | |||
568 | assert(fqm_length <= 32); |
||
569 | assert(sizeof(*fqm) == 4); |
||
570 | memcpy(fqm_buffer, fqm, fqm_length * 4); |
||
571 | |||
572 | BEGIN_BCS_BATCH(batch, 34); |
||
573 | OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2)); |
||
574 | OUT_BCS_BATCH(batch, fqm_type << 0); |
||
575 | intel_batchbuffer_data(batch, fqm_buffer, 32 * 4); |
||
576 | ADVANCE_BCS_BATCH(batch); |
||
577 | } |
||
578 | |||
579 | static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, |
||
580 | struct gen6_encoder_context *gen6_encoder_context, |
||
581 | struct intel_batchbuffer *batch) |
||
582 | { |
||
583 | unsigned int qm[32] = { |
||
584 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
585 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
586 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
587 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
588 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
589 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
590 | 0x10001000, 0x10001000, 0x10001000, 0x10001000, |
||
591 | 0x10001000, 0x10001000, 0x10001000, 0x10001000 |
||
592 | }; |
||
593 | |||
594 | gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context, batch); |
||
595 | gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context, batch); |
||
596 | gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context, batch); |
||
597 | gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context, batch); |
||
598 | } |
||
599 | |||
600 | static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, |
||
601 | struct gen6_encoder_context *gen6_encoder_context, |
||
602 | struct intel_batchbuffer *batch) |
||
603 | { |
||
604 | int i; |
||
605 | |||
606 | if (batch == NULL) |
||
607 | batch = gen6_encoder_context->base.batch; |
||
608 | |||
609 | BEGIN_BCS_BATCH(batch, 10); |
||
610 | |||
611 | OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); |
||
612 | OUT_BCS_BATCH(batch, 0); //Select L0 |
||
613 | |||
614 | OUT_BCS_BATCH(batch, 0x80808000); //Only 1 reference |
||
615 | for(i = 0; i < 7; i++) { |
||
616 | OUT_BCS_BATCH(batch, 0x80808080); |
||
617 | } |
||
618 | |||
619 | ADVANCE_BCS_BATCH(batch); |
||
620 | } |
||
621 | |||
622 | static int |
||
623 | gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, |
||
624 | struct gen6_encoder_context *gen6_encoder_context, |
||
625 | struct intel_batchbuffer *batch) |
||
626 | { |
||
627 | int len_in_dwords = 11; |
||
628 | |||
629 | if (batch == NULL) |
||
630 | batch = gen6_encoder_context->base.batch; |
||
631 | |||
632 | BEGIN_BCS_BATCH(batch, len_in_dwords); |
||
633 | |||
634 | OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); |
||
635 | OUT_BCS_BATCH(batch, 0); |
||
636 | OUT_BCS_BATCH(batch, 0); |
||
637 | OUT_BCS_BATCH(batch, |
||
638 | (0 << 24) | /* PackedMvNum, Debug*/ |
||
639 | (0 << 20) | /* No motion vector */ |
||
640 | (1 << 19) | /* CbpDcY */ |
||
641 | (1 << 18) | /* CbpDcU */ |
||
642 | (1 << 17) | /* CbpDcV */ |
||
643 | (msg[0] & 0xFFFF) ); |
||
644 | |||
645 | OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ |
||
646 | OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ |
||
647 | OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ |
||
648 | |||
649 | /*Stuff for Intra MB*/ |
||
650 | OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ |
||
651 | OUT_BCS_BATCH(batch, msg[2]); |
||
652 | OUT_BCS_BATCH(batch, msg[3]&0xFC); |
||
653 | |||
654 | OUT_BCS_BATCH(batch, 0x8040000); /*MaxSizeInWord and TargetSzieInWord*/ |
||
655 | |||
656 | ADVANCE_BCS_BATCH(batch); |
||
657 | |||
658 | return len_in_dwords; |
||
659 | } |
||
660 | |||
661 | static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset, |
||
662 | struct gen6_encoder_context *gen6_encoder_context, struct intel_batchbuffer *batch) |
||
663 | { |
||
664 | int len_in_dwords = 11; |
||
665 | |||
666 | if (batch == NULL) |
||
667 | batch = gen6_encoder_context->base.batch; |
||
668 | |||
669 | BEGIN_BCS_BATCH(batch, len_in_dwords); |
||
670 | |||
671 | OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); |
||
672 | |||
673 | OUT_BCS_BATCH(batch, 32); /* 32 MV*/ |
||
674 | OUT_BCS_BATCH(batch, offset); |
||
675 | |||
676 | OUT_BCS_BATCH(batch, |
||
677 | (1 << 24) | /* PackedMvNum, Debug*/ |
||
678 | (4 << 20) | /* 8 MV, SNB don't use it*/ |
||
679 | (1 << 19) | /* CbpDcY */ |
||
680 | (1 << 18) | /* CbpDcU */ |
||
681 | (1 << 17) | /* CbpDcV */ |
||
682 | (0 << 15) | /* Transform8x8Flag = 0*/ |
||
683 | (0 << 14) | /* Frame based*/ |
||
684 | (0 << 13) | /* Inter MB */ |
||
685 | (1 << 8) | /* MbType = P_L0_16x16 */ |
||
686 | (0 << 7) | /* MBZ for frame */ |
||
687 | (0 << 6) | /* MBZ */ |
||
688 | (2 << 4) | /* MBZ for inter*/ |
||
689 | (0 << 3) | /* MBZ */ |
||
690 | (0 << 2) | /* SkipMbFlag */ |
||
691 | (0 << 0)); /* InterMbMode */ |
||
692 | |||
693 | OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ |
||
694 | OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ |
||
695 | OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ |
||
696 | |||
697 | /*Stuff for Inter MB*/ |
||
698 | OUT_BCS_BATCH(batch, 0x0); |
||
699 | OUT_BCS_BATCH(batch, 0x0); |
||
700 | OUT_BCS_BATCH(batch, 0x0); |
||
701 | |||
702 | OUT_BCS_BATCH(batch, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/ |
||
703 | |||
704 | ADVANCE_BCS_BATCH(batch); |
||
705 | |||
706 | return len_in_dwords; |
||
707 | } |
||
708 | |||
709 | static void gen6_mfc_init(VADriverContextP ctx, |
||
710 | struct encode_state *encode_state, |
||
711 | struct gen6_encoder_context *gen6_encoder_context) |
||
712 | { |
||
713 | struct i965_driver_data *i965 = i965_driver_data(ctx); |
||
714 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
||
715 | dri_bo *bo; |
||
716 | int i; |
||
717 | VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer; |
||
718 | int width_in_mbs = pSequenceParameter->picture_width_in_mbs; |
||
719 | |||
720 | /*Encode common setup for MFC*/ |
||
721 | dri_bo_unreference(mfc_context->post_deblocking_output.bo); |
||
722 | mfc_context->post_deblocking_output.bo = NULL; |
||
723 | |||
724 | dri_bo_unreference(mfc_context->pre_deblocking_output.bo); |
||
725 | mfc_context->pre_deblocking_output.bo = NULL; |
||
726 | |||
727 | dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); |
||
728 | mfc_context->uncompressed_picture_source.bo = NULL; |
||
729 | |||
730 | dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); |
||
731 | mfc_context->mfc_indirect_pak_bse_object.bo = NULL; |
||
732 | |||
733 | for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ |
||
734 | dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); |
||
735 | mfc_context->direct_mv_buffers[i].bo = NULL; |
||
736 | } |
||
737 | |||
738 | for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ |
||
739 | if (mfc_context->reference_surfaces[i].bo != NULL) |
||
740 | dri_bo_unreference(mfc_context->reference_surfaces[i].bo); |
||
741 | mfc_context->reference_surfaces[i].bo = NULL; |
||
742 | } |
||
743 | |||
744 | dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); |
||
745 | bo = dri_bo_alloc(i965->intel.bufmgr, |
||
746 | "Buffer", |
||
747 | width_in_mbs * 64, |
||
748 | 64); |
||
749 | assert(bo); |
||
750 | mfc_context->intra_row_store_scratch_buffer.bo = bo; |
||
751 | |||
752 | dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); |
||
753 | bo = dri_bo_alloc(i965->intel.bufmgr, |
||
754 | "Buffer", |
||
755 | 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */ |
||
756 | 64); |
||
757 | assert(bo); |
||
758 | mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo; |
||
759 | |||
760 | dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); |
||
761 | bo = dri_bo_alloc(i965->intel.bufmgr, |
||
762 | "Buffer", |
||
763 | 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */ |
||
764 | 0x1000); |
||
765 | assert(bo); |
||
766 | mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo; |
||
767 | } |
||
768 | |||
769 | void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx, |
||
770 | struct encode_state *encode_state, |
||
771 | struct gen6_encoder_context *gen6_encoder_context) |
||
772 | { |
||
773 | struct i965_driver_data *i965 = i965_driver_data(ctx); |
||
774 | struct intel_batchbuffer *main_batch = gen6_encoder_context->base.batch; |
||
775 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
||
776 | struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context; |
||
777 | VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer; |
||
778 | VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer; /* FIXME: multi slices */ |
||
779 | unsigned int *msg = NULL, offset = 0; |
||
780 | int emit_new_state = 1, object_len_in_bytes; |
||
781 | int is_intra = pSliceParameter->slice_flags.bits.is_intra; |
||
782 | int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; |
||
783 | int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; |
||
784 | int x,y; |
||
785 | struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, width_in_mbs * height_in_mbs * 12 * 4 + 0x800); |
||
786 | |||
787 | intel_batchbuffer_start_atomic_bcs(batch, width_in_mbs * height_in_mbs * 12 * 4 + 0x700); |
||
788 | |||
789 | if (is_intra) { |
||
790 | dri_bo_map(vme_context->vme_output.bo , 1); |
||
791 | msg = (unsigned int *)vme_context->vme_output.bo->virtual; |
||
792 | } |
||
793 | |||
794 | for (y = 0; y < height_in_mbs; y++) { |
||
795 | for (x = 0; x < width_in_mbs; x++) { |
||
796 | int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) ); |
||
797 | int qp = pSequenceParameter->initial_qp; |
||
798 | |||
799 | if (emit_new_state) { |
||
800 | intel_batchbuffer_emit_mi_flush(batch); |
||
801 | |||
802 | if (IS_GEN7(i965->intel.device_id)) { |
||
803 | gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context, batch); |
||
804 | gen7_mfc_surface_state(ctx, gen6_encoder_context, batch); |
||
805 | gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch); |
||
806 | } else { |
||
807 | gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context, batch); |
||
808 | gen6_mfc_surface_state(ctx, gen6_encoder_context, batch); |
||
809 | gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch); |
||
810 | } |
||
811 | |||
812 | gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context, batch); |
||
813 | gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context, batch); |
||
814 | |||
815 | if (IS_GEN7(i965->intel.device_id)) { |
||
816 | gen7_mfc_avc_img_state(ctx, gen6_encoder_context, batch); |
||
817 | gen7_mfc_avc_qm_state(ctx, gen6_encoder_context, batch); |
||
818 | gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch); |
||
819 | } else { |
||
820 | gen6_mfc_avc_img_state(ctx, gen6_encoder_context, batch); |
||
821 | gen6_mfc_avc_qm_state(ctx, gen6_encoder_context, batch); |
||
822 | gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch); |
||
823 | } |
||
824 | |||
825 | gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context, batch); |
||
826 | gen6_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context, batch); |
||
827 | emit_new_state = 0; |
||
828 | } |
||
829 | |||
830 | if (is_intra) { |
||
831 | assert(msg); |
||
832 | object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context, batch); |
||
833 | msg += 4; |
||
834 | } else { |
||
835 | object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context, batch); |
||
836 | offset += 64; |
||
837 | } |
||
838 | |||
839 | if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) { |
||
840 | intel_batchbuffer_end_atomic(batch); |
||
841 | intel_batchbuffer_flush(batch); |
||
842 | emit_new_state = 1; |
||
843 | intel_batchbuffer_start_atomic_bcs(batch, 0x1000); |
||
844 | } |
||
845 | } |
||
846 | } |
||
847 | |||
848 | if (is_intra) |
||
849 | dri_bo_unmap(vme_context->vme_output.bo); |
||
850 | |||
851 | intel_batchbuffer_align(batch, 8); |
||
852 | |||
853 | BEGIN_BCS_BATCH(batch, 2); |
||
854 | OUT_BCS_BATCH(batch, 0); |
||
855 | OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); |
||
856 | ADVANCE_BCS_BATCH(batch); |
||
857 | |||
858 | intel_batchbuffer_end_atomic(batch); |
||
859 | |||
860 | /* chain to the main batch buffer */ |
||
861 | intel_batchbuffer_start_atomic_bcs(main_batch, 0x100); |
||
862 | intel_batchbuffer_emit_mi_flush(main_batch); |
||
863 | BEGIN_BCS_BATCH(main_batch, 2); |
||
864 | OUT_BCS_BATCH(main_batch, MI_BATCH_BUFFER_START | (1 << 8)); |
||
865 | OUT_BCS_RELOC(main_batch, |
||
866 | batch->buffer, |
||
867 | I915_GEM_DOMAIN_COMMAND, 0, |
||
868 | 0); |
||
869 | ADVANCE_BCS_BATCH(main_batch); |
||
870 | intel_batchbuffer_end_atomic(main_batch); |
||
871 | |||
872 | // end programing |
||
873 | intel_batchbuffer_free(batch); |
||
874 | } |
||
875 | |||
876 | static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx, |
||
877 | struct encode_state *encode_state, |
||
878 | struct gen6_encoder_context *gen6_encoder_context) |
||
879 | { |
||
880 | struct i965_driver_data *i965 = i965_driver_data(ctx); |
||
881 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
||
882 | struct object_surface *obj_surface; |
||
883 | struct object_buffer *obj_buffer; |
||
884 | dri_bo *bo; |
||
885 | VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer; |
||
886 | VAStatus vaStatus = VA_STATUS_SUCCESS; |
||
887 | |||
888 | /*Setup all the input&output object*/ |
||
889 | obj_surface = SURFACE(pPicParameter->reconstructed_picture); |
||
890 | assert(obj_surface); |
||
891 | i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); |
||
892 | mfc_context->post_deblocking_output.bo = obj_surface->bo; |
||
893 | dri_bo_reference(mfc_context->post_deblocking_output.bo); |
||
894 | |||
895 | mfc_context->surface_state.width = obj_surface->orig_width; |
||
896 | mfc_context->surface_state.height = obj_surface->orig_height; |
||
897 | mfc_context->surface_state.w_pitch = obj_surface->width; |
||
898 | mfc_context->surface_state.h_pitch = obj_surface->height; |
||
899 | |||
900 | obj_surface = SURFACE(pPicParameter->reference_picture); |
||
901 | assert(obj_surface); |
||
902 | if (obj_surface->bo != NULL) { |
||
903 | mfc_context->reference_surfaces[0].bo = obj_surface->bo; |
||
904 | dri_bo_reference(obj_surface->bo); |
||
905 | } |
||
906 | |||
907 | obj_surface = SURFACE(encode_state->current_render_target); |
||
908 | assert(obj_surface && obj_surface->bo); |
||
909 | mfc_context->uncompressed_picture_source.bo = obj_surface->bo; |
||
910 | dri_bo_reference(mfc_context->uncompressed_picture_source.bo); |
||
911 | |||
912 | obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */ |
||
913 | bo = obj_buffer->buffer_store->bo; |
||
914 | assert(bo); |
||
915 | mfc_context->mfc_indirect_pak_bse_object.bo = bo; |
||
916 | mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64); |
||
917 | dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo); |
||
918 | |||
919 | /*Programing bcs pipeline*/ |
||
920 | gen6_mfc_avc_pipeline_programing(ctx, encode_state, gen6_encoder_context); //filling the pipeline |
||
921 | |||
922 | return vaStatus; |
||
923 | } |
||
924 | |||
925 | static VAStatus gen6_mfc_run(VADriverContextP ctx, |
||
926 | struct encode_state *encode_state, |
||
927 | struct gen6_encoder_context *gen6_encoder_context) |
||
928 | { |
||
929 | struct intel_batchbuffer *batch = gen6_encoder_context->base.batch; |
||
930 | |||
931 | intel_batchbuffer_flush(batch); //run the pipeline |
||
932 | |||
933 | return VA_STATUS_SUCCESS; |
||
934 | } |
||
935 | |||
936 | static VAStatus gen6_mfc_stop(VADriverContextP ctx, |
||
937 | struct encode_state *encode_state, |
||
938 | struct gen6_encoder_context *gen6_encoder_context) |
||
939 | { |
||
940 | #if 0 |
||
941 | struct i965_driver_data *i965 = i965_driver_data(ctx); |
||
942 | struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context; |
||
943 | |||
944 | VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer; |
||
945 | |||
946 | struct object_surface *obj_surface = SURFACE(pPicParameter->reconstructed_picture); |
||
947 | //struct object_surface *obj_surface = SURFACE(pPicParameter->reference_picture[0]); |
||
948 | //struct object_surface *obj_surface = SURFACE(encode_state->current_render_target); |
||
949 | my_debug(obj_surface); |
||
950 | |||
951 | #endif |
||
952 | |||
953 | return VA_STATUS_SUCCESS; |
||
954 | } |
||
955 | |||
956 | static VAStatus |
||
957 | gen6_mfc_avc_encode_picture(VADriverContextP ctx, |
||
958 | struct encode_state *encode_state, |
||
959 | struct gen6_encoder_context *gen6_encoder_context) |
||
960 | { |
||
961 | gen6_mfc_init(ctx, encode_state, gen6_encoder_context); |
||
962 | gen6_mfc_avc_prepare(ctx, encode_state, gen6_encoder_context); |
||
963 | gen6_mfc_run(ctx, encode_state, gen6_encoder_context); |
||
964 | gen6_mfc_stop(ctx, encode_state, gen6_encoder_context); |
||
965 | |||
966 | return VA_STATUS_SUCCESS; |
||
967 | } |
||
968 | |||
969 | VAStatus |
||
970 | gen6_mfc_pipeline(VADriverContextP ctx, |
||
971 | VAProfile profile, |
||
972 | struct encode_state *encode_state, |
||
973 | struct gen6_encoder_context *gen6_encoder_context) |
||
974 | { |
||
975 | VAStatus vaStatus; |
||
976 | |||
977 | switch (profile) { |
||
978 | case VAProfileH264Baseline: |
||
979 | vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, gen6_encoder_context); |
||
980 | break; |
||
981 | |||
982 | /* FIXME: add for other profile */ |
||
983 | default: |
||
984 | vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; |
||
985 | break; |
||
986 | } |
||
987 | |||
988 | return vaStatus; |
||
989 | } |
||
990 | |||
991 | Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context) |
||
992 | { |
||
993 | return True; |
||
994 | } |
||
995 | |||
996 | Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context) |
||
997 | { |
||
998 | int i; |
||
999 | |||
1000 | dri_bo_unreference(mfc_context->post_deblocking_output.bo); |
||
1001 | mfc_context->post_deblocking_output.bo = NULL; |
||
1002 | |||
1003 | dri_bo_unreference(mfc_context->pre_deblocking_output.bo); |
||
1004 | mfc_context->pre_deblocking_output.bo = NULL; |
||
1005 | |||
1006 | dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); |
||
1007 | mfc_context->uncompressed_picture_source.bo = NULL; |
||
1008 | |||
1009 | dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); |
||
1010 | mfc_context->mfc_indirect_pak_bse_object.bo = NULL; |
||
1011 | |||
1012 | for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ |
||
1013 | dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); |
||
1014 | mfc_context->direct_mv_buffers[i].bo = NULL; |
||
1015 | } |
||
1016 | |||
1017 | dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); |
||
1018 | mfc_context->intra_row_store_scratch_buffer.bo = NULL; |
||
1019 | |||
1020 | dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); |
||
1021 | mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; |
||
1022 | |||
1023 | dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); |
||
1024 | mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; |
||
1025 | |||
1026 | return True; |
||
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